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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.19 root 10: * This file is distributed under the GNU General Public License, version 2
11: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
1.1.1.19 root 49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after instruction 'n' was processed, the */
1.1.1.12 root 50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
1.1.1.19 root 83: /* interrupt that would exit the STOP state immediately, without doing a 'while' */
1.1.1.14 root 84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.17 root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
112: /* exception if it's the case. */
1.1.1.20 root 113: /* 2012/09/01 [NP] Add a special case to correct the stacked PC when a bus error happens during */
114: /* a movem (fix the game Blood Money). */
115: /* 2013/03/16 [NP] In refill_prefetch(), reload only one new word in regs.prefetch if low word is */
116: /* still valid : low word goes to high word and we reload only low word */
117: /* (fix EOR/ADD self modified code in the protection for the game Damocles). */
1.1.1.19 root 118: /* 2013/04/11 [NP] In Exception(), call MFP_ProcessIACK after 12 cycles to update the MFP's vector */
119: /* number used for the exception (see mfp.c). */
120: /* 2013/05/03 [NP] In Exception(), handle IACK for HBL and VBL interrupts too, allowing pending bit*/
121: /* to be set twice during an active video interrupt (correct fix for Super Monaco */
122: /* GP, Super Hang On, Monster Business, European Demo's Intro, BBC Menu 52). */
1.1.1.20 root 123: /* 2014/02/22 [NP] In Exception(), call valid_address() before reading the opcode at BusErrorPC, */
124: /* else this will cause an unwanted "double bus error" ("Union Demo" loader). */
125: /* 2014/02/22 [NP] In refill_prefetch(), use get_word() instead of do_get_mem_word() to generate */
126: /* a bus error when trying to read from an invalid region. */
127: /* 2014/03/18 [NP] In Exception(), add a specific case to restore the dest part of a "move" after */
128: /* it was overwritten during a bus error (fix the game Dragon Flight). */
129: /* 2014/04/06 [NP] In Exception(), add a special case for last_addr_for_exception_3 stored in the */
130: /* stack after a bus error (fix the game Batman The Movie). */
1.1.1.21 root 131: /* 2014/09/07 [NP] In m68k_run_1(), if get_iword_prefetch() triggers a bus error, we must call the */
132: /* bus error immediately and fetch the correct opcode for the bus error handler */
133: /* (fix Blood Money on Superior 65, PC=4e664e66 after RTS). */
134: /* 2014/09/07 [NP] For address error, store if the access was in cpu space or data space and fix */
135: /* the exception stack frame accordingly (fix Blood Money on Superior 65, */
136: /* PC=4e664e66 after RTS) */
137: /* 2015/02/11 [NP] Replace BusErrorPC by regs.instruction_pc, to get similar code to WinUAE's cpu */
138:
1.1.1.12 root 139:
1.1.1.15 root 140: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 141:
142: #include "sysdeps.h"
143: #include "hatari-glue.h"
144: #include "maccess.h"
145: #include "memory.h"
146: #include "newcpu.h"
1.1.1.16 root 147: #include "main.h"
148: #include "m68000.h"
1.1.1.21 root 149: #include "reset.h"
1.1.1.16 root 150: #include "cycInt.h"
151: #include "mfp.h"
152: #include "tos.h"
153: #include "vdi.h"
154: #include "cart.h"
155: #include "dialog.h"
156: #include "bios.h"
157: #include "xbios.h"
1.1.1.17 root 158: #include "screen.h"
1.1.1.16 root 159: #include "video.h"
160: #include "options.h"
161: #include "dsp.h"
162: #include "log.h"
163: #include "debugui.h"
164: #include "debugcpu.h"
1.1.1.17 root 165: #include "68kDisass.h"
1.1.1.22! root 166: #include "stMemory.h"
1.1 root 167:
1.1.1.20 root 168: #ifdef HAVE_CAPSIMAGE
169: #if CAPSIMAGE_VERSION == 5
170: #include <caps5/CapsLibAll.h>
171: #endif
172: #endif
173:
1.1.1.12 root 174: //#define DEBUG_PREFETCH
1.1 root 175:
176: struct flag_struct regflags;
177:
178: /* Opcode of faulting instruction */
179: uae_u16 last_op_for_exception_3;
180: /* PC at fault time */
181: uaecptr last_addr_for_exception_3;
182: /* Address that generated the exception */
183: uaecptr last_fault_for_exception_3;
1.1.1.21 root 184: /* read (0) or write (1) access */
185: int last_writeaccess_for_exception_3;
186: /* instruction (1) or data (0) access */
187: int last_instructionaccess_for_exception_3;
1.1 root 188:
1.1.1.11 root 189: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
190: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 191:
192: int movem_index1[256];
193: int movem_index2[256];
194: int movem_next[256];
195:
196: int fpp_movem_index1[256];
197: int fpp_movem_index2[256];
198: int fpp_movem_next[256];
199:
200: cpuop_func *cpufunctbl[65536];
201:
1.1.1.12 root 202: int OpcodeFamily;
1.1.1.16 root 203: int BusCyclePenalty = 0;
1.1.1.6 root 204:
1.1 root 205: #define COUNT_INSTRS 0
206:
207: #if COUNT_INSTRS
208: static unsigned long int instrcount[65536];
209: static uae_u16 opcodenums[65536];
210:
211: static int compfn (const void *el1, const void *el2)
212: {
213: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
214: }
215:
216: static char *icountfilename (void)
217: {
218: char *name = getenv ("INSNCOUNT");
219: if (name)
220: return name;
221: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
222: }
223:
224: void dump_counts (void)
225: {
226: FILE *f = fopen (icountfilename (), "w");
227: unsigned long int total;
228: int i;
229:
230: write_log ("Writing instruction count file...\n");
231: for (i = 0; i < 65536; i++) {
232: opcodenums[i] = i;
233: total += instrcount[i];
234: }
235: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
236:
237: fprintf (f, "Total: %lu\n", total);
238: for (i=0; i < 65536; i++) {
239: unsigned long int cnt = instrcount[opcodenums[i]];
240: struct instr *dp;
241: struct mnemolookup *lookup;
242: if (!cnt)
243: break;
244: dp = table68k + opcodenums[i];
245: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
246: ;
247: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
248: }
249: fclose (f);
250: }
251: #else
252: void dump_counts (void)
253: {
254: }
255: #endif
256:
1.1.1.21 root 257: static void cpu_halt ( void )
258: {
259: Dialog_HaltDlg();
260: }
261:
1.1 root 262:
263: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
264:
265: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
266: {
1.1.1.6 root 267: op_illg (opcode);
1.1 root 268: return 4;
269: }
270:
1.1.1.4 root 271:
272: void build_cpufunctbl(void)
1.1 root 273: {
274: int i;
275: unsigned long opcode;
1.1.1.12 root 276: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
277: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
278: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
279: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
280: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 281: : op_smalltbl_5_ff);
1.1 root 282:
1.1.1.10 root 283: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 284: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 285:
286: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 287: cpufunctbl[opcode] = op_illg_1;
1.1 root 288: for (i = 0; tbl[i].handler != NULL; i++) {
289: if (! tbl[i].specific)
1.1.1.6 root 290: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 291: }
292: for (opcode = 0; opcode < 65536; opcode++) {
293: cpuop_func *f;
294:
1.1.1.12 root 295: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 296: continue;
297:
298: if (table68k[opcode].handler != -1) {
1.1.1.6 root 299: f = cpufunctbl[table68k[opcode].handler];
1.1 root 300: if (f == op_illg_1)
301: abort();
1.1.1.6 root 302: cpufunctbl[opcode] = f;
1.1 root 303: }
304: }
305: for (i = 0; tbl[i].handler != NULL; i++) {
306: if (tbl[i].specific)
1.1.1.6 root 307: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 308: }
309: }
310:
311:
312:
313: void init_m68k (void)
314: {
315: int i;
316:
317: for (i = 0 ; i < 256 ; i++) {
318: int j;
319: for (j = 0 ; j < 8 ; j++) {
320: if (i & (1 << j)) break;
321: }
322: movem_index1[i] = j;
323: movem_index2[i] = 7-j;
324: movem_next[i] = i & (~(1 << j));
325: }
326: for (i = 0 ; i < 256 ; i++) {
327: int j;
328: for (j = 7 ; j >= 0 ; j--) {
329: if (i & (1 << j)) break;
330: }
331: fpp_movem_index1[i] = 7-j;
332: fpp_movem_index2[i] = j;
333: fpp_movem_next[i] = i & (~(1 << j));
334: }
335: #if COUNT_INSTRS
336: {
337: FILE *f = fopen (icountfilename (), "r");
338: memset (instrcount, 0, sizeof instrcount);
339: if (f) {
340: uae_u32 opcode, count, total;
341: char name[20];
342: write_log ("Reading instruction count file...\n");
343: fscanf (f, "Total: %lu\n", &total);
344: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
345: instrcount[opcode] = count;
346: }
347: fclose(f);
348: }
349: }
350: #endif
351: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 352: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 353: write_log ("EC");
1.1.1.12 root 354: switch (currprefs.cpu_level) {
1.1 root 355: case 1:
356: write_log ("010");
357: break;
358: case 2:
359: write_log ("020");
360: break;
361: case 3:
362: write_log ("020/881");
363: break;
364: case 4:
365: /* Who is going to miss the MMU anyway...? :-) */
366: write_log ("040");
367: break;
368: default:
369: write_log ("000");
370: break;
371: }
1.1.1.12 root 372: if (currprefs.cpu_compatible)
1.1 root 373: write_log (" (compatible mode)");
374: write_log ("\n");
1.1.1.7 root 375:
1.1 root 376: read_table68k ();
377: do_merges ();
378:
1.1.1.10 root 379: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 380:
381: build_cpufunctbl ();
382: }
383:
1.1.1.4 root 384:
1.1.1.8 root 385: /* not used ATM:
1.1 root 386: static struct regstruct regs_backup[16];
387: static int backup_pointer = 0;
1.1.1.10 root 388: struct regstruct lastint_regs;
389: int lastint_no;
1.1.1.8 root 390: */
1.1.1.10 root 391: struct regstruct regs;
1.1 root 392: static long int m68kpc_offset;
1.1.1.10 root 393:
1.1 root 394:
1.1.1.22! root 395: #define get_ibyte_1(o) STMemory_ReadByte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
! 396: #define get_iword_1(o) STMemory_ReadWord(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
! 397: #define get_ilong_1(o) STMemory_ReadLong(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
1.1 root 398:
399: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
400: {
401: uae_u16 dp;
402: uae_s8 disp8;
403: uae_s16 disp16;
404: int r;
405: uae_u32 dispreg;
406: uaecptr addr;
407: uae_s32 offset = 0;
408: char buffer[80];
409:
410: switch (mode){
411: case Dreg:
412: sprintf (buffer,"D%d", reg);
413: break;
414: case Areg:
415: sprintf (buffer,"A%d", reg);
416: break;
417: case Aind:
418: sprintf (buffer,"(A%d)", reg);
419: break;
420: case Aipi:
421: sprintf (buffer,"(A%d)+", reg);
422: break;
423: case Apdi:
424: sprintf (buffer,"-(A%d)", reg);
425: break;
426: case Ad16:
427: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
428: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
429: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
430: (unsigned long)addr);
431: break;
432: case Ad8r:
433: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
434: disp8 = dp & 0xFF;
435: r = (dp & 0x7000) >> 12;
436: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
437: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
438: dispreg <<= (dp >> 9) & 3;
439:
440: if (dp & 0x100) {
441: uae_s32 outer = 0, disp = 0;
442: uae_s32 base = m68k_areg(regs,reg);
443: char name[10];
444: sprintf (name,"A%d, ",reg);
445: if (dp & 0x80) { base = 0; name[0] = 0; }
446: if (dp & 0x40) dispreg = 0;
447: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
448: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
449: base += disp;
450:
451: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
452: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
453:
454: if (!(dp & 4)) base += dispreg;
455: if (dp & 3) base = get_long (base);
456: if (dp & 4) base += dispreg;
457:
458: addr = base + outer;
459: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
460: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
461: 1 << ((dp >> 9) & 3),
1.1.1.5 root 462: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 463: } else {
464: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
465: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
466: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
467: 1 << ((dp >> 9) & 3), disp8,
468: (unsigned long)addr);
469: }
470: break;
471: case PC16:
472: addr = m68k_getpc () + m68kpc_offset;
473: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
474: addr += (uae_s16)disp16;
475: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
476: break;
477: case PC8r:
478: addr = m68k_getpc () + m68kpc_offset;
479: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
480: disp8 = dp & 0xFF;
481: r = (dp & 0x7000) >> 12;
482: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
483: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
484: dispreg <<= (dp >> 9) & 3;
485:
486: if (dp & 0x100) {
487: uae_s32 outer = 0,disp = 0;
488: uae_s32 base = addr;
489: char name[10];
490: sprintf (name,"PC, ");
491: if (dp & 0x80) { base = 0; name[0] = 0; }
492: if (dp & 0x40) dispreg = 0;
493: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
494: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
495: base += disp;
496:
497: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
498: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
499:
500: if (!(dp & 4)) base += dispreg;
501: if (dp & 3) base = get_long (base);
502: if (dp & 4) base += dispreg;
503:
504: addr = base + outer;
505: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
506: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
507: 1 << ((dp >> 9) & 3),
1.1.1.5 root 508: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 509: } else {
510: addr += (uae_s32)((uae_s8)disp8) + dispreg;
511: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
512: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
513: disp8, (unsigned long)addr);
514: }
515: break;
516: case absw:
517: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
518: m68kpc_offset += 2;
519: break;
520: case absl:
521: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
522: m68kpc_offset += 4;
523: break;
524: case imm:
525: switch (size){
526: case sz_byte:
527: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
528: m68kpc_offset += 2;
529: break;
530: case sz_word:
531: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
532: m68kpc_offset += 2;
533: break;
534: case sz_long:
535: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
536: m68kpc_offset += 4;
537: break;
538: default:
539: break;
540: }
541: break;
542: case imm0:
543: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
544: m68kpc_offset += 2;
545: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
546: break;
547: case imm1:
548: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
549: m68kpc_offset += 2;
550: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
551: break;
552: case imm2:
553: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
554: m68kpc_offset += 4;
555: sprintf (buffer,"#$%08lx", (unsigned long)offset);
556: break;
557: case immi:
558: offset = (uae_s32)(uae_s8)(reg & 0xff);
559: sprintf (buffer,"#$%08lx", (unsigned long)offset);
560: break;
561: default:
562: break;
563: }
564: if (buf == 0)
565: fprintf (f, "%s", buffer);
566: else
567: strcat (buf, buffer);
568: return offset;
569: }
570:
1.1.1.8 root 571:
1.1 root 572: /* The plan is that this will take over the job of exception 3 handling -
573: * the CPU emulation functions will just do a longjmp to m68k_go whenever
574: * they hit an odd address. */
1.1.1.8 root 575: #if 0
1.1 root 576: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
577: {
578: uae_u16 dp;
579: uae_s8 disp8;
580: uae_s16 disp16;
581: int r;
582: uae_u32 dispreg;
583: uaecptr addr;
1.1.1.5 root 584: /*uae_s32 offset = 0;*/
1.1 root 585:
586: switch (mode){
587: case Dreg:
588: *val = m68k_dreg (regs, reg);
589: return 1;
590: case Areg:
591: *val = m68k_areg (regs, reg);
592: return 1;
593:
594: case Aind:
595: case Aipi:
596: addr = m68k_areg (regs, reg);
597: break;
598: case Apdi:
599: addr = m68k_areg (regs, reg);
600: break;
601: case Ad16:
602: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
603: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
604: break;
605: case Ad8r:
606: addr = m68k_areg (regs, reg);
607: d8r_common:
608: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
609: disp8 = dp & 0xFF;
610: r = (dp & 0x7000) >> 12;
611: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
612: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
613: dispreg <<= (dp >> 9) & 3;
614:
615: if (dp & 0x100) {
616: uae_s32 outer = 0, disp = 0;
617: uae_s32 base = addr;
618: if (dp & 0x80) base = 0;
619: if (dp & 0x40) dispreg = 0;
620: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
621: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
622: base += disp;
623:
624: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
625: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
626:
627: if (!(dp & 4)) base += dispreg;
628: if (dp & 3) base = get_long (base);
629: if (dp & 4) base += dispreg;
630:
631: addr = base + outer;
632: } else {
633: addr += (uae_s32)((uae_s8)disp8) + dispreg;
634: }
635: break;
636: case PC16:
637: addr = m68k_getpc () + m68kpc_offset;
638: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
639: addr += (uae_s16)disp16;
640: break;
641: case PC8r:
642: addr = m68k_getpc () + m68kpc_offset;
643: goto d8r_common;
644: case absw:
645: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
646: m68kpc_offset += 2;
647: break;
648: case absl:
649: addr = get_ilong_1 (m68kpc_offset);
650: m68kpc_offset += 4;
651: break;
652: case imm:
653: switch (size){
654: case sz_byte:
655: *val = get_iword_1 (m68kpc_offset) & 0xff;
656: m68kpc_offset += 2;
657: break;
658: case sz_word:
659: *val = get_iword_1 (m68kpc_offset) & 0xffff;
660: m68kpc_offset += 2;
661: break;
662: case sz_long:
663: *val = get_ilong_1 (m68kpc_offset);
664: m68kpc_offset += 4;
665: break;
666: default:
667: break;
668: }
669: return 1;
670: case imm0:
671: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
672: m68kpc_offset += 2;
673: return 1;
674: case imm1:
675: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
676: m68kpc_offset += 2;
677: return 1;
678: case imm2:
679: *val = get_ilong_1 (m68kpc_offset);
680: m68kpc_offset += 4;
681: return 1;
682: case immi:
683: *val = (uae_s32)(uae_s8)(reg & 0xff);
684: return 1;
685: default:
686: addr = 0;
687: break;
688: }
689: if ((addr & 1) == 0)
690: return 1;
691:
692: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
693: last_fault_for_exception_3 = addr;
694: return 0;
695: }
1.1.1.8 root 696: #endif
697:
1.1 root 698:
699: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
700: {
701: int reg = (dp >> 12) & 15;
702: uae_s32 regd = regs.regs[reg];
703: if ((dp & 0x800) == 0)
704: regd = (uae_s32)(uae_s16)regd;
705: regd <<= (dp >> 9) & 3;
706: if (dp & 0x100) {
707: uae_s32 outer = 0;
708: if (dp & 0x80) base = 0;
709: if (dp & 0x40) regd = 0;
710:
711: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
712: if ((dp & 0x30) == 0x30) base += next_ilong();
713:
714: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
715: if ((dp & 0x3) == 0x3) outer = next_ilong();
716:
717: if ((dp & 0x4) == 0) base += regd;
718: if (dp & 0x3) base = get_long (base);
719: if (dp & 0x4) base += regd;
720:
721: return base + outer;
722: } else {
723: return base + (uae_s32)((uae_s8)dp) + regd;
724: }
725: }
726:
727: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
728: {
729: int reg = (dp >> 12) & 15;
730: uae_s32 regd = regs.regs[reg];
731: #if 1
732: if ((dp & 0x800) == 0)
733: regd = (uae_s32)(uae_s16)regd;
734: return base + (uae_s8)dp + regd;
735: #else
736: /* Branch-free code... benchmark this again now that
737: * things are no longer inline. */
738: uae_s32 regd16;
739: uae_u32 mask;
740: mask = ((dp & 0x800) >> 11) - 1;
741: regd16 = (uae_s32)(uae_s16)regd;
742: regd16 &= mask;
743: mask = ~mask;
744: base += (uae_s8)dp;
745: regd &= mask;
746: regd |= regd16;
747: return base + regd;
748: #endif
749: }
750:
1.1.1.8 root 751:
752: /* Create the Status Register from the flags */
1.1 root 753: void MakeSR (void)
754: {
755: #if 0
756: assert((regs.t1 & 1) == regs.t1);
757: assert((regs.t0 & 1) == regs.t0);
758: assert((regs.s & 1) == regs.s);
759: assert((regs.m & 1) == regs.m);
760: assert((XFLG & 1) == XFLG);
761: assert((NFLG & 1) == NFLG);
762: assert((ZFLG & 1) == ZFLG);
763: assert((VFLG & 1) == VFLG);
764: assert((CFLG & 1) == CFLG);
765: #endif
766: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
767: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
768: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
769: | GET_CFLG);
770: }
771:
1.1.1.8 root 772:
773: /* Set up the flags from Status Register */
1.1 root 774: void MakeFromSR (void)
775: {
776: int oldm = regs.m;
777: int olds = regs.s;
778:
779: regs.t1 = (regs.sr >> 15) & 1;
780: regs.t0 = (regs.sr >> 14) & 1;
781: regs.s = (regs.sr >> 13) & 1;
782: regs.m = (regs.sr >> 12) & 1;
783: regs.intmask = (regs.sr >> 8) & 7;
784: SET_XFLG ((regs.sr >> 4) & 1);
785: SET_NFLG ((regs.sr >> 3) & 1);
786: SET_ZFLG ((regs.sr >> 2) & 1);
787: SET_VFLG ((regs.sr >> 1) & 1);
788: SET_CFLG (regs.sr & 1);
1.1.1.12 root 789: if (currprefs.cpu_level >= 2) {
1.1 root 790: if (olds != regs.s) {
791: if (olds) {
792: if (oldm)
793: regs.msp = m68k_areg(regs, 7);
794: else
795: regs.isp = m68k_areg(regs, 7);
796: m68k_areg(regs, 7) = regs.usp;
797: } else {
798: regs.usp = m68k_areg(regs, 7);
799: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
800: }
801: } else if (olds && oldm != regs.m) {
802: if (oldm) {
803: regs.msp = m68k_areg(regs, 7);
804: m68k_areg(regs, 7) = regs.isp;
805: } else {
806: regs.isp = m68k_areg(regs, 7);
807: m68k_areg(regs, 7) = regs.msp;
808: }
809: }
810: } else {
1.1.1.12 root 811: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
812: regs.t0 = 0;
813: regs.m = 0;
814:
1.1 root 815: if (olds != regs.s) {
816: if (olds) {
817: regs.isp = m68k_areg(regs, 7);
818: m68k_areg(regs, 7) = regs.usp;
819: } else {
820: regs.usp = m68k_areg(regs, 7);
821: m68k_areg(regs, 7) = regs.isp;
822: }
823: }
824: }
825:
1.1.1.8 root 826: /* Pending interrupts can occur again after a write to the SR: */
827: set_special (SPCFLAG_DOINT);
1.1 root 828: if (regs.t1 || regs.t0)
829: set_special (SPCFLAG_TRACE);
830: else
1.1.1.6 root 831: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
832: SR-modifying instructions (including STOP). */
833: unset_special (SPCFLAG_TRACE);
1.1 root 834: }
835:
1.1.1.5 root 836:
1.1.1.12 root 837: static void exception_trace (int nr)
838: {
839: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
840: if (regs.t1 && !regs.t0) {
841: /* trace stays pending if exception is div by zero, chk,
842: * trapv or trap #x
843: */
844: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
845: set_special (SPCFLAG_DOTRACE);
846: }
847: regs.t1 = regs.t0 = regs.m = 0;
848: }
849:
850:
1.1.1.14 root 851: /*
852: * Compute the number of jitter cycles to add when a video interrupt occurs
853: * (this is specific to the Atari ST)
854: */
855: static void InterruptAddJitter (int Level , int Pending)
856: {
857: int cycles = 0;
858:
859: if ( Level == 2 ) /* HBL */
860: {
861: if ( Pending )
862: cycles = HblJitterArrayPending[ HblJitterIndex ];
863: else
864: cycles = HblJitterArray[ HblJitterIndex ];
865: }
866:
867: else if ( Level == 4 ) /* VBL */
868: {
869: if ( Pending )
870: cycles = VblJitterArrayPending[ VblJitterIndex ];
871: else
872: cycles = VblJitterArray[ VblJitterIndex ];
873: }
874:
875: //fprintf ( stderr , "jitter %d\n" , cycles );
876: //cycles=0;
877: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
878: M68000_AddCycles ( cycles );
879: }
880:
881:
1.1.1.13 root 882: /* Handle exceptions. We need a special case to handle MFP exceptions */
883: /* on Atari ST, because it's possible to change the MFP's vector base */
884: /* and get a conflict with 'normal' cpu exceptions. */
885: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 886: {
1.1.1.17 root 887: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 888:
1.1.1.2 root 889: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 890:
1.1.1.19 root 891: /* Pending bits / vector number can change before the end of the IACK sequence. */
892: /* We need to handle MFP and HBL/VBL cases for this. */
893: if ( ExceptionSource == M68000_EXC_SRC_INT_MFP )
894: {
1.1.1.21 root 895: M68000_AddCycles ( CPU_IACK_CYCLES_START+CPU_IACK_CYCLES_MFP );
1.1.1.19 root 896: CPU_IACK = true;
897: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
898: CALL_VAR(PendingInterruptFunction);
899: nr = MFP_ProcessIACK ( nr );
900: CPU_IACK = false;
901: }
1.1.1.20 root 902: else if ( ( ExceptionSource == M68000_EXC_SRC_AUTOVEC ) && ( ( nr == 26 ) || ( nr == 28 ) ) )
1.1.1.19 root 903: {
1.1.1.21 root 904: M68000_AddCycles ( CPU_IACK_CYCLES_START+CPU_IACK_CYCLES_VIDEO );
1.1.1.19 root 905: CPU_IACK = true;
906: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
907: CALL_VAR(PendingInterruptFunction);
1.1.1.20 root 908: if ( MFP_UpdateNeeded == true )
909: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1.1.1.19 root 910: pendingInterrupts &= ~( 1 << ( nr - 24 ) ); /* clear HBL or VBL pending bit */
911: CPU_IACK = false;
912: }
913:
914:
1.1.1.16 root 915: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 916: {
1.1.1.20 root 917: if (nr == 0x22)
1.1.1.13 root 918: {
1.1.1.17 root 919: /* Intercept VDI & AES exceptions (Trap #2) */
1.1.1.20 root 920: if(bVdiAesIntercept && VDI_AES_Entry())
1.1.1.13 root 921: {
1.1.1.17 root 922: /* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
923: * This will call OpCode_VDI() after completion of Trap call!
924: * This is used to modify specific VDI return vectors contents.
925: */
1.1.1.13 root 926: VDI_OldPC = currpc;
927: currpc = CART_VDI_OPCODE_ADDR;
928: }
929: }
1.1.1.20 root 930: else if (nr == 0x2d)
1.1.1.13 root 931: {
1.1.1.20 root 932: /* Intercept BIOS (Trap #13) calls */
933: if (Bios()) return;
934: }
935: else if (nr == 0x2e)
936: {
937: /* Intercept XBIOS (Trap #14) calls */
938: if (XBios()) return;
1.1.1.13 root 939: }
1.1.1.5 root 940: }
1.1.1.8 root 941:
1.1 root 942: MakeSR();
943:
1.1.1.8 root 944: /* Change to supervisor mode if necessary */
1.1 root 945: if (!regs.s) {
946: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 947: if (currprefs.cpu_level >= 2)
1.1 root 948: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
949: else
950: m68k_areg(regs, 7) = regs.isp;
951: regs.s = 1;
952: }
1.1.1.8 root 953:
954: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 955: /* (special case for MFP) */
1.1.1.12 root 956: if (currprefs.cpu_level > 0) {
1.1.1.16 root 957: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
958: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 959: m68k_areg(regs, 7) -= 2;
960: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
961: }
962: else if (nr == 2 || nr == 3) {
1.1 root 963: int i;
964: /* @@@ this is probably wrong (?) */
965: for (i = 0 ; i < 12 ; i++) {
966: m68k_areg(regs, 7) -= 2;
967: put_word (m68k_areg(regs, 7), 0);
968: }
969: m68k_areg(regs, 7) -= 2;
970: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
971: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
972: m68k_areg(regs, 7) -= 4;
973: put_long (m68k_areg(regs, 7), oldpc);
974: m68k_areg(regs, 7) -= 2;
975: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
976: } else if (regs.m && nr >= 24 && nr < 32) {
977: m68k_areg(regs, 7) -= 2;
978: put_word (m68k_areg(regs, 7), nr * 4);
979: m68k_areg(regs, 7) -= 4;
980: put_long (m68k_areg(regs, 7), currpc);
981: m68k_areg(regs, 7) -= 2;
982: put_word (m68k_areg(regs, 7), regs.sr);
983: regs.sr |= (1 << 13);
984: regs.msp = m68k_areg(regs, 7);
985: m68k_areg(regs, 7) = regs.isp;
986: m68k_areg(regs, 7) -= 2;
987: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
988: } else {
989: m68k_areg(regs, 7) -= 2;
990: put_word (m68k_areg(regs, 7), nr * 4);
991: }
992: }
1.1.1.3 root 993:
994: /* Push PC on stack: */
1.1 root 995: m68k_areg(regs, 7) -= 4;
996: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 997: /* Push SR on stack: */
1.1 root 998: m68k_areg(regs, 7) -= 2;
999: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 1000:
1.1.1.15 root 1001: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
1.1.1.21 root 1002: nr, currpc, regs.instruction_pc, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 1003:
1.1.1.3 root 1004: /* 68000 bus/address errors: */
1.1.1.16 root 1005: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.21 root 1006: uae_u16 specialstatus = last_instructionaccess_for_exception_3 ? 2 : 1;
1.1.1.20 root 1007: uae_u16 BusError_opcode;
1.1.1.12 root 1008:
1.1.1.8 root 1009: /* Special status word emulation isn't perfect yet... :-( */
1010: if (regs.sr & 0x2000)
1011: specialstatus |= 0x4;
1.1.1.3 root 1012: m68k_areg(regs, 7) -= 8;
1013: if (nr == 3) { /* Address error */
1.1.1.12 root 1014: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.21 root 1015: if (last_writeaccess_for_exception_3==0)
1016: specialstatus |= 0x10; /* bit 4 : 0=write 1=read */
1.1.1.8 root 1017: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 1018: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
1019: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
1020: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.21 root 1021:
1022: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
1023: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1024: if ( last_op_for_exception_3 == 0x2285 ) /* move.l d5,(a1) (War Heli) */
1025: put_long (m68k_areg(regs, 7)+10, currpc+4); /* correct PC is 2 bytes more than usual value */
1026:
1027: fprintf(stderr,"Address Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n",last_fault_for_exception_3, currpc, last_addr_for_exception_3, last_op_for_exception_3);
1.1.1.20 root 1028: if (ExceptionDebugMask & EXCEPT_ADDRESS) {
1.1.1.18 root 1029: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1030: }
1.1.1.3 root 1031: }
1.1.1.8 root 1032: else { /* Bus error */
1.1.1.20 root 1033: /* Get the opcode that caused the bus error, to adapt the stack frame in some cases */
1.1.1.21 root 1034: BusError_opcode = regs.opcode;
1.1.1.20 root 1035:
1036: specialstatus |= ( BusError_opcode & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 1037: if (bBusErrorReadWrite)
1.1.1.21 root 1038: specialstatus |= 0x10; /* bit 4 : 0=write 1=read */
1.1.1.8 root 1039: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 1040: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.20 root 1041: put_word (m68k_areg(regs, 7)+6, BusError_opcode); /* Opcode */
1.1.1.12 root 1042:
1043: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
1044: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.21 root 1045: if ( BusError_opcode == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
1046: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.20 root 1047:
1.1.1.21 root 1048: else if ( ( regs.instruction_pc == 0xccc ) && ( BusError_opcode == 0x48d6 ) ) /* 48d6 3f00 movem.l a0-a5,(a6) (Blood Money) */
1049: put_long (m68k_areg(regs, 7)+10, currpc+2); /* correct PC is 2 bytes more than usual value */
1.1.1.20 root 1050:
1.1.1.21 root 1051: else if ( ( regs.instruction_pc == 0x1fece ) && ( BusError_opcode == 0x33d4 ) ) /* 1fece : 33d4 0001 fdca move.w (a4),$1fdca (Batman The Movie) */
1052: put_long (m68k_areg(regs, 7)+10, currpc-4); /* correct PC is 4 bytes less than usual value */
1.1.1.20 root 1053:
1054: /* [NP] In case of a move with a bus error on the read part, uae cpu is writing to the dest part */
1055: /* then process the bus error ; on a real CPU, the bus error occurs after the read and before the */
1056: /* write, so the dest part doesn't change. For now, we restore the dest part on some specific cases */
1057: /* FIXME : the bus error should be processed just after the read, not at the end of the instruction */
1.1.1.21 root 1058: else if ( ( regs.instruction_pc == 0x62a ) && ( BusError_opcode == 0x3079 ) ) /* 3079 4ef9 0000 move.l $4ef90000,a0 (Dragon Flight) */
1059: m68k_areg(regs, 0) = 8; /* A0 should not be changed to "0" but keep its value "8" */
1.1.1.20 root 1060:
1.1.1.21 root 1061: else if ( get_long(regs.instruction_pc) == 0x13f88e21 ) /* 13f8 8e21 move.b $ffff8e21.w,$xxxxx (Tymewarp) */
1062: put_byte ( get_long(regs.instruction_pc+4) , 0x00 ); /* dest content should not be changed to "ff" but keep its value "00" */
1.1.1.20 root 1063:
1.1.1.22! root 1064: if (BusErrorAddress != 0xff8a00 || currpc < TosAddress || currpc > TosAddress + TosSize)
! 1065: fprintf(stderr, "Bus Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n",
! 1066: BusErrorAddress, currpc, get_long(m68k_areg(regs, 7)+10) , BusError_opcode);
1.1.1.20 root 1067:
1.1.1.8 root 1068: /* Check for double bus errors: */
1069: if (regs.spcflags & SPCFLAG_BUSERROR) {
1.1.1.21 root 1070: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n", BusErrorAddress, (long)currpc);
1071: cpu_halt();
1.1.1.8 root 1072: return;
1073: }
1.1.1.20 root 1074: if ((ExceptionDebugMask & EXCEPT_BUS) && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 1075: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.18 root 1076: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1077: }
1078: }
1.1.1.3 root 1079: }
1080:
1.1.1.8 root 1081: /* Set PC and flags */
1.1.1.20 root 1082: if ((ExceptionDebugMask & EXCEPT_NOHANDLER) && (regs.vbr + 4*nr) == 0) {
1083: fprintf(stderr,"Uninitialized exception handler #%i!\n", nr);
1.1.1.18 root 1084: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1085: }
1.1.1.17 root 1086: newpc = get_long (regs.vbr + 4*nr);
1087: if ( newpc & 1) /* check new pc is even */
1088: {
1089: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
1090: {
1.1.1.21 root 1091: fprintf(stderr,"Address Error during exception 2/3, new PC=$%x => CPU halted\n",newpc);
1092: cpu_halt();
1.1.1.17 root 1093: }
1094: else
1095: {
1096: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
1097: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
1098: }
1099: return;
1100: }
1.1.1.20 root 1101: /* handle debugger invocation for rest of exceptions */
1102: if (ExceptionDebugMask && nr > 3 && nr < 9)
1103: DebugUI_Exceptions(nr, currpc);
1.1.1.17 root 1104:
1.1 root 1105: m68k_setpc (get_long (regs.vbr + 4*nr));
1106: fill_prefetch_0 ();
1.1.1.12 root 1107: /* Handle trace flags depending on current state */
1108: exception_trace (nr);
1.1.1.6 root 1109:
1.1.1.13 root 1110: /* Handle exception cycles (special case for MFP) */
1.1.1.16 root 1111: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1112: {
1.1.1.21 root 1113: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_MFP); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1.1.1.13 root 1114: }
1115: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1116: {
1.1.1.21 root 1117: if ( nr == 26 ) /* HBL */
1118: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1119: else if ( nr == 28 ) /* VBL */
1120: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1.1.1.12 root 1121: else
1.1.1.21 root 1122: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1123: }
1124: else if(nr >= 32 && nr <= 47)
1125: {
1.1.1.13 root 1126: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1127: }
1128: else switch(nr)
1129: {
1.1.1.12 root 1130: case 2: M68000_AddCycles(50); break; /* Bus error */
1131: case 3: M68000_AddCycles(50); break; /* Address error */
1132: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1133: case 5: M68000_AddCycles(38); break; /* Div by zero */
1134: case 6: M68000_AddCycles(40); break; /* CHK */
1135: case 7: M68000_AddCycles(34); break; /* TRAPV */
1136: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1137: case 9: M68000_AddCycles(34); break; /* Trace */
1138: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1139: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1140: default:
1.1.1.8 root 1141: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1142: if(nr < 64)
1.1.1.12 root 1143: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1144: else
1.1.1.16 root 1145: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1146: break;
1.1.1.6 root 1147: }
1.1.1.14 root 1148:
1.1 root 1149: }
1150:
1.1.1.7 root 1151:
1.1.1.14 root 1152: static void Interrupt(int nr , int Pending)
1.1 root 1153: {
1154: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1155: /*lastint_regs = regs;*/
1156: /*lastint_no = nr;*/
1.1.1.13 root 1157:
1.1.1.16 root 1158: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1159: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1160:
1161: regs.intmask = nr;
1162: set_special (SPCFLAG_INT);
1.1.1.14 root 1163:
1164: /* Handle Atari ST's specific jitter for hbl/vbl */
1165: InterruptAddJitter ( nr , Pending );
1.1 root 1166: }
1167:
1.1.1.7 root 1168:
1.1.1.12 root 1169: uae_u32 caar, cacr;
1.1.1.8 root 1170: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1171:
1.1.1.7 root 1172:
1.1.1.12 root 1173: static int movec_illg (int regno)
1174: {
1175: int regno2 = regno & 0x7ff;
1176: if (currprefs.cpu_level == 1) { /* 68010 */
1177: if (regno2 < 2)
1178: return 0;
1179: return 1;
1180: }
1181: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1182: if (regno == 3) return 1; /* 68040 only */
1183: /* 4 is >=68040, but 0x804 is in 68020 */
1184: if (regno2 < 4 || regno == 0x804)
1185: return 0;
1186: return 1;
1187: }
1188: if (currprefs.cpu_level >= 4) { /* 68040 */
1189: if (regno == 0x802) return 1; /* 68020 only */
1190: if (regno2 < 8) return 0;
1191: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1192: return 0;
1193: return 1;
1194: }
1195: return 1;
1196: }
1197:
1.1 root 1198: int m68k_move2c (int regno, uae_u32 *regp)
1199: {
1.1.1.12 root 1200: if (movec_illg (regno)) {
1.1 root 1201: op_illg (0x4E7B);
1202: return 0;
1203: } else {
1204: switch (regno) {
1205: case 0: regs.sfc = *regp & 7; break;
1206: case 1: regs.dfc = *regp & 7; break;
1.1.1.16 root 1207: case 2:
1208: {
1209: uae_u32 cacr_mask = 0;
1210: if (currprefs.cpu_level == 2) // 68020
1211: cacr_mask = 0x0000000f;
1212: else if (currprefs.cpu_level == 3) // Fake 68030
1213: cacr_mask = 0x00003f1f;
1214: else if (currprefs.cpu_level == 4) // 68040
1215: cacr_mask = 0x80008000;
1216: cacr = *regp & cacr_mask;
1217: }
1.1 root 1218: case 3: tc = *regp & 0xc000; break;
1219: /* Mask out fields that should be zero. */
1220: case 4: itt0 = *regp & 0xffffe364; break;
1221: case 5: itt1 = *regp & 0xffffe364; break;
1222: case 6: dtt0 = *regp & 0xffffe364; break;
1223: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1224:
1.1 root 1225: case 0x800: regs.usp = *regp; break;
1226: case 0x801: regs.vbr = *regp; break;
1.1.1.20 root 1227: case 0x802: caar = *regp; break;
1.1 root 1228: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1229: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1230: case 0x805: mmusr = *regp; break;
1231: case 0x806: urp = *regp; break;
1232: case 0x807: srp = *regp; break;
1.1 root 1233: default:
1234: op_illg (0x4E7B);
1235: return 0;
1236: }
1237: }
1238: return 1;
1239: }
1240:
1241: int m68k_movec2 (int regno, uae_u32 *regp)
1242: {
1.1.1.12 root 1243: if (movec_illg (regno)) {
1.1 root 1244: op_illg (0x4E7A);
1245: return 0;
1246: } else {
1247: switch (regno) {
1248: case 0: *regp = regs.sfc; break;
1249: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1250: case 2: *regp = cacr; break;
1.1 root 1251: case 3: *regp = tc; break;
1252: case 4: *regp = itt0; break;
1253: case 5: *regp = itt1; break;
1254: case 6: *regp = dtt0; break;
1255: case 7: *regp = dtt1; break;
1256: case 0x800: *regp = regs.usp; break;
1257: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1258: case 0x802: *regp = caar; break;
1.1 root 1259: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1260: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1261: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1262: case 0x806: *regp = urp; break;
1263: case 0x807: *regp = srp; break;
1.1 root 1264: default:
1265: op_illg (0x4E7A);
1266: return 0;
1267: }
1268: }
1269: return 1;
1270: }
1271:
1272: STATIC_INLINE int
1.1.1.10 root 1273: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1274: {
1275: uae_u32 q = 0, cbit = 0;
1276: int i;
1277:
1.1.1.10 root 1278: if (ndiv <= src_hi) {
1.1 root 1279: return 1;
1280: }
1281: for (i = 0 ; i < 32 ; i++) {
1282: cbit = src_hi & 0x80000000ul;
1283: src_hi <<= 1;
1284: if (src_lo & 0x80000000ul) src_hi++;
1285: src_lo <<= 1;
1286: q = q << 1;
1.1.1.10 root 1287: if (cbit || ndiv <= src_hi) {
1.1 root 1288: q |= 1;
1.1.1.10 root 1289: src_hi -= ndiv;
1.1 root 1290: }
1291: }
1292: *quot = q;
1293: *rem = src_hi;
1294: return 0;
1295: }
1296:
1297: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1298: {
1299: #if defined(uae_s64)
1300: if (src == 0) {
1.1.1.16 root 1301: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1302: return;
1303: }
1304: if (extra & 0x800) {
1305: /* signed variant */
1306: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1307: uae_s64 quot, rem;
1308:
1309: if (extra & 0x400) {
1310: a &= 0xffffffffu;
1311: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1312: }
1313: rem = a % (uae_s64)(uae_s32)src;
1314: quot = a / (uae_s64)(uae_s32)src;
1315: if ((quot & UVAL64(0xffffffff80000000)) != 0
1316: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1317: {
1318: SET_VFLG (1);
1319: SET_NFLG (1);
1320: SET_CFLG (0);
1321: } else {
1322: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1323: SET_VFLG (0);
1324: SET_CFLG (0);
1325: SET_ZFLG (((uae_s32)quot) == 0);
1326: SET_NFLG (((uae_s32)quot) < 0);
1327: m68k_dreg(regs, extra & 7) = rem;
1328: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1329: }
1330: } else {
1331: /* unsigned */
1332: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1333: uae_u64 quot, rem;
1334:
1335: if (extra & 0x400) {
1336: a &= 0xffffffffu;
1337: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1338: }
1339: rem = a % (uae_u64)src;
1340: quot = a / (uae_u64)src;
1341: if (quot > 0xffffffffu) {
1342: SET_VFLG (1);
1343: SET_NFLG (1);
1344: SET_CFLG (0);
1345: } else {
1346: SET_VFLG (0);
1347: SET_CFLG (0);
1348: SET_ZFLG (((uae_s32)quot) == 0);
1349: SET_NFLG (((uae_s32)quot) < 0);
1350: m68k_dreg(regs, extra & 7) = rem;
1351: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1352: }
1353: }
1354: #else
1355: if (src == 0) {
1.1.1.16 root 1356: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1357: return;
1358: }
1359: if (extra & 0x800) {
1360: /* signed variant */
1361: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1362: uae_s32 hi = lo < 0 ? -1 : 0;
1363: uae_s32 save_high;
1364: uae_u32 quot, rem;
1365: uae_u32 sign;
1366:
1367: if (extra & 0x400) {
1368: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1369: }
1370: save_high = hi;
1371: sign = (hi ^ src);
1372: if (hi < 0) {
1373: hi = ~hi;
1374: lo = -lo;
1375: if (lo == 0) hi++;
1376: }
1377: if ((uae_s32)src < 0) src = -src;
1378: if (div_unsigned(hi, lo, src, ", &rem) ||
1379: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1380: SET_VFLG (1);
1381: SET_NFLG (1);
1382: SET_CFLG (0);
1383: } else {
1384: if (sign & 0x80000000) quot = -quot;
1385: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1386: SET_VFLG (0);
1387: SET_CFLG (0);
1388: SET_ZFLG (((uae_s32)quot) == 0);
1389: SET_NFLG (((uae_s32)quot) < 0);
1390: m68k_dreg(regs, extra & 7) = rem;
1391: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1392: }
1393: } else {
1394: /* unsigned */
1395: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1396: uae_u32 hi = 0;
1397: uae_u32 quot, rem;
1398:
1399: if (extra & 0x400) {
1400: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1401: }
1402: if (div_unsigned(hi, lo, src, ", &rem)) {
1403: SET_VFLG (1);
1404: SET_NFLG (1);
1405: SET_CFLG (0);
1406: } else {
1407: SET_VFLG (0);
1408: SET_CFLG (0);
1409: SET_ZFLG (((uae_s32)quot) == 0);
1410: SET_NFLG (((uae_s32)quot) < 0);
1411: m68k_dreg(regs, extra & 7) = rem;
1412: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1413: }
1414: }
1415: #endif
1416: }
1417:
1418: STATIC_INLINE void
1419: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1420: {
1421: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1422: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1423: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1424: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1425: uae_u32 lo;
1426:
1427: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1428: if (lo < r0) r3++;
1429: r0 = lo;
1430: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1431: if (lo < r0) r3++;
1432: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1433: *dst_lo = lo;
1434: *dst_hi = r3;
1435: }
1436:
1437: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1438: {
1439: #if defined(uae_s64)
1440: if (extra & 0x800) {
1441: /* signed variant */
1442: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1443:
1444: a *= (uae_s64)(uae_s32)src;
1445: SET_VFLG (0);
1446: SET_CFLG (0);
1447: SET_ZFLG (a == 0);
1448: SET_NFLG (a < 0);
1449: if (extra & 0x400)
1450: m68k_dreg(regs, extra & 7) = a >> 32;
1451: else if ((a & UVAL64(0xffffffff80000000)) != 0
1452: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1453: {
1454: SET_VFLG (1);
1455: }
1456: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1457: } else {
1458: /* unsigned */
1459: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1460:
1461: a *= (uae_u64)src;
1462: SET_VFLG (0);
1463: SET_CFLG (0);
1464: SET_ZFLG (a == 0);
1465: SET_NFLG (((uae_s64)a) < 0);
1466: if (extra & 0x400)
1467: m68k_dreg(regs, extra & 7) = a >> 32;
1468: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1469: SET_VFLG (1);
1470: }
1471: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1472: }
1473: #else
1474: if (extra & 0x800) {
1475: /* signed variant */
1476: uae_s32 src1,src2;
1477: uae_u32 dst_lo,dst_hi;
1478: uae_u32 sign;
1479:
1480: src1 = (uae_s32)src;
1481: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1482: sign = (src1 ^ src2);
1483: if (src1 < 0) src1 = -src1;
1484: if (src2 < 0) src2 = -src2;
1485: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1486: if (sign & 0x80000000) {
1487: dst_hi = ~dst_hi;
1488: dst_lo = -dst_lo;
1489: if (dst_lo == 0) dst_hi++;
1490: }
1491: SET_VFLG (0);
1492: SET_CFLG (0);
1493: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1494: SET_NFLG (((uae_s32)dst_hi) < 0);
1495: if (extra & 0x400)
1496: m68k_dreg(regs, extra & 7) = dst_hi;
1497: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1498: && ((dst_hi & 0xffffffff) != 0xffffffff
1499: || (dst_lo & 0x80000000) != 0x80000000))
1500: {
1501: SET_VFLG (1);
1502: }
1503: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1504: } else {
1505: /* unsigned */
1506: uae_u32 dst_lo,dst_hi;
1507:
1508: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1509:
1510: SET_VFLG (0);
1511: SET_CFLG (0);
1512: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1513: SET_NFLG (((uae_s32)dst_hi) < 0);
1514: if (extra & 0x400)
1515: m68k_dreg(regs, extra & 7) = dst_hi;
1516: else if (dst_hi != 0) {
1517: SET_VFLG (1);
1518: }
1519: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1520: }
1521: #endif
1522: }
1.1.1.6 root 1523:
1.1 root 1524:
1525: void m68k_reset (void)
1526: {
1527: regs.s = 1;
1528: regs.m = 0;
1529: regs.stopped = 0;
1530: regs.t1 = 0;
1531: regs.t0 = 0;
1532: SET_ZFLG (0);
1533: SET_XFLG (0);
1534: SET_CFLG (0);
1535: SET_VFLG (0);
1536: SET_NFLG (0);
1.1.1.16 root 1537: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1538: regs.intmask = 7;
1539: regs.vbr = regs.sfc = regs.dfc = 0;
1540: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1541:
1542: m68k_areg(regs, 7) = get_long(0);
1543: m68k_setpc(get_long(4));
1544: refill_prefetch (m68k_getpc(), 0);
1.1 root 1545: }
1546:
1.1.1.8 root 1547:
1.1 root 1548: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1549: {
1.1.1.8 root 1550: #if 0
1.1 root 1551: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1552: #endif
1.1.1.6 root 1553: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16 root 1554: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1555: return 4;
1.1.1.6 root 1556: }
1557: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16 root 1558: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1559: return 4;
1.1.1.6 root 1560: }
1.1.1.3 root 1561: #if 0
1.1.1.6 root 1562: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1563: #endif
1.1.1.16 root 1564: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1565: return 4;
1566: }
1567:
1.1.1.8 root 1568:
1.1 root 1569: void mmu_op(uae_u32 opcode, uae_u16 extra)
1570: {
1571: if ((opcode & 0xFE0) == 0x0500) {
1572: /* PFLUSH */
1573: mmusr = 0;
1574: write_log ("PFLUSH\n");
1575: } else if ((opcode & 0x0FD8) == 0x548) {
1576: /* PTEST */
1577: write_log ("PTEST\n");
1578: } else
1579: op_illg (opcode);
1580: }
1581:
1582:
1583: static uaecptr last_trace_ad = 0;
1584:
1585: static void do_trace (void)
1586: {
1.1.1.12 root 1587: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1588: uae_u16 opcode;
1589: /* should also include TRAP, CHK, SR modification FPcc */
1590: /* probably never used so why bother */
1591: /* We can afford this to be inefficient... */
1592: m68k_setpc (m68k_getpc ());
1593: fill_prefetch_0 ();
1594: opcode = get_word (regs.pc);
1.1.1.19 root 1595: if (opcode == 0x4e73 /* RTE */
1.1 root 1596: || opcode == 0x4e74 /* RTD */
1597: || opcode == 0x4e75 /* RTS */
1598: || opcode == 0x4e77 /* RTR */
1599: || opcode == 0x4e76 /* TRAPV */
1600: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1601: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1602: || (opcode & 0xff00) == 0x6100 /* BSR */
1603: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1604: && cctrue((opcode >> 8) & 0xf))
1605: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1606: && !cctrue((opcode >> 8) & 0xf)
1607: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1608: {
1609: last_trace_ad = m68k_getpc ();
1610: unset_special (SPCFLAG_TRACE);
1611: set_special (SPCFLAG_DOTRACE);
1612: }
1613: } else if (regs.t1) {
1614: last_trace_ad = m68k_getpc ();
1615: unset_special (SPCFLAG_TRACE);
1616: set_special (SPCFLAG_DOTRACE);
1617: }
1618: }
1619:
1620:
1.1.1.8 root 1621: /*
1622: * Handle special flags
1623: */
1.1.1.14 root 1624:
1625: static bool do_specialties_interrupt (int Pending)
1626: {
1.1.1.19 root 1627: #if ENABLE_DSP_EMU
1628: /* Check for DSP int first (if enabled) (level 6) */
1629: if (regs.spcflags & SPCFLAG_DSP) {
1630: if (DSP_ProcessIRQ() == true)
1631: return true;
1632: }
1633: #endif
1634:
1635: /* Check for MFP ints (level 6) */
1.1.1.14 root 1636: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.19 root 1637: if (MFP_ProcessIRQ() == true)
1.1.1.15 root 1638: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1639: }
1640:
1641: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1642: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1643: int intr = intlev ();
1644: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1645: // unset_special (SPCFLAG_DOINT);
1646: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1647: if (intr != -1 && intr > regs.intmask) {
1648: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1649: return true;
1.1.1.14 root 1650: }
1651: }
1652:
1.1.1.15 root 1653: return false; /* no interrupt was found */
1.1.1.14 root 1654: }
1655:
1656:
1.1 root 1657: static int do_specialties (void)
1658: {
1.1.1.7 root 1659: if(regs.spcflags & SPCFLAG_BUSERROR) {
1660: /* We can not execute bus errors directly in the memory handler
1661: * functions since the PC should point to the address of the next
1662: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1663: unset_special(SPCFLAG_BUSERROR);
1.1.1.16 root 1664: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1665: }
1666:
1.1.1.22! root 1667: if ( WaitStateCycles ) {
1.1.1.8 root 1668: /* Add some extra cycles to simulate a wait state */
1.1.1.22! root 1669: M68000_AddCycles(WaitStateCycles);
! 1670: WaitStateCycles = 0;
1.1.1.8 root 1671: }
1672:
1.1 root 1673: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16 root 1674: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1675: }
1.1.1.8 root 1676:
1.1.1.14 root 1677:
1678: /* Handle the STOP instruction */
1679: if ( regs.spcflags & SPCFLAG_STOP ) {
1.1.1.19 root 1680: //fprintf ( stderr , "test stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1681: /* We first test if there's a pending interrupt that would */
1.1.1.19 root 1682: /* allow to immediately leave the STOP state */
1.1.1.15 root 1683: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1684: regs.stopped = 0;
1685: unset_special (SPCFLAG_STOP);
1.1.1.19 root 1686: //fprintf ( stderr , "exit stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1687: }
1688:
1689: /* No pending int, we have to wait for the next matching int */
1690: while (regs.spcflags & SPCFLAG_STOP) {
1691:
1692: /* Take care of quit event if needed */
1693: if (regs.spcflags & SPCFLAG_BRK)
1694: return 1;
1695:
1696: M68000_AddCycles(4);
1697:
1698: /* It is possible one or more ints happen at the same time */
1.1.1.19 root 1699: /* We must process them during the same cpu cycle then choose the highest priority one */
1700: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1.1.1.14 root 1701: CALL_VAR(PendingInterruptFunction);
1.1.1.19 root 1702: if ( MFP_UpdateNeeded == true )
1703: MFP_UpdateIRQ ( 0 );
1704:
1705: /* Check is there's an interrupt to process (could be a delayed MFP interrupt) */
1706: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1707: regs.stopped = 0;
1708: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1709: }
1.1 root 1710: }
1711: }
1.1.1.8 root 1712:
1.1.1.14 root 1713:
1.1 root 1714: if (regs.spcflags & SPCFLAG_TRACE)
1715: do_trace ();
1716:
1.1.1.12 root 1717: // if (regs.spcflags & SPCFLAG_DOINT) {
1718: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1719: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1720:
1721: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1722: regs.stopped = 0; /* [NP] useless ? */
1723: }
1724: if (regs.spcflags & SPCFLAG_INT) {
1725: unset_special (SPCFLAG_INT);
1726: set_special (SPCFLAG_DOINT);
1727: }
1.1.1.8 root 1728:
1.1.1.15 root 1729: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16 root 1730: DebugCpu_Check();
1.1.1.15 root 1731:
1.1 root 1732: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1733: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1734: return 1;
1735: }
1.1.1.8 root 1736:
1.1 root 1737: return 0;
1738: }
1739:
1.1.1.3 root 1740:
1.1 root 1741: /* It's really sad to have two almost identical functions for this, but we
1742: do it all for performance... :( */
1743: static void m68k_run_1 (void)
1744: {
1745: #ifdef DEBUG_PREFETCH
1746: uae_u8 saved_bytes[20];
1.1.1.20 root 1747: uae_u8 *oldpcp;
1.1 root 1748: #endif
1.1.1.8 root 1749:
1750: for (;;) {
1.1 root 1751: int cycles;
1.1.1.20 root 1752: //fprintf (stderr, "ir in %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1.1.21 root 1753: regs.opcode = get_iword_prefetch (0);
1754:
1755: if (regs.spcflags & SPCFLAG_BUSERROR)
1756: {
1757: unset_special(SPCFLAG_BUSERROR);
1758: Exception(2,0,M68000_EXC_SRC_CPU);
1759:
1760: /* Get opcode for bus error handler and check other special bits */
1761: regs.opcode = get_iword_prefetch (0);
1762: if (regs.spcflags) {
1763: if (do_specialties ())
1764: return;
1765: }
1766: }
1.1.1.8 root 1767:
1.1 root 1768: #ifdef DEBUG_PREFETCH
1.1.1.20 root 1769: // if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1770: // fprintf (stderr, "Prefetch differs from memory.\n");
1771: // debugging = 1;
1772: // return;
1773: // }
1.1 root 1774: oldpcp = regs.pc_p;
1775: memcpy (saved_bytes, regs.pc_p, 20);
1776: #endif
1777:
1778: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1779: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1780: {
1781: int FrameCycles, HblCounterVideo, LineCycles;
1782:
1783: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1784:
1785: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1786: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1787: }
1.1 root 1788:
1789: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1790: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1791: #if COUNT_INSTRS == 2
1.1.1.21 root 1792: if (table68k[regs.opcode].handler != -1)
1793: instrcount[table68k[regs.opcode].handler]++;
1.1 root 1794: #elif COUNT_INSTRS == 1
1.1.1.21 root 1795: instrcount[regs.opcode]++;
1.1 root 1796: #endif
1.1.1.2 root 1797:
1.1.1.12 root 1798: /* In case of a Bus Error, we need the PC of the instruction that caused */
1799: /* the error to build the exception stack frame */
1.1.1.21 root 1800: regs.instruction_pc = m68k_getpc();
1.1.1.12 root 1801:
1.1.1.18 root 1802: if (bDspEnabled)
1803: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1804:
1.1.1.20 root 1805: /* Uncomment following lines to call capslib's debugger after each instruction */
1806: //if ( CAPSGetDebugRequest() )
1807: // DebugUI(REASON_CPU_BREAKPOINT);
1808:
1.1.1.21 root 1809: cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
1.1.1.20 root 1810: //fprintf (stderr, "ir out %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1.1.6 root 1811:
1.1 root 1812: #ifdef DEBUG_PREFETCH
1813: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1814: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1.1.20 root 1815: // set_special (SPCFLAG_BRK);
1816: // debugging = 1;
1.1 root 1817: }
1818: #endif
1.1.1.2 root 1819:
1.1.1.12 root 1820: M68000_AddCyclesWithPairing(cycles);
1.1.1.22! root 1821:
! 1822: if ( WaitStateCycles ) {
1.1.1.13 root 1823: /* Add some extra cycles to simulate a wait state */
1.1.1.22! root 1824: M68000_AddCycles(WaitStateCycles);
! 1825: WaitStateCycles = 0;
1.1.1.13 root 1826: }
1827:
1.1.1.14 root 1828: /* We can have several interrupts at the same time before the next CPU instruction */
1829: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1830: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1831: /* and prevent exiting the STOP state when calling do_specialties() after. */
1832: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1.1.1.19 root 1833: if ( PendingInterruptCount <= 0 )
1834: {
1835: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1836: CALL_VAR ( PendingInterruptFunction ); /* call the interrupt's handler */
1837: if ( MFP_UpdateNeeded == true )
1838: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1839: }
1.1.1.14 root 1840:
1841: if (regs.spcflags) {
1842: if (do_specialties ())
1843: return;
1844: }
1845:
1.1.1.15 root 1846: /* Run DSP 56k code if necessary */
1847: if (bDspEnabled) {
1.1.1.22! root 1848: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * DSP_CPU_FREQ_RATIO);
1.1.1.15 root 1849: }
1.1 root 1850: }
1851: }
1852:
1853:
1854: /* Same thing, but don't use prefetch to get opcode. */
1855: static void m68k_run_2 (void)
1856: {
1.1.1.8 root 1857: for (;;) {
1.1 root 1858: int cycles;
1.1.1.21 root 1859:
1860: regs.opcode = get_iword (0);
1.1 root 1861:
1862: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1863: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1864: {
1865: int FrameCycles, HblCounterVideo, LineCycles;
1866:
1867: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1868:
1869: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1870: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1871: }
1.1.1.12 root 1872:
1.1 root 1873: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1874: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1875: #if COUNT_INSTRS == 2
1.1.1.21 root 1876: if (table68k[regs.opcode].handler != -1)
1877: instrcount[table68k[regs.opcode].handler]++;
1.1 root 1878: #elif COUNT_INSTRS == 1
1.1.1.21 root 1879: instrcount[regs.opcode]++;
1.1 root 1880: #endif
1.1.1.2 root 1881:
1.1.1.17 root 1882: /* In case of a Bus Error, we need the PC of the instruction that caused */
1883: /* the error to build the exception stack frame */
1.1.1.21 root 1884: regs.instruction_pc = m68k_getpc();
1.1.1.17 root 1885:
1.1.1.21 root 1886: cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
1.1.1.6 root 1887:
1.1.1.16 root 1888: if (bDspEnabled)
1889: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1890:
1.1.1.8 root 1891: M68000_AddCycles(cycles);
1.1.1.22! root 1892:
! 1893: if ( WaitStateCycles ) {
1.1.1.13 root 1894: /* Add some extra cycles to simulate a wait state */
1.1.1.22! root 1895: M68000_AddCycles(WaitStateCycles);
! 1896: WaitStateCycles = 0;
1.1.1.13 root 1897: }
1898:
1.1.1.19 root 1899: if ( PendingInterruptCount <= 0 )
1900: {
1901: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1902: CALL_VAR(PendingInterruptFunction);
1903: if ( MFP_UpdateNeeded == true )
1904: MFP_UpdateIRQ ( 0 );
1905: }
1.1.1.8 root 1906:
1.1 root 1907: if (regs.spcflags) {
1908: if (do_specialties ())
1909: return;
1910: }
1.1.1.15 root 1911:
1912: /* Run DSP 56k code if necessary */
1913: if (bDspEnabled) {
1.1.1.22! root 1914: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * DSP_CPU_FREQ_RATIO);
1.1.1.15 root 1915: }
1.1 root 1916: }
1917: }
1918:
1919:
1920: void m68k_go (int may_quit)
1921: {
1.1.1.8 root 1922: static int in_m68k_go = 0;
1923:
1.1 root 1924: if (in_m68k_go || !may_quit) {
1925: write_log ("Bug! m68k_go is not reentrant.\n");
1926: abort ();
1927: }
1928:
1929: in_m68k_go++;
1.1.1.8 root 1930: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1931: if(currprefs.cpu_compatible)
1.1.1.2 root 1932: m68k_run_1();
1933: else
1934: m68k_run_2();
1.1 root 1935: }
1.1.1.8 root 1936: unset_special(SPCFLAG_BRK);
1.1 root 1937: in_m68k_go--;
1938: }
1939:
1.1.1.8 root 1940:
1941: /*
1.1 root 1942: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1943: {
1944: uae_u32 opcode, val;
1945: struct instr *dp;
1946:
1947: opcode = get_iword_1(0);
1948: last_op_for_exception_3 = opcode;
1949: m68kpc_offset = 2;
1950:
1.1.1.6 root 1951: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1952: opcode = 0x4AFC;
1953: }
1954: dp = table68k + opcode;
1955:
1956: if (dp->suse) {
1957: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16 root 1958: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1959: return;
1960: }
1961: }
1962: if (dp->duse) {
1963: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16 root 1964: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1965: return;
1966: }
1967: }
1968: }
1.1.1.8 root 1969: */
1970:
1.1 root 1971:
1972: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1973: {
1.1.1.11 root 1974: static const char * const ccnames[] =
1.1.1.8 root 1975: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1976: "VC","VS","PL","MI","GE","LT","GT","LE" };
1977:
1.1 root 1978: uaecptr newpc = 0;
1979: m68kpc_offset = addr - m68k_getpc ();
1980: while (cnt-- > 0) {
1981: char instrname[20],*ccpt;
1982: int opwords;
1983: uae_u32 opcode;
1.1.1.11 root 1984: const struct mnemolookup *lookup;
1.1 root 1985: struct instr *dp;
1986: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1987: for (opwords = 0; opwords < 5; opwords++){
1.1.1.21 root 1988: if ( valid_address ( m68k_getpc () + m68kpc_offset + opwords*2 , 2 ) )
1989: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1990: else
1991: fprintf (f, "**** " );
1.1 root 1992: }
1.1.1.21 root 1993: if ( ! valid_address ( m68k_getpc () + m68kpc_offset , 2 ) ) {
1994: fprintf (f , "BUS ERROR\n" ); /* If region is not valid (bus error region) */
1995: m68kpc_offset += 2;
1996: continue;
1997: }
1998:
1.1 root 1999: opcode = get_iword_1 (m68kpc_offset);
2000: m68kpc_offset += 2;
1.1.1.6 root 2001: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 2002: opcode = 0x4AFC;
2003: }
2004: dp = table68k + opcode;
2005: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
2006: ;
2007:
2008: strcpy (instrname, lookup->name);
2009: ccpt = strstr (instrname, "cc");
2010: if (ccpt != 0) {
2011: strncpy (ccpt, ccnames[dp->cc], 2);
2012: }
2013: fprintf (f, "%s", instrname);
2014: switch (dp->size){
2015: case sz_byte: fprintf (f, ".B "); break;
2016: case sz_word: fprintf (f, ".W "); break;
2017: case sz_long: fprintf (f, ".L "); break;
2018: default: fprintf (f, " "); break;
2019: }
2020:
2021: if (dp->suse) {
2022: newpc = m68k_getpc () + m68kpc_offset;
2023: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
2024: }
2025: if (dp->suse && dp->duse)
2026: fprintf (f, ",");
2027: if (dp->duse) {
2028: newpc = m68k_getpc () + m68kpc_offset;
2029: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
2030: }
2031: if (ccpt != 0) {
2032: if (cctrue(dp->cc))
1.1.1.5 root 2033: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 2034: else
1.1.1.5 root 2035: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 2036: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 2037: fprintf (f, " == %08lx", (long)newpc);
1.1 root 2038: fprintf (f, "\n");
2039: }
2040: if (nextpc)
2041: *nextpc = m68k_getpc () + m68kpc_offset;
2042: }
2043:
2044: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
2045: {
2046: int i;
2047: for (i = 0; i < 8; i++){
1.1.1.5 root 2048: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 2049: if ((i & 3) == 3) fprintf (f, "\n");
2050: }
2051: for (i = 0; i < 8; i++){
1.1.1.5 root 2052: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 2053: if ((i & 3) == 3) fprintf (f, "\n");
2054: }
2055: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
2056: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
2057: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
2058: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 2059: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 2060: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
2061: regs.t1, regs.t0, regs.s, regs.m,
2062: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
2063: for (i = 0; i < 8; i++){
2064: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
2065: if ((i & 3) == 3) fprintf (f, "\n");
2066: }
2067: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
2068: (regs.fpsr & 0x8000000) != 0,
2069: (regs.fpsr & 0x4000000) != 0,
2070: (regs.fpsr & 0x2000000) != 0,
2071: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 2072: if (currprefs.cpu_compatible)
1.1 root 2073: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
2074:
2075: m68k_disasm (f, m68k_getpc (), nextpc, 1);
2076: if (nextpc)
1.1.1.5 root 2077: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 2078: }
1.1.1.12 root 2079:
2080:
2081: /*
2082:
2083: The routines below take dividend and divisor as parameters.
2084: They return 0 if division by zero, or exact number of cycles otherwise.
2085:
2086: The number of cycles returned assumes a register operand.
2087: Effective address time must be added if memory operand.
2088:
2089: For 68000 only (not 68010, 68012, 68020, etc).
2090: Probably valid for 68008 after adding the extra prefetch cycle.
2091:
2092:
2093: Best and worst cases are for register operand:
2094: (Note the difference with the documented range.)
2095:
2096:
2097: DIVU:
2098:
2099: Overflow (always): 10 cycles.
2100: Worst case: 136 cycles.
2101: Best case: 76 cycles.
2102:
2103:
2104: DIVS:
2105:
2106: Absolute overflow: 16-18 cycles.
2107: Signed overflow is not detected prematurely.
2108:
2109: Worst case: 156 cycles.
2110: Best case without signed overflow: 122 cycles.
2111: Best case with signed overflow: 120 cycles
2112:
2113:
2114: */
2115:
2116:
2117: //
2118: // DIVU
2119: // Unsigned division
2120: //
2121:
2122: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2123: {
2124: int mcycles;
2125: uae_u32 hdivisor;
2126: int i;
2127:
2128: if (divisor == 0)
2129: return 0;
2130:
2131: // Overflow
2132: if ((dividend >> 16) >= divisor)
2133: return (mcycles = 5) * 2;
2134:
2135: mcycles = 38;
2136: hdivisor = divisor << 16;
2137:
2138: for (i = 0; i < 15; i++) {
2139: uae_u32 temp;
2140: temp = dividend;
2141:
2142: dividend <<= 1;
2143:
2144: // If carry from shift
2145: if ((uae_s32)temp < 0)
2146: dividend -= hdivisor;
2147: else {
2148: mcycles += 2;
2149: if (dividend >= hdivisor) {
2150: dividend -= hdivisor;
2151: mcycles--;
2152: }
2153: }
2154: }
2155: return mcycles * 2;
2156: }
2157: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2158: {
2159: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2160: // write_log ("U%d ", v);
2161: return v;
2162: }
2163:
2164: //
2165: // DIVS
2166: // Signed division
2167: //
2168:
2169: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2170: {
2171: int mcycles;
2172: uae_u32 aquot;
2173: int i;
2174:
2175: if (divisor == 0)
2176: return 0;
2177:
2178: mcycles = 6;
2179:
2180: if (dividend < 0)
2181: mcycles++;
2182:
2183: // Check for absolute overflow
2184: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2185: return (mcycles + 2) * 2;
2186:
2187: // Absolute quotient
2188: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2189:
2190: mcycles += 55;
2191:
2192: if (divisor >= 0) {
2193: if (dividend >= 0)
2194: mcycles--;
2195: else
2196: mcycles++;
2197: }
2198:
2199: // Count 15 msbits in absolute of quotient
2200:
2201: for (i = 0; i < 15; i++) {
2202: if ((uae_s16)aquot >= 0)
2203: mcycles++;
2204: aquot <<= 1;
2205: }
2206:
2207: return mcycles * 2;
2208: }
2209: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2210: {
2211: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2212: // write_log ("S%d ", v);
2213: return v;
2214: }
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