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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.7 ! root 13: static char rcsid[] = "Hatari $Id: newcpu.c,v 1.25 2003/07/04 12:40:13 thothy Exp $";
1.1 root 14:
15: #include "sysdeps.h"
16: #include "hatari-glue.h"
17: #include "maccess.h"
18: #include "memory.h"
19: #include "newcpu.h"
20: #include "events.h"
1.1.1.5 root 21: #include "../includes/main.h"
1.1.1.7 ! root 22: #include "../includes/m68000.h"
1.1 root 23: #include "../includes/tos.h"
1.1.1.5 root 24: #include "../includes/vdi.h"
25: #include "../includes/cart.h"
26: #include "../includes/debugui.h"
1.1 root 27:
28:
29: struct flag_struct regflags;
30:
1.1.1.2 root 31: int lastInstructionCycles; /* how many cycles last instruction took to execute */
32:
1.1 root 33: /* Opcode of faulting instruction */
34: uae_u16 last_op_for_exception_3;
35: /* PC at fault time */
36: uaecptr last_addr_for_exception_3;
37: /* Address that generated the exception */
38: uaecptr last_fault_for_exception_3;
39:
40: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
41: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
42:
43: int movem_index1[256];
44: int movem_index2[256];
45: int movem_next[256];
46:
47: int fpp_movem_index1[256];
48: int fpp_movem_index2[256];
49: int fpp_movem_next[256];
50:
51: cpuop_func *cpufunctbl[65536];
52:
1.1.1.6 root 53:
1.1 root 54: #define COUNT_INSTRS 0
55:
56: #if COUNT_INSTRS
57: static unsigned long int instrcount[65536];
58: static uae_u16 opcodenums[65536];
59:
60: static int compfn (const void *el1, const void *el2)
61: {
62: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
63: }
64:
65: static char *icountfilename (void)
66: {
67: char *name = getenv ("INSNCOUNT");
68: if (name)
69: return name;
70: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
71: }
72:
73: void dump_counts (void)
74: {
75: FILE *f = fopen (icountfilename (), "w");
76: unsigned long int total;
77: int i;
78:
79: write_log ("Writing instruction count file...\n");
80: for (i = 0; i < 65536; i++) {
81: opcodenums[i] = i;
82: total += instrcount[i];
83: }
84: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
85:
86: fprintf (f, "Total: %lu\n", total);
87: for (i=0; i < 65536; i++) {
88: unsigned long int cnt = instrcount[opcodenums[i]];
89: struct instr *dp;
90: struct mnemolookup *lookup;
91: if (!cnt)
92: break;
93: dp = table68k + opcodenums[i];
94: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
95: ;
96: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
97: }
98: fclose (f);
99: }
100: #else
101: void dump_counts (void)
102: {
103: }
104: #endif
105:
106: int broken_in;
107:
108: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
109:
110: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
111: {
1.1.1.6 root 112: op_illg (opcode);
1.1 root 113: return 4;
114: }
115:
1.1.1.4 root 116:
117: void build_cpufunctbl(void)
1.1 root 118: {
119: int i;
120: unsigned long opcode;
121: struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff
122: : cpu_level == 3 ? op_smalltbl_1_ff
123: : cpu_level == 2 ? op_smalltbl_2_ff
124: : cpu_level == 1 ? op_smalltbl_3_ff
125: : ! cpu_compatible ? op_smalltbl_4_ff
126: : op_smalltbl_5_ff);
127:
128: write_log ("Building CPU function table (%d %d %d).\n",
129: cpu_level, cpu_compatible, address_space_24);
130:
131: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 132: cpufunctbl[opcode] = op_illg_1;
1.1 root 133: for (i = 0; tbl[i].handler != NULL; i++) {
134: if (! tbl[i].specific)
1.1.1.6 root 135: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 136: }
137: for (opcode = 0; opcode < 65536; opcode++) {
138: cpuop_func *f;
139:
140: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
141: continue;
142:
143: if (table68k[opcode].handler != -1) {
1.1.1.6 root 144: f = cpufunctbl[table68k[opcode].handler];
1.1 root 145: if (f == op_illg_1)
146: abort();
1.1.1.6 root 147: cpufunctbl[opcode] = f;
1.1 root 148: }
149: }
150: for (i = 0; tbl[i].handler != NULL; i++) {
151: if (tbl[i].specific)
1.1.1.6 root 152: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 153: }
154:
1.1.1.6 root 155: /* Hatari's illegal opcodes: */
156: cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos;
157: cpufunctbl[RUNOLDGEMDOS_OPCODE] = OpCode_OldGemDos;
1.1.1.7 ! root 158: cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit;
1.1.1.6 root 159: cpufunctbl[VDI_OPCODE] = OpCode_VDI;
1.1 root 160: }
161:
162:
163:
164: void init_m68k (void)
165: {
166: int i;
167:
168: for (i = 0 ; i < 256 ; i++) {
169: int j;
170: for (j = 0 ; j < 8 ; j++) {
171: if (i & (1 << j)) break;
172: }
173: movem_index1[i] = j;
174: movem_index2[i] = 7-j;
175: movem_next[i] = i & (~(1 << j));
176: }
177: for (i = 0 ; i < 256 ; i++) {
178: int j;
179: for (j = 7 ; j >= 0 ; j--) {
180: if (i & (1 << j)) break;
181: }
182: fpp_movem_index1[i] = 7-j;
183: fpp_movem_index2[i] = j;
184: fpp_movem_next[i] = i & (~(1 << j));
185: }
186: #if COUNT_INSTRS
187: {
188: FILE *f = fopen (icountfilename (), "r");
189: memset (instrcount, 0, sizeof instrcount);
190: if (f) {
191: uae_u32 opcode, count, total;
192: char name[20];
193: write_log ("Reading instruction count file...\n");
194: fscanf (f, "Total: %lu\n", &total);
195: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
196: instrcount[opcode] = count;
197: }
198: fclose(f);
199: }
200: }
201: #endif
202: write_log ("Building CPU table for configuration: 68");
203: if (address_space_24 && cpu_level > 1)
204: write_log ("EC");
205: switch (cpu_level) {
206: case 1:
207: write_log ("010");
208: break;
209: case 2:
210: write_log ("020");
211: break;
212: case 3:
213: write_log ("020/881");
214: break;
215: case 4:
216: /* Who is going to miss the MMU anyway...? :-) */
217: write_log ("040");
218: break;
219: default:
220: write_log ("000");
221: break;
222: }
223: if (cpu_compatible)
224: write_log (" (compatible mode)");
225: write_log ("\n");
1.1.1.7 ! root 226:
1.1 root 227: read_table68k ();
228: do_merges ();
229:
230: write_log ("%d CPU functions\n", nr_cpuop_funcs);
231:
232: build_cpufunctbl ();
233: }
234:
1.1.1.4 root 235:
1.1 root 236: struct regstruct regs, lastint_regs;
237: static struct regstruct regs_backup[16];
238: static int backup_pointer = 0;
239: static long int m68kpc_offset;
240: int lastint_no;
241:
242: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
243: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
244: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
245:
246: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
247: {
248: uae_u16 dp;
249: uae_s8 disp8;
250: uae_s16 disp16;
251: int r;
252: uae_u32 dispreg;
253: uaecptr addr;
254: uae_s32 offset = 0;
255: char buffer[80];
256:
257: switch (mode){
258: case Dreg:
259: sprintf (buffer,"D%d", reg);
260: break;
261: case Areg:
262: sprintf (buffer,"A%d", reg);
263: break;
264: case Aind:
265: sprintf (buffer,"(A%d)", reg);
266: break;
267: case Aipi:
268: sprintf (buffer,"(A%d)+", reg);
269: break;
270: case Apdi:
271: sprintf (buffer,"-(A%d)", reg);
272: break;
273: case Ad16:
274: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
275: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
276: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
277: (unsigned long)addr);
278: break;
279: case Ad8r:
280: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
281: disp8 = dp & 0xFF;
282: r = (dp & 0x7000) >> 12;
283: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
284: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
285: dispreg <<= (dp >> 9) & 3;
286:
287: if (dp & 0x100) {
288: uae_s32 outer = 0, disp = 0;
289: uae_s32 base = m68k_areg(regs,reg);
290: char name[10];
291: sprintf (name,"A%d, ",reg);
292: if (dp & 0x80) { base = 0; name[0] = 0; }
293: if (dp & 0x40) dispreg = 0;
294: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
295: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
296: base += disp;
297:
298: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
299: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
300:
301: if (!(dp & 4)) base += dispreg;
302: if (dp & 3) base = get_long (base);
303: if (dp & 4) base += dispreg;
304:
305: addr = base + outer;
306: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
307: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
308: 1 << ((dp >> 9) & 3),
1.1.1.5 root 309: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 310: } else {
311: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
312: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
313: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
314: 1 << ((dp >> 9) & 3), disp8,
315: (unsigned long)addr);
316: }
317: break;
318: case PC16:
319: addr = m68k_getpc () + m68kpc_offset;
320: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
321: addr += (uae_s16)disp16;
322: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
323: break;
324: case PC8r:
325: addr = m68k_getpc () + m68kpc_offset;
326: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
327: disp8 = dp & 0xFF;
328: r = (dp & 0x7000) >> 12;
329: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
330: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
331: dispreg <<= (dp >> 9) & 3;
332:
333: if (dp & 0x100) {
334: uae_s32 outer = 0,disp = 0;
335: uae_s32 base = addr;
336: char name[10];
337: sprintf (name,"PC, ");
338: if (dp & 0x80) { base = 0; name[0] = 0; }
339: if (dp & 0x40) dispreg = 0;
340: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
341: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
342: base += disp;
343:
344: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
345: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
346:
347: if (!(dp & 4)) base += dispreg;
348: if (dp & 3) base = get_long (base);
349: if (dp & 4) base += dispreg;
350:
351: addr = base + outer;
352: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
353: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
354: 1 << ((dp >> 9) & 3),
1.1.1.5 root 355: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 356: } else {
357: addr += (uae_s32)((uae_s8)disp8) + dispreg;
358: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
359: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
360: disp8, (unsigned long)addr);
361: }
362: break;
363: case absw:
364: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
365: m68kpc_offset += 2;
366: break;
367: case absl:
368: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
369: m68kpc_offset += 4;
370: break;
371: case imm:
372: switch (size){
373: case sz_byte:
374: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
375: m68kpc_offset += 2;
376: break;
377: case sz_word:
378: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
379: m68kpc_offset += 2;
380: break;
381: case sz_long:
382: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
383: m68kpc_offset += 4;
384: break;
385: default:
386: break;
387: }
388: break;
389: case imm0:
390: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
391: m68kpc_offset += 2;
392: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
393: break;
394: case imm1:
395: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
396: m68kpc_offset += 2;
397: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
398: break;
399: case imm2:
400: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
401: m68kpc_offset += 4;
402: sprintf (buffer,"#$%08lx", (unsigned long)offset);
403: break;
404: case immi:
405: offset = (uae_s32)(uae_s8)(reg & 0xff);
406: sprintf (buffer,"#$%08lx", (unsigned long)offset);
407: break;
408: default:
409: break;
410: }
411: if (buf == 0)
412: fprintf (f, "%s", buffer);
413: else
414: strcat (buf, buffer);
415: return offset;
416: }
417:
418: /* The plan is that this will take over the job of exception 3 handling -
419: * the CPU emulation functions will just do a longjmp to m68k_go whenever
420: * they hit an odd address. */
421: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
422: {
423: uae_u16 dp;
424: uae_s8 disp8;
425: uae_s16 disp16;
426: int r;
427: uae_u32 dispreg;
428: uaecptr addr;
1.1.1.5 root 429: /*uae_s32 offset = 0;*/
1.1 root 430:
431: switch (mode){
432: case Dreg:
433: *val = m68k_dreg (regs, reg);
434: return 1;
435: case Areg:
436: *val = m68k_areg (regs, reg);
437: return 1;
438:
439: case Aind:
440: case Aipi:
441: addr = m68k_areg (regs, reg);
442: break;
443: case Apdi:
444: addr = m68k_areg (regs, reg);
445: break;
446: case Ad16:
447: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
448: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
449: break;
450: case Ad8r:
451: addr = m68k_areg (regs, reg);
452: d8r_common:
453: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
454: disp8 = dp & 0xFF;
455: r = (dp & 0x7000) >> 12;
456: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
457: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
458: dispreg <<= (dp >> 9) & 3;
459:
460: if (dp & 0x100) {
461: uae_s32 outer = 0, disp = 0;
462: uae_s32 base = addr;
463: if (dp & 0x80) base = 0;
464: if (dp & 0x40) dispreg = 0;
465: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
466: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
467: base += disp;
468:
469: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
470: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
471:
472: if (!(dp & 4)) base += dispreg;
473: if (dp & 3) base = get_long (base);
474: if (dp & 4) base += dispreg;
475:
476: addr = base + outer;
477: } else {
478: addr += (uae_s32)((uae_s8)disp8) + dispreg;
479: }
480: break;
481: case PC16:
482: addr = m68k_getpc () + m68kpc_offset;
483: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
484: addr += (uae_s16)disp16;
485: break;
486: case PC8r:
487: addr = m68k_getpc () + m68kpc_offset;
488: goto d8r_common;
489: case absw:
490: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
491: m68kpc_offset += 2;
492: break;
493: case absl:
494: addr = get_ilong_1 (m68kpc_offset);
495: m68kpc_offset += 4;
496: break;
497: case imm:
498: switch (size){
499: case sz_byte:
500: *val = get_iword_1 (m68kpc_offset) & 0xff;
501: m68kpc_offset += 2;
502: break;
503: case sz_word:
504: *val = get_iword_1 (m68kpc_offset) & 0xffff;
505: m68kpc_offset += 2;
506: break;
507: case sz_long:
508: *val = get_ilong_1 (m68kpc_offset);
509: m68kpc_offset += 4;
510: break;
511: default:
512: break;
513: }
514: return 1;
515: case imm0:
516: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
517: m68kpc_offset += 2;
518: return 1;
519: case imm1:
520: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
521: m68kpc_offset += 2;
522: return 1;
523: case imm2:
524: *val = get_ilong_1 (m68kpc_offset);
525: m68kpc_offset += 4;
526: return 1;
527: case immi:
528: *val = (uae_s32)(uae_s8)(reg & 0xff);
529: return 1;
530: default:
531: addr = 0;
532: break;
533: }
534: if ((addr & 1) == 0)
535: return 1;
536:
537: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
538: last_fault_for_exception_3 = addr;
539: return 0;
540: }
541:
542: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
543: {
544: int reg = (dp >> 12) & 15;
545: uae_s32 regd = regs.regs[reg];
546: if ((dp & 0x800) == 0)
547: regd = (uae_s32)(uae_s16)regd;
548: regd <<= (dp >> 9) & 3;
549: if (dp & 0x100) {
550: uae_s32 outer = 0;
551: if (dp & 0x80) base = 0;
552: if (dp & 0x40) regd = 0;
553:
554: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
555: if ((dp & 0x30) == 0x30) base += next_ilong();
556:
557: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
558: if ((dp & 0x3) == 0x3) outer = next_ilong();
559:
560: if ((dp & 0x4) == 0) base += regd;
561: if (dp & 0x3) base = get_long (base);
562: if (dp & 0x4) base += regd;
563:
564: return base + outer;
565: } else {
566: return base + (uae_s32)((uae_s8)dp) + regd;
567: }
568: }
569:
570: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
571: {
572: int reg = (dp >> 12) & 15;
573: uae_s32 regd = regs.regs[reg];
574: #if 1
575: if ((dp & 0x800) == 0)
576: regd = (uae_s32)(uae_s16)regd;
577: return base + (uae_s8)dp + regd;
578: #else
579: /* Branch-free code... benchmark this again now that
580: * things are no longer inline. */
581: uae_s32 regd16;
582: uae_u32 mask;
583: mask = ((dp & 0x800) >> 11) - 1;
584: regd16 = (uae_s32)(uae_s16)regd;
585: regd16 &= mask;
586: mask = ~mask;
587: base += (uae_s8)dp;
588: regd &= mask;
589: regd |= regd16;
590: return base + regd;
591: #endif
592: }
593:
594: void MakeSR (void)
595: {
596: #if 0
597: assert((regs.t1 & 1) == regs.t1);
598: assert((regs.t0 & 1) == regs.t0);
599: assert((regs.s & 1) == regs.s);
600: assert((regs.m & 1) == regs.m);
601: assert((XFLG & 1) == XFLG);
602: assert((NFLG & 1) == NFLG);
603: assert((ZFLG & 1) == ZFLG);
604: assert((VFLG & 1) == VFLG);
605: assert((CFLG & 1) == CFLG);
606: #endif
607: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
608: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
609: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
610: | GET_CFLG);
611: }
612:
613: void MakeFromSR (void)
614: {
615: int oldm = regs.m;
616: int olds = regs.s;
617:
618: regs.t1 = (regs.sr >> 15) & 1;
619: regs.t0 = (regs.sr >> 14) & 1;
620: regs.s = (regs.sr >> 13) & 1;
621: regs.m = (regs.sr >> 12) & 1;
622: regs.intmask = (regs.sr >> 8) & 7;
623: SET_XFLG ((regs.sr >> 4) & 1);
624: SET_NFLG ((regs.sr >> 3) & 1);
625: SET_ZFLG ((regs.sr >> 2) & 1);
626: SET_VFLG ((regs.sr >> 1) & 1);
627: SET_CFLG (regs.sr & 1);
628: if (cpu_level >= 2) {
629: if (olds != regs.s) {
630: if (olds) {
631: if (oldm)
632: regs.msp = m68k_areg(regs, 7);
633: else
634: regs.isp = m68k_areg(regs, 7);
635: m68k_areg(regs, 7) = regs.usp;
636: } else {
637: regs.usp = m68k_areg(regs, 7);
638: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
639: }
640: } else if (olds && oldm != regs.m) {
641: if (oldm) {
642: regs.msp = m68k_areg(regs, 7);
643: m68k_areg(regs, 7) = regs.isp;
644: } else {
645: regs.isp = m68k_areg(regs, 7);
646: m68k_areg(regs, 7) = regs.msp;
647: }
648: }
649: } else {
650: if (olds != regs.s) {
651: if (olds) {
652: regs.isp = m68k_areg(regs, 7);
653: m68k_areg(regs, 7) = regs.usp;
654: } else {
655: regs.usp = m68k_areg(regs, 7);
656: m68k_areg(regs, 7) = regs.isp;
657: }
658: }
659: }
660:
661: set_special (SPCFLAG_INT);
662: if (regs.t1 || regs.t0)
663: set_special (SPCFLAG_TRACE);
664: else
1.1.1.6 root 665: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
666: SR-modifying instructions (including STOP). */
667: unset_special (SPCFLAG_TRACE);
1.1 root 668: }
669:
1.1.1.5 root 670:
1.1 root 671: void Exception(int nr, uaecptr oldpc)
672: {
673: uae_u32 currpc = m68k_getpc ();
674:
1.1.1.2 root 675: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 676:
1.1.1.7 ! root 677: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
! 678: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
1.1.1.5 root 679: {
1.1.1.6 root 680: if(!VDI())
1.1.1.5 root 681: {
1.1.1.6 root 682: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
683: * This will call OpCode_VDI after completion of Trap call!
684: * Use to modify return structure from VDI */
685: VDI_OldPC = currpc;
686: currpc = CART_VDI_OPCODE_ADDR;
1.1.1.5 root 687: }
688: }
689:
1.1 root 690: MakeSR();
691:
692: if (!regs.s) {
693: regs.usp = m68k_areg(regs, 7);
694: if (cpu_level >= 2)
695: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
696: else
697: m68k_areg(regs, 7) = regs.isp;
698: regs.s = 1;
699: }
700: if (cpu_level > 0) {
701: if (nr == 2 || nr == 3) {
702: int i;
703: /* @@@ this is probably wrong (?) */
704: for (i = 0 ; i < 12 ; i++) {
705: m68k_areg(regs, 7) -= 2;
706: put_word (m68k_areg(regs, 7), 0);
707: }
708: m68k_areg(regs, 7) -= 2;
709: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
710: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
711: m68k_areg(regs, 7) -= 4;
712: put_long (m68k_areg(regs, 7), oldpc);
713: m68k_areg(regs, 7) -= 2;
714: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
715: } else if (regs.m && nr >= 24 && nr < 32) {
716: m68k_areg(regs, 7) -= 2;
717: put_word (m68k_areg(regs, 7), nr * 4);
718: m68k_areg(regs, 7) -= 4;
719: put_long (m68k_areg(regs, 7), currpc);
720: m68k_areg(regs, 7) -= 2;
721: put_word (m68k_areg(regs, 7), regs.sr);
722: regs.sr |= (1 << 13);
723: regs.msp = m68k_areg(regs, 7);
724: m68k_areg(regs, 7) = regs.isp;
725: m68k_areg(regs, 7) -= 2;
726: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
727: } else {
728: m68k_areg(regs, 7) -= 2;
729: put_word (m68k_areg(regs, 7), nr * 4);
730: }
731: }
1.1.1.3 root 732:
733: /* Push PC on stack: */
1.1 root 734: m68k_areg(regs, 7) -= 4;
735: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 736: /* Push SR on stack: */
1.1 root 737: m68k_areg(regs, 7) -= 2;
738: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 739:
740: /* 68000 bus/address errors: */
1.1.1.7 ! root 741: /* Well these 8 more bytes are not here just for debuging.
! 742: It seems adebug expects them to be on the stack when it receives
! 743: a bus error... */
1.1.1.3 root 744: if (cpu_level==0 && (nr==2 || nr==3)) {
745: m68k_areg(regs, 7) -= 8;
746: if (nr == 3) { /* Address error */
1.1.1.7 ! root 747: put_word (m68k_areg(regs, 7), 0); /* FIXME: Add real function code value */
1.1.1.3 root 748: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
749: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
750: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
751: if( bEnableDebug ) {
752: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
753: DebugUI();
754: }
755: }
756: else { /* Bus error */
1.1.1.7 ! root 757: put_word (m68k_areg(regs, 7), 0); /* FIXME: Add real function code value */
1.1.1.3 root 758: put_long (m68k_areg(regs, 7)+2, BusAddressLocation);
1.1.1.7 ! root 759: put_word (m68k_areg(regs, 7)+6, BusErrorOpcode);
1.1.1.3 root 760: if( bEnableDebug && BusAddressLocation!=0xff8a00) {
1.1.1.7 ! root 761: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n",BusAddressLocation,(long)currpc);
1.1.1.3 root 762: DebugUI();
763: }
764: }
765: }
766:
1.1 root 767: m68k_setpc (get_long (regs.vbr + 4*nr));
768: fill_prefetch_0 ();
769: regs.t1 = regs.t0 = regs.m = 0;
770: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
1.1.1.6 root 771:
1.1.1.7 ! root 772: /* Handle exception cycles: */
! 773: if(nr >= 24 && nr <= 31)
! 774: {
! 775: ADD_CYCLES(44+4, 5, 3); /* Interrupt */
! 776: }
! 777: else if(nr >= 32 && nr <= 47)
! 778: {
! 779: ADD_CYCLES(34, 5, 3); /* Trap */
! 780: }
! 781: else switch(nr)
! 782: {
! 783: case 2: ADD_CYCLES(50, 4, 7); break; /* Bus error */
! 784: case 3: ADD_CYCLES(50, 4, 7); break; /* Address error */
! 785: case 4: ADD_CYCLES(34, 4, 3); break; /* Illegal instruction */
! 786: case 5: ADD_CYCLES(38, 4, 3); break; /* Div by zero */
! 787: case 6: ADD_CYCLES(40, 4, 3); break; /* CHK */
! 788: case 7: ADD_CYCLES(34, 5, 3); break; /* TRAPV */
! 789: case 8: ADD_CYCLES(34, 4, 3); break; /* Privilege violation */
! 790: case 9: ADD_CYCLES(34, 4, 3); break; /* Trace */
! 791: case 10: ADD_CYCLES(34, 4, 3); break; /* Line-A - probably wrong */
! 792: case 11: ADD_CYCLES(34, 4, 3); break; /* Line-F - probably wrong */
! 793: default:
! 794: #if 0 /* Hatari currently seems to run more instable when adding MFP cycles */
! 795: if(nr < 64)
! 796: ADD_CYCLES(0, 0, 0); /* Coprocessor and unassigned exceptions (???) */
! 797: else
! 798: ADD_CYCLES(44+4, 5, 3); /* Must be a MFP interrupt */
! 799: #endif
! 800: break;
1.1.1.6 root 801: }
1.1 root 802: }
803:
1.1.1.7 ! root 804:
1.1 root 805: static void Interrupt(int nr)
806: {
807: assert(nr < 8 && nr >= 0);
808: lastint_regs = regs;
809: lastint_no = nr;
810: Exception(nr+24, 0);
811:
812: regs.intmask = nr;
813: set_special (SPCFLAG_INT);
814: }
815:
1.1.1.7 ! root 816:
1.1.1.6 root 817: static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 818:
1.1.1.7 ! root 819:
1.1 root 820: int m68k_move2c (int regno, uae_u32 *regp)
821: {
822: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
823: || (cpu_level < 4 && (regno & 0x7FF) > 2)
824: || (cpu_level == 4 && regno == 0x802))
825: {
826: op_illg (0x4E7B);
827: return 0;
828: } else {
829: switch (regno) {
830: case 0: regs.sfc = *regp & 7; break;
831: case 1: regs.dfc = *regp & 7; break;
832: case 2: cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break;
833: case 3: tc = *regp & 0xc000; break;
834: /* Mask out fields that should be zero. */
835: case 4: itt0 = *regp & 0xffffe364; break;
836: case 5: itt1 = *regp & 0xffffe364; break;
837: case 6: dtt0 = *regp & 0xffffe364; break;
838: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 ! root 839:
1.1 root 840: case 0x800: regs.usp = *regp; break;
841: case 0x801: regs.vbr = *regp; break;
842: case 0x802: caar = *regp & 0xfc; break;
843: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
844: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 845: case 0x805: mmusr = *regp; break;
846: case 0x806: urp = *regp; break;
847: case 0x807: srp = *regp; break;
1.1 root 848: default:
849: op_illg (0x4E7B);
850: return 0;
851: }
852: }
853: return 1;
854: }
855:
856: int m68k_movec2 (int regno, uae_u32 *regp)
857: {
858: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
859: || (cpu_level < 4 && (regno & 0x7FF) > 2)
860: || (cpu_level == 4 && regno == 0x802))
861: {
862: op_illg (0x4E7A);
863: return 0;
864: } else {
865: switch (regno) {
866: case 0: *regp = regs.sfc; break;
867: case 1: *regp = regs.dfc; break;
868: case 2: *regp = cacr; break;
869: case 3: *regp = tc; break;
870: case 4: *regp = itt0; break;
871: case 5: *regp = itt1; break;
872: case 6: *regp = dtt0; break;
873: case 7: *regp = dtt1; break;
874: case 0x800: *regp = regs.usp; break;
875: case 0x801: *regp = regs.vbr; break;
876: case 0x802: *regp = caar; break;
877: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
878: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
879: case 0x805: *regp = mmusr; break;
1.1.1.6 root 880: case 0x806: *regp = urp; break;
881: case 0x807: *regp = srp; break;
1.1 root 882: default:
883: op_illg (0x4E7A);
884: return 0;
885: }
886: }
887: return 1;
888: }
889:
890: STATIC_INLINE int
891: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
892: {
893: uae_u32 q = 0, cbit = 0;
894: int i;
895:
896: if (div <= src_hi) {
897: return 1;
898: }
899: for (i = 0 ; i < 32 ; i++) {
900: cbit = src_hi & 0x80000000ul;
901: src_hi <<= 1;
902: if (src_lo & 0x80000000ul) src_hi++;
903: src_lo <<= 1;
904: q = q << 1;
905: if (cbit || div <= src_hi) {
906: q |= 1;
907: src_hi -= div;
908: }
909: }
910: *quot = q;
911: *rem = src_hi;
912: return 0;
913: }
914:
915: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
916: {
917: #if defined(uae_s64)
918: if (src == 0) {
919: Exception (5, oldpc);
920: return;
921: }
922: if (extra & 0x800) {
923: /* signed variant */
924: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
925: uae_s64 quot, rem;
926:
927: if (extra & 0x400) {
928: a &= 0xffffffffu;
929: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
930: }
931: rem = a % (uae_s64)(uae_s32)src;
932: quot = a / (uae_s64)(uae_s32)src;
933: if ((quot & UVAL64(0xffffffff80000000)) != 0
934: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
935: {
936: SET_VFLG (1);
937: SET_NFLG (1);
938: SET_CFLG (0);
939: } else {
940: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
941: SET_VFLG (0);
942: SET_CFLG (0);
943: SET_ZFLG (((uae_s32)quot) == 0);
944: SET_NFLG (((uae_s32)quot) < 0);
945: m68k_dreg(regs, extra & 7) = rem;
946: m68k_dreg(regs, (extra >> 12) & 7) = quot;
947: }
948: } else {
949: /* unsigned */
950: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
951: uae_u64 quot, rem;
952:
953: if (extra & 0x400) {
954: a &= 0xffffffffu;
955: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
956: }
957: rem = a % (uae_u64)src;
958: quot = a / (uae_u64)src;
959: if (quot > 0xffffffffu) {
960: SET_VFLG (1);
961: SET_NFLG (1);
962: SET_CFLG (0);
963: } else {
964: SET_VFLG (0);
965: SET_CFLG (0);
966: SET_ZFLG (((uae_s32)quot) == 0);
967: SET_NFLG (((uae_s32)quot) < 0);
968: m68k_dreg(regs, extra & 7) = rem;
969: m68k_dreg(regs, (extra >> 12) & 7) = quot;
970: }
971: }
972: #else
973: if (src == 0) {
974: Exception (5, oldpc);
975: return;
976: }
977: if (extra & 0x800) {
978: /* signed variant */
979: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
980: uae_s32 hi = lo < 0 ? -1 : 0;
981: uae_s32 save_high;
982: uae_u32 quot, rem;
983: uae_u32 sign;
984:
985: if (extra & 0x400) {
986: hi = (uae_s32)m68k_dreg(regs, extra & 7);
987: }
988: save_high = hi;
989: sign = (hi ^ src);
990: if (hi < 0) {
991: hi = ~hi;
992: lo = -lo;
993: if (lo == 0) hi++;
994: }
995: if ((uae_s32)src < 0) src = -src;
996: if (div_unsigned(hi, lo, src, ", &rem) ||
997: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
998: SET_VFLG (1);
999: SET_NFLG (1);
1000: SET_CFLG (0);
1001: } else {
1002: if (sign & 0x80000000) quot = -quot;
1003: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1004: SET_VFLG (0);
1005: SET_CFLG (0);
1006: SET_ZFLG (((uae_s32)quot) == 0);
1007: SET_NFLG (((uae_s32)quot) < 0);
1008: m68k_dreg(regs, extra & 7) = rem;
1009: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1010: }
1011: } else {
1012: /* unsigned */
1013: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1014: uae_u32 hi = 0;
1015: uae_u32 quot, rem;
1016:
1017: if (extra & 0x400) {
1018: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1019: }
1020: if (div_unsigned(hi, lo, src, ", &rem)) {
1021: SET_VFLG (1);
1022: SET_NFLG (1);
1023: SET_CFLG (0);
1024: } else {
1025: SET_VFLG (0);
1026: SET_CFLG (0);
1027: SET_ZFLG (((uae_s32)quot) == 0);
1028: SET_NFLG (((uae_s32)quot) < 0);
1029: m68k_dreg(regs, extra & 7) = rem;
1030: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1031: }
1032: }
1033: #endif
1034: }
1035:
1036: STATIC_INLINE void
1037: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1038: {
1039: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1040: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1041: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1042: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1043: uae_u32 lo;
1044:
1045: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1046: if (lo < r0) r3++;
1047: r0 = lo;
1048: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1049: if (lo < r0) r3++;
1050: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1051: *dst_lo = lo;
1052: *dst_hi = r3;
1053: }
1054:
1055: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1056: {
1057: #if defined(uae_s64)
1058: if (extra & 0x800) {
1059: /* signed variant */
1060: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1061:
1062: a *= (uae_s64)(uae_s32)src;
1063: SET_VFLG (0);
1064: SET_CFLG (0);
1065: SET_ZFLG (a == 0);
1066: SET_NFLG (a < 0);
1067: if (extra & 0x400)
1068: m68k_dreg(regs, extra & 7) = a >> 32;
1069: else if ((a & UVAL64(0xffffffff80000000)) != 0
1070: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1071: {
1072: SET_VFLG (1);
1073: }
1074: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1075: } else {
1076: /* unsigned */
1077: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1078:
1079: a *= (uae_u64)src;
1080: SET_VFLG (0);
1081: SET_CFLG (0);
1082: SET_ZFLG (a == 0);
1083: SET_NFLG (((uae_s64)a) < 0);
1084: if (extra & 0x400)
1085: m68k_dreg(regs, extra & 7) = a >> 32;
1086: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1087: SET_VFLG (1);
1088: }
1089: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1090: }
1091: #else
1092: if (extra & 0x800) {
1093: /* signed variant */
1094: uae_s32 src1,src2;
1095: uae_u32 dst_lo,dst_hi;
1096: uae_u32 sign;
1097:
1098: src1 = (uae_s32)src;
1099: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1100: sign = (src1 ^ src2);
1101: if (src1 < 0) src1 = -src1;
1102: if (src2 < 0) src2 = -src2;
1103: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1104: if (sign & 0x80000000) {
1105: dst_hi = ~dst_hi;
1106: dst_lo = -dst_lo;
1107: if (dst_lo == 0) dst_hi++;
1108: }
1109: SET_VFLG (0);
1110: SET_CFLG (0);
1111: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1112: SET_NFLG (((uae_s32)dst_hi) < 0);
1113: if (extra & 0x400)
1114: m68k_dreg(regs, extra & 7) = dst_hi;
1115: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1116: && ((dst_hi & 0xffffffff) != 0xffffffff
1117: || (dst_lo & 0x80000000) != 0x80000000))
1118: {
1119: SET_VFLG (1);
1120: }
1121: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1122: } else {
1123: /* unsigned */
1124: uae_u32 dst_lo,dst_hi;
1125:
1126: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1127:
1128: SET_VFLG (0);
1129: SET_CFLG (0);
1130: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1131: SET_NFLG (((uae_s32)dst_hi) < 0);
1132: if (extra & 0x400)
1133: m68k_dreg(regs, extra & 7) = dst_hi;
1134: else if (dst_hi != 0) {
1135: SET_VFLG (1);
1136: }
1137: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1138: }
1139: #endif
1140: }
1.1.1.6 root 1141:
1.1 root 1142: static char* ccnames[] =
1143: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1144: "VC","VS","PL","MI","GE","LT","GT","LE" };
1145:
1146: void m68k_reset (void)
1147: {
1148: regs.s = 1;
1149: regs.m = 0;
1150: regs.stopped = 0;
1151: regs.t1 = 0;
1152: regs.t0 = 0;
1153: SET_ZFLG (0);
1154: SET_XFLG (0);
1155: SET_CFLG (0);
1156: SET_VFLG (0);
1157: SET_NFLG (0);
1.1.1.7 ! root 1158: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1159: regs.intmask = 7;
1160: regs.vbr = regs.sfc = regs.dfc = 0;
1161: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 ! root 1162:
! 1163: m68k_areg(regs, 7) = get_long(0);
! 1164: m68k_setpc(get_long(4));
! 1165: refill_prefetch (m68k_getpc(), 0);
1.1 root 1166: }
1167:
1168: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1169: {
1170: uaecptr pc = m68k_getpc ();
1.1.1.6 root 1171:
1172: if (opcode == 0x4E7B && get_long (0x10) == 0 ) {
1.1 root 1173: write_log ("This program requires a 68020 CPU!\n");
1174: broken_in = 1;
1175: set_special (SPCFLAG_BRK);
1.1.1.4 root 1176: bQuitProgram = 1;
1.1 root 1177: }
1.1.1.6 root 1178:
1179: if ((opcode & 0xF000) == 0xF000) {
1.1 root 1180: Exception(0xB,0);
1181: return 4;
1.1.1.6 root 1182: }
1183: if ((opcode & 0xF000) == 0xA000) {
1.1 root 1184: Exception(0xA,0);
1185: return 4;
1.1.1.6 root 1186: }
1.1 root 1187:
1.1.1.3 root 1188: #if 0
1.1.1.6 root 1189: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1190: #endif
1191: Exception (4,0);
1192: return 4;
1193: }
1194:
1195: void mmu_op(uae_u32 opcode, uae_u16 extra)
1196: {
1197: if ((opcode & 0xFE0) == 0x0500) {
1198: /* PFLUSH */
1199: mmusr = 0;
1200: write_log ("PFLUSH\n");
1201: } else if ((opcode & 0x0FD8) == 0x548) {
1202: /* PTEST */
1203: write_log ("PTEST\n");
1204: } else
1205: op_illg (opcode);
1206: }
1207:
1208:
1209: static uaecptr last_trace_ad = 0;
1210:
1211: static void do_trace (void)
1212: {
1213: if (regs.t0 && cpu_level >= 2) {
1214: uae_u16 opcode;
1215: /* should also include TRAP, CHK, SR modification FPcc */
1216: /* probably never used so why bother */
1217: /* We can afford this to be inefficient... */
1218: m68k_setpc (m68k_getpc ());
1219: fill_prefetch_0 ();
1220: opcode = get_word (regs.pc);
1221: if (opcode == 0x4e72 /* RTE */
1222: || opcode == 0x4e74 /* RTD */
1223: || opcode == 0x4e75 /* RTS */
1224: || opcode == 0x4e77 /* RTR */
1225: || opcode == 0x4e76 /* TRAPV */
1226: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1227: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1228: || (opcode & 0xff00) == 0x6100 /* BSR */
1229: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1230: && cctrue((opcode >> 8) & 0xf))
1231: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1232: && !cctrue((opcode >> 8) & 0xf)
1233: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1234: {
1235: last_trace_ad = m68k_getpc ();
1236: unset_special (SPCFLAG_TRACE);
1237: set_special (SPCFLAG_DOTRACE);
1238: }
1239: } else if (regs.t1) {
1240: last_trace_ad = m68k_getpc ();
1241: unset_special (SPCFLAG_TRACE);
1242: set_special (SPCFLAG_DOTRACE);
1243: }
1244: }
1245:
1246:
1247: static int do_specialties (void)
1248: {
1.1.1.7 ! root 1249: if(regs.spcflags & SPCFLAG_BUSERROR) {
! 1250: /* We can not execute bus errors directly in the memory handler
! 1251: * functions since the PC should point to the address of the next
! 1252: * instruction, so we're executing the bus errors here: */
! 1253: unset_special(SPCFLAG_BUSERROR);
! 1254: Exception(2,0);
! 1255: }
! 1256:
1.1 root 1257: if (regs.spcflags & SPCFLAG_DOTRACE) {
1258: Exception (9,last_trace_ad);
1259: }
1260: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.6 root 1261: do_cycles (8);
1.1.1.5 root 1262: if (regs.intmask>5) {
1263: /* We still have to care about events when IPL==7 ! */
1264: Main_EventHandler();
1265: if(bQuitProgram) unset_special(SPCFLAG_STOP);
1266: }
1267: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1268: int intr = intlev ();
1.1 root 1269: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1270: if (intr != -1 && intr > regs.intmask) {
1.1 root 1271: Interrupt (intr);
1272: regs.stopped = 0;
1273: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1274: }
1.1 root 1275: }
1276: }
1277: if (regs.spcflags & SPCFLAG_TRACE)
1278: do_trace ();
1279:
1280: if (regs.spcflags & SPCFLAG_DOINT) {
1.1.1.6 root 1281: int intr = intlev ();
1.1 root 1282: unset_special (SPCFLAG_DOINT);
1.1.1.6 root 1283: if (intr != -1 && intr > regs.intmask) {
1.1 root 1284: Interrupt (intr);
1285: regs.stopped = 0;
1.1.1.6 root 1286: }
1.1 root 1287: }
1288: if (regs.spcflags & SPCFLAG_INT) {
1289: unset_special (SPCFLAG_INT);
1290: set_special (SPCFLAG_DOINT);
1291: }
1292: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1293: unset_special (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1294: return 1;
1295: }
1296: return 0;
1297: }
1298:
1.1.1.3 root 1299:
1.1 root 1300: /* It's really sad to have two almost identical functions for this, but we
1301: do it all for performance... :( */
1302: static void m68k_run_1 (void)
1303: {
1304: #ifdef DEBUG_PREFETCH
1305: uae_u8 saved_bytes[20];
1306: uae_u16 *oldpcp;
1307: #endif
1.1.1.4 root 1308: while(!bQuitProgram) {
1.1 root 1309: int cycles;
1310: uae_u32 opcode = get_iword_prefetch (0);
1311: #ifdef DEBUG_PREFETCH
1312: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1313: fprintf (stderr, "Prefetch differs from memory.\n");
1314: debugging = 1;
1315: return;
1316: }
1317: oldpcp = regs.pc_p;
1318: memcpy (saved_bytes, regs.pc_p, 20);
1319: #endif
1320:
1321: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1322: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1323:
1324: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1325: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1326: #if COUNT_INSTRS == 2
1327: if (table68k[opcode].handler != -1)
1328: instrcount[table68k[opcode].handler]++;
1329: #elif COUNT_INSTRS == 1
1330: instrcount[opcode]++;
1331: #endif
1.1.1.2 root 1332:
1.1.1.6 root 1333: cycles = (*cpufunctbl[opcode])(opcode);
1334:
1.1 root 1335: #ifdef DEBUG_PREFETCH
1336: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1337: fprintf (stderr, "Self-modifying code detected.\n");
1338: set_special (SPCFLAG_BRK);
1339: debugging = 1;
1340: }
1341: #endif
1.1.1.2 root 1342:
1.1 root 1343: do_cycles (cycles);
1344: if (regs.spcflags) {
1345: if (do_specialties ())
1346: return;
1347: }
1348: }
1349: }
1350:
1351:
1352: /* Same thing, but don't use prefetch to get opcode. */
1353: static void m68k_run_2 (void)
1354: {
1.1.1.4 root 1355: while(!bQuitProgram) {
1.1 root 1356: int cycles;
1357: uae_u32 opcode = get_iword (0);
1358:
1359: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1360: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1361:
1362: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1363: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1364: #if COUNT_INSTRS == 2
1365: if (table68k[opcode].handler != -1)
1366: instrcount[table68k[opcode].handler]++;
1367: #elif COUNT_INSTRS == 1
1368: instrcount[opcode]++;
1369: #endif
1.1.1.2 root 1370:
1.1.1.6 root 1371: cycles = (*cpufunctbl[opcode])(opcode);
1372:
1.1 root 1373: do_cycles (cycles);
1374: if (regs.spcflags) {
1375: if (do_specialties ())
1376: return;
1377: }
1378: }
1379: }
1380:
1381:
1382: int in_m68k_go = 0;
1383:
1384: void m68k_go (int may_quit)
1385: {
1386: if (in_m68k_go || !may_quit) {
1387: write_log ("Bug! m68k_go is not reentrant.\n");
1388: abort ();
1389: }
1390:
1391: in_m68k_go++;
1.1.1.4 root 1392: while(!bQuitProgram) {
1.1.1.2 root 1393: if(cpu_compatible)
1394: m68k_run_1();
1395: else
1396: m68k_run_2();
1.1 root 1397: }
1398: in_m68k_go--;
1399: }
1400:
1401: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1402: {
1403: uae_u32 opcode, val;
1404: struct instr *dp;
1405:
1406: opcode = get_iword_1(0);
1407: last_op_for_exception_3 = opcode;
1408: m68kpc_offset = 2;
1409:
1.1.1.6 root 1410: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1411: opcode = 0x4AFC;
1412: }
1413: dp = table68k + opcode;
1414:
1415: if (dp->suse) {
1416: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1417: Exception (3, 0);
1418: return;
1419: }
1420: }
1421: if (dp->duse) {
1422: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1423: Exception (3, 0);
1424: return;
1425: }
1426: }
1427: }
1428:
1429: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1430: {
1431: uaecptr newpc = 0;
1432: m68kpc_offset = addr - m68k_getpc ();
1433: while (cnt-- > 0) {
1434: char instrname[20],*ccpt;
1435: int opwords;
1436: uae_u32 opcode;
1437: struct mnemolookup *lookup;
1438: struct instr *dp;
1439: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1440: for (opwords = 0; opwords < 5; opwords++){
1441: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1442: }
1443: opcode = get_iword_1 (m68kpc_offset);
1444: m68kpc_offset += 2;
1.1.1.6 root 1445: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1446: opcode = 0x4AFC;
1447: }
1448: dp = table68k + opcode;
1449: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1450: ;
1451:
1452: strcpy (instrname, lookup->name);
1453: ccpt = strstr (instrname, "cc");
1454: if (ccpt != 0) {
1455: strncpy (ccpt, ccnames[dp->cc], 2);
1456: }
1457: fprintf (f, "%s", instrname);
1458: switch (dp->size){
1459: case sz_byte: fprintf (f, ".B "); break;
1460: case sz_word: fprintf (f, ".W "); break;
1461: case sz_long: fprintf (f, ".L "); break;
1462: default: fprintf (f, " "); break;
1463: }
1464:
1465: if (dp->suse) {
1466: newpc = m68k_getpc () + m68kpc_offset;
1467: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1468: }
1469: if (dp->suse && dp->duse)
1470: fprintf (f, ",");
1471: if (dp->duse) {
1472: newpc = m68k_getpc () + m68kpc_offset;
1473: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1474: }
1475: if (ccpt != 0) {
1476: if (cctrue(dp->cc))
1.1.1.5 root 1477: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1478: else
1.1.1.5 root 1479: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1480: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1481: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1482: fprintf (f, "\n");
1483: }
1484: if (nextpc)
1485: *nextpc = m68k_getpc () + m68kpc_offset;
1486: }
1487:
1488: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1489: {
1490: int i;
1491: for (i = 0; i < 8; i++){
1.1.1.5 root 1492: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1493: if ((i & 3) == 3) fprintf (f, "\n");
1494: }
1495: for (i = 0; i < 8; i++){
1.1.1.5 root 1496: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1497: if ((i & 3) == 3) fprintf (f, "\n");
1498: }
1499: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1500: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1501: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1502: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1503: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1504: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1505: regs.t1, regs.t0, regs.s, regs.m,
1506: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1507: for (i = 0; i < 8; i++){
1508: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1509: if ((i & 3) == 3) fprintf (f, "\n");
1510: }
1511: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1512: (regs.fpsr & 0x8000000) != 0,
1513: (regs.fpsr & 0x4000000) != 0,
1514: (regs.fpsr & 0x2000000) != 0,
1515: (regs.fpsr & 0x1000000) != 0);
1516: if (cpu_compatible)
1517: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1518:
1519: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1520: if (nextpc)
1.1.1.5 root 1521: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1522: }
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