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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.8 ! root 13: char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.35 2004/06/11 10:04:47 thothy Exp $";
1.1 root 14:
15: #include "sysdeps.h"
16: #include "hatari-glue.h"
17: #include "maccess.h"
18: #include "memory.h"
19: #include "newcpu.h"
1.1.1.5 root 20: #include "../includes/main.h"
1.1.1.7 root 21: #include "../includes/m68000.h"
1.1.1.8 ! root 22: #include "../includes/mfp.h"
1.1 root 23: #include "../includes/tos.h"
1.1.1.5 root 24: #include "../includes/vdi.h"
25: #include "../includes/cart.h"
26: #include "../includes/debugui.h"
1.1.1.8 ! root 27: #include "../includes/bios.h"
! 28: #include "../includes/xbios.h"
1.1 root 29:
30:
31: struct flag_struct regflags;
32:
33: /* Opcode of faulting instruction */
34: uae_u16 last_op_for_exception_3;
35: /* PC at fault time */
36: uaecptr last_addr_for_exception_3;
37: /* Address that generated the exception */
38: uaecptr last_fault_for_exception_3;
39:
40: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
41: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
42:
43: int movem_index1[256];
44: int movem_index2[256];
45: int movem_next[256];
46:
47: int fpp_movem_index1[256];
48: int fpp_movem_index2[256];
49: int fpp_movem_next[256];
50:
51: cpuop_func *cpufunctbl[65536];
52:
1.1.1.6 root 53:
1.1 root 54: #define COUNT_INSTRS 0
55:
56: #if COUNT_INSTRS
57: static unsigned long int instrcount[65536];
58: static uae_u16 opcodenums[65536];
59:
60: static int compfn (const void *el1, const void *el2)
61: {
62: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
63: }
64:
65: static char *icountfilename (void)
66: {
67: char *name = getenv ("INSNCOUNT");
68: if (name)
69: return name;
70: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
71: }
72:
73: void dump_counts (void)
74: {
75: FILE *f = fopen (icountfilename (), "w");
76: unsigned long int total;
77: int i;
78:
79: write_log ("Writing instruction count file...\n");
80: for (i = 0; i < 65536; i++) {
81: opcodenums[i] = i;
82: total += instrcount[i];
83: }
84: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
85:
86: fprintf (f, "Total: %lu\n", total);
87: for (i=0; i < 65536; i++) {
88: unsigned long int cnt = instrcount[opcodenums[i]];
89: struct instr *dp;
90: struct mnemolookup *lookup;
91: if (!cnt)
92: break;
93: dp = table68k + opcodenums[i];
94: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
95: ;
96: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
97: }
98: fclose (f);
99: }
100: #else
101: void dump_counts (void)
102: {
103: }
104: #endif
105:
106:
107: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
108:
109: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
110: {
1.1.1.6 root 111: op_illg (opcode);
1.1 root 112: return 4;
113: }
114:
1.1.1.4 root 115:
116: void build_cpufunctbl(void)
1.1 root 117: {
118: int i;
119: unsigned long opcode;
120: struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff
121: : cpu_level == 3 ? op_smalltbl_1_ff
122: : cpu_level == 2 ? op_smalltbl_2_ff
123: : cpu_level == 1 ? op_smalltbl_3_ff
124: : ! cpu_compatible ? op_smalltbl_4_ff
125: : op_smalltbl_5_ff);
126:
127: write_log ("Building CPU function table (%d %d %d).\n",
128: cpu_level, cpu_compatible, address_space_24);
129:
130: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 131: cpufunctbl[opcode] = op_illg_1;
1.1 root 132: for (i = 0; tbl[i].handler != NULL; i++) {
133: if (! tbl[i].specific)
1.1.1.6 root 134: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 135: }
136: for (opcode = 0; opcode < 65536; opcode++) {
137: cpuop_func *f;
138:
139: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
140: continue;
141:
142: if (table68k[opcode].handler != -1) {
1.1.1.6 root 143: f = cpufunctbl[table68k[opcode].handler];
1.1 root 144: if (f == op_illg_1)
145: abort();
1.1.1.6 root 146: cpufunctbl[opcode] = f;
1.1 root 147: }
148: }
149: for (i = 0; tbl[i].handler != NULL; i++) {
150: if (tbl[i].specific)
1.1.1.6 root 151: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 152: }
153:
1.1.1.6 root 154: /* Hatari's illegal opcodes: */
155: cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos;
156: cpufunctbl[RUNOLDGEMDOS_OPCODE] = OpCode_OldGemDos;
1.1.1.7 root 157: cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit;
1.1.1.6 root 158: cpufunctbl[VDI_OPCODE] = OpCode_VDI;
1.1 root 159: }
160:
161:
162:
163: void init_m68k (void)
164: {
165: int i;
166:
167: for (i = 0 ; i < 256 ; i++) {
168: int j;
169: for (j = 0 ; j < 8 ; j++) {
170: if (i & (1 << j)) break;
171: }
172: movem_index1[i] = j;
173: movem_index2[i] = 7-j;
174: movem_next[i] = i & (~(1 << j));
175: }
176: for (i = 0 ; i < 256 ; i++) {
177: int j;
178: for (j = 7 ; j >= 0 ; j--) {
179: if (i & (1 << j)) break;
180: }
181: fpp_movem_index1[i] = 7-j;
182: fpp_movem_index2[i] = j;
183: fpp_movem_next[i] = i & (~(1 << j));
184: }
185: #if COUNT_INSTRS
186: {
187: FILE *f = fopen (icountfilename (), "r");
188: memset (instrcount, 0, sizeof instrcount);
189: if (f) {
190: uae_u32 opcode, count, total;
191: char name[20];
192: write_log ("Reading instruction count file...\n");
193: fscanf (f, "Total: %lu\n", &total);
194: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
195: instrcount[opcode] = count;
196: }
197: fclose(f);
198: }
199: }
200: #endif
201: write_log ("Building CPU table for configuration: 68");
202: if (address_space_24 && cpu_level > 1)
203: write_log ("EC");
204: switch (cpu_level) {
205: case 1:
206: write_log ("010");
207: break;
208: case 2:
209: write_log ("020");
210: break;
211: case 3:
212: write_log ("020/881");
213: break;
214: case 4:
215: /* Who is going to miss the MMU anyway...? :-) */
216: write_log ("040");
217: break;
218: default:
219: write_log ("000");
220: break;
221: }
222: if (cpu_compatible)
223: write_log (" (compatible mode)");
224: write_log ("\n");
1.1.1.7 root 225:
1.1 root 226: read_table68k ();
227: do_merges ();
228:
229: write_log ("%d CPU functions\n", nr_cpuop_funcs);
230:
231: build_cpufunctbl ();
232: }
233:
1.1.1.4 root 234:
1.1 root 235: struct regstruct regs, lastint_regs;
1.1.1.8 ! root 236: /* not used ATM:
1.1 root 237: static struct regstruct regs_backup[16];
238: static int backup_pointer = 0;
1.1.1.8 ! root 239: */
1.1 root 240: static long int m68kpc_offset;
241: int lastint_no;
242:
243: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
244: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
245: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
246:
247: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
248: {
249: uae_u16 dp;
250: uae_s8 disp8;
251: uae_s16 disp16;
252: int r;
253: uae_u32 dispreg;
254: uaecptr addr;
255: uae_s32 offset = 0;
256: char buffer[80];
257:
258: switch (mode){
259: case Dreg:
260: sprintf (buffer,"D%d", reg);
261: break;
262: case Areg:
263: sprintf (buffer,"A%d", reg);
264: break;
265: case Aind:
266: sprintf (buffer,"(A%d)", reg);
267: break;
268: case Aipi:
269: sprintf (buffer,"(A%d)+", reg);
270: break;
271: case Apdi:
272: sprintf (buffer,"-(A%d)", reg);
273: break;
274: case Ad16:
275: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
276: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
277: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
278: (unsigned long)addr);
279: break;
280: case Ad8r:
281: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
282: disp8 = dp & 0xFF;
283: r = (dp & 0x7000) >> 12;
284: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
285: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
286: dispreg <<= (dp >> 9) & 3;
287:
288: if (dp & 0x100) {
289: uae_s32 outer = 0, disp = 0;
290: uae_s32 base = m68k_areg(regs,reg);
291: char name[10];
292: sprintf (name,"A%d, ",reg);
293: if (dp & 0x80) { base = 0; name[0] = 0; }
294: if (dp & 0x40) dispreg = 0;
295: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
296: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
297: base += disp;
298:
299: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
300: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
301:
302: if (!(dp & 4)) base += dispreg;
303: if (dp & 3) base = get_long (base);
304: if (dp & 4) base += dispreg;
305:
306: addr = base + outer;
307: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
308: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
309: 1 << ((dp >> 9) & 3),
1.1.1.5 root 310: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 311: } else {
312: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
313: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
314: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
315: 1 << ((dp >> 9) & 3), disp8,
316: (unsigned long)addr);
317: }
318: break;
319: case PC16:
320: addr = m68k_getpc () + m68kpc_offset;
321: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
322: addr += (uae_s16)disp16;
323: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
324: break;
325: case PC8r:
326: addr = m68k_getpc () + m68kpc_offset;
327: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
328: disp8 = dp & 0xFF;
329: r = (dp & 0x7000) >> 12;
330: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
331: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
332: dispreg <<= (dp >> 9) & 3;
333:
334: if (dp & 0x100) {
335: uae_s32 outer = 0,disp = 0;
336: uae_s32 base = addr;
337: char name[10];
338: sprintf (name,"PC, ");
339: if (dp & 0x80) { base = 0; name[0] = 0; }
340: if (dp & 0x40) dispreg = 0;
341: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
342: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
343: base += disp;
344:
345: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
346: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
347:
348: if (!(dp & 4)) base += dispreg;
349: if (dp & 3) base = get_long (base);
350: if (dp & 4) base += dispreg;
351:
352: addr = base + outer;
353: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
354: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
355: 1 << ((dp >> 9) & 3),
1.1.1.5 root 356: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 357: } else {
358: addr += (uae_s32)((uae_s8)disp8) + dispreg;
359: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
360: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
361: disp8, (unsigned long)addr);
362: }
363: break;
364: case absw:
365: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
366: m68kpc_offset += 2;
367: break;
368: case absl:
369: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
370: m68kpc_offset += 4;
371: break;
372: case imm:
373: switch (size){
374: case sz_byte:
375: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
376: m68kpc_offset += 2;
377: break;
378: case sz_word:
379: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
380: m68kpc_offset += 2;
381: break;
382: case sz_long:
383: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
384: m68kpc_offset += 4;
385: break;
386: default:
387: break;
388: }
389: break;
390: case imm0:
391: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
392: m68kpc_offset += 2;
393: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
394: break;
395: case imm1:
396: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
397: m68kpc_offset += 2;
398: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
399: break;
400: case imm2:
401: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
402: m68kpc_offset += 4;
403: sprintf (buffer,"#$%08lx", (unsigned long)offset);
404: break;
405: case immi:
406: offset = (uae_s32)(uae_s8)(reg & 0xff);
407: sprintf (buffer,"#$%08lx", (unsigned long)offset);
408: break;
409: default:
410: break;
411: }
412: if (buf == 0)
413: fprintf (f, "%s", buffer);
414: else
415: strcat (buf, buffer);
416: return offset;
417: }
418:
1.1.1.8 ! root 419:
1.1 root 420: /* The plan is that this will take over the job of exception 3 handling -
421: * the CPU emulation functions will just do a longjmp to m68k_go whenever
422: * they hit an odd address. */
1.1.1.8 ! root 423: #if 0
1.1 root 424: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
425: {
426: uae_u16 dp;
427: uae_s8 disp8;
428: uae_s16 disp16;
429: int r;
430: uae_u32 dispreg;
431: uaecptr addr;
1.1.1.5 root 432: /*uae_s32 offset = 0;*/
1.1 root 433:
434: switch (mode){
435: case Dreg:
436: *val = m68k_dreg (regs, reg);
437: return 1;
438: case Areg:
439: *val = m68k_areg (regs, reg);
440: return 1;
441:
442: case Aind:
443: case Aipi:
444: addr = m68k_areg (regs, reg);
445: break;
446: case Apdi:
447: addr = m68k_areg (regs, reg);
448: break;
449: case Ad16:
450: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
451: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
452: break;
453: case Ad8r:
454: addr = m68k_areg (regs, reg);
455: d8r_common:
456: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
457: disp8 = dp & 0xFF;
458: r = (dp & 0x7000) >> 12;
459: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
460: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
461: dispreg <<= (dp >> 9) & 3;
462:
463: if (dp & 0x100) {
464: uae_s32 outer = 0, disp = 0;
465: uae_s32 base = addr;
466: if (dp & 0x80) base = 0;
467: if (dp & 0x40) dispreg = 0;
468: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
469: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
470: base += disp;
471:
472: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
473: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
474:
475: if (!(dp & 4)) base += dispreg;
476: if (dp & 3) base = get_long (base);
477: if (dp & 4) base += dispreg;
478:
479: addr = base + outer;
480: } else {
481: addr += (uae_s32)((uae_s8)disp8) + dispreg;
482: }
483: break;
484: case PC16:
485: addr = m68k_getpc () + m68kpc_offset;
486: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
487: addr += (uae_s16)disp16;
488: break;
489: case PC8r:
490: addr = m68k_getpc () + m68kpc_offset;
491: goto d8r_common;
492: case absw:
493: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
494: m68kpc_offset += 2;
495: break;
496: case absl:
497: addr = get_ilong_1 (m68kpc_offset);
498: m68kpc_offset += 4;
499: break;
500: case imm:
501: switch (size){
502: case sz_byte:
503: *val = get_iword_1 (m68kpc_offset) & 0xff;
504: m68kpc_offset += 2;
505: break;
506: case sz_word:
507: *val = get_iword_1 (m68kpc_offset) & 0xffff;
508: m68kpc_offset += 2;
509: break;
510: case sz_long:
511: *val = get_ilong_1 (m68kpc_offset);
512: m68kpc_offset += 4;
513: break;
514: default:
515: break;
516: }
517: return 1;
518: case imm0:
519: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
520: m68kpc_offset += 2;
521: return 1;
522: case imm1:
523: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
524: m68kpc_offset += 2;
525: return 1;
526: case imm2:
527: *val = get_ilong_1 (m68kpc_offset);
528: m68kpc_offset += 4;
529: return 1;
530: case immi:
531: *val = (uae_s32)(uae_s8)(reg & 0xff);
532: return 1;
533: default:
534: addr = 0;
535: break;
536: }
537: if ((addr & 1) == 0)
538: return 1;
539:
540: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
541: last_fault_for_exception_3 = addr;
542: return 0;
543: }
1.1.1.8 ! root 544: #endif
! 545:
1.1 root 546:
547: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
548: {
549: int reg = (dp >> 12) & 15;
550: uae_s32 regd = regs.regs[reg];
551: if ((dp & 0x800) == 0)
552: regd = (uae_s32)(uae_s16)regd;
553: regd <<= (dp >> 9) & 3;
554: if (dp & 0x100) {
555: uae_s32 outer = 0;
556: if (dp & 0x80) base = 0;
557: if (dp & 0x40) regd = 0;
558:
559: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
560: if ((dp & 0x30) == 0x30) base += next_ilong();
561:
562: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
563: if ((dp & 0x3) == 0x3) outer = next_ilong();
564:
565: if ((dp & 0x4) == 0) base += regd;
566: if (dp & 0x3) base = get_long (base);
567: if (dp & 0x4) base += regd;
568:
569: return base + outer;
570: } else {
571: return base + (uae_s32)((uae_s8)dp) + regd;
572: }
573: }
574:
575: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
576: {
577: int reg = (dp >> 12) & 15;
578: uae_s32 regd = regs.regs[reg];
579: #if 1
580: if ((dp & 0x800) == 0)
581: regd = (uae_s32)(uae_s16)regd;
582: return base + (uae_s8)dp + regd;
583: #else
584: /* Branch-free code... benchmark this again now that
585: * things are no longer inline. */
586: uae_s32 regd16;
587: uae_u32 mask;
588: mask = ((dp & 0x800) >> 11) - 1;
589: regd16 = (uae_s32)(uae_s16)regd;
590: regd16 &= mask;
591: mask = ~mask;
592: base += (uae_s8)dp;
593: regd &= mask;
594: regd |= regd16;
595: return base + regd;
596: #endif
597: }
598:
1.1.1.8 ! root 599:
! 600: /* Create the Status Register from the flags */
1.1 root 601: void MakeSR (void)
602: {
603: #if 0
604: assert((regs.t1 & 1) == regs.t1);
605: assert((regs.t0 & 1) == regs.t0);
606: assert((regs.s & 1) == regs.s);
607: assert((regs.m & 1) == regs.m);
608: assert((XFLG & 1) == XFLG);
609: assert((NFLG & 1) == NFLG);
610: assert((ZFLG & 1) == ZFLG);
611: assert((VFLG & 1) == VFLG);
612: assert((CFLG & 1) == CFLG);
613: #endif
614: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
615: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
616: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
617: | GET_CFLG);
618: }
619:
1.1.1.8 ! root 620:
! 621: /* Set up the flags from Status Register */
1.1 root 622: void MakeFromSR (void)
623: {
624: int oldm = regs.m;
625: int olds = regs.s;
626:
627: regs.t1 = (regs.sr >> 15) & 1;
628: regs.t0 = (regs.sr >> 14) & 1;
629: regs.s = (regs.sr >> 13) & 1;
630: regs.m = (regs.sr >> 12) & 1;
631: regs.intmask = (regs.sr >> 8) & 7;
632: SET_XFLG ((regs.sr >> 4) & 1);
633: SET_NFLG ((regs.sr >> 3) & 1);
634: SET_ZFLG ((regs.sr >> 2) & 1);
635: SET_VFLG ((regs.sr >> 1) & 1);
636: SET_CFLG (regs.sr & 1);
637: if (cpu_level >= 2) {
638: if (olds != regs.s) {
639: if (olds) {
640: if (oldm)
641: regs.msp = m68k_areg(regs, 7);
642: else
643: regs.isp = m68k_areg(regs, 7);
644: m68k_areg(regs, 7) = regs.usp;
645: } else {
646: regs.usp = m68k_areg(regs, 7);
647: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
648: }
649: } else if (olds && oldm != regs.m) {
650: if (oldm) {
651: regs.msp = m68k_areg(regs, 7);
652: m68k_areg(regs, 7) = regs.isp;
653: } else {
654: regs.isp = m68k_areg(regs, 7);
655: m68k_areg(regs, 7) = regs.msp;
656: }
657: }
658: } else {
659: if (olds != regs.s) {
660: if (olds) {
661: regs.isp = m68k_areg(regs, 7);
662: m68k_areg(regs, 7) = regs.usp;
663: } else {
664: regs.usp = m68k_areg(regs, 7);
665: m68k_areg(regs, 7) = regs.isp;
666: }
667: }
668: }
669:
1.1.1.8 ! root 670: /* Pending interrupts can occur again after a write to the SR: */
! 671: set_special (SPCFLAG_DOINT);
1.1 root 672: if (regs.t1 || regs.t0)
673: set_special (SPCFLAG_TRACE);
674: else
1.1.1.6 root 675: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
676: SR-modifying instructions (including STOP). */
677: unset_special (SPCFLAG_TRACE);
1.1 root 678: }
679:
1.1.1.5 root 680:
1.1 root 681: void Exception(int nr, uaecptr oldpc)
682: {
683: uae_u32 currpc = m68k_getpc ();
684:
1.1.1.2 root 685: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 686:
1.1.1.7 root 687: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
688: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
1.1.1.5 root 689: {
1.1.1.6 root 690: if(!VDI())
1.1.1.5 root 691: {
1.1.1.6 root 692: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
693: * This will call OpCode_VDI after completion of Trap call!
694: * Use to modify return structure from VDI */
695: VDI_OldPC = currpc;
696: currpc = CART_VDI_OPCODE_ADDR;
1.1.1.5 root 697: }
698: }
699:
1.1.1.8 ! root 700: #if 0
! 701: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
! 702: if (nr == 0x2d)
! 703: {
! 704: /* Intercept BIOS calls */
! 705: if (Bios()) return;
! 706: }
! 707: else if (nr == 0x2e)
! 708: {
! 709: /* Intercept XBIOS calls */
! 710: if (XBios()) return;
! 711: }
! 712: #endif
! 713:
1.1 root 714: MakeSR();
715:
1.1.1.8 ! root 716: /* Change to supervisor mode if necessary */
1.1 root 717: if (!regs.s) {
718: regs.usp = m68k_areg(regs, 7);
719: if (cpu_level >= 2)
720: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
721: else
722: m68k_areg(regs, 7) = regs.isp;
723: regs.s = 1;
724: }
1.1.1.8 ! root 725:
! 726: /* Build additional exception stack frame for 68010 and higher */
1.1 root 727: if (cpu_level > 0) {
728: if (nr == 2 || nr == 3) {
729: int i;
730: /* @@@ this is probably wrong (?) */
731: for (i = 0 ; i < 12 ; i++) {
732: m68k_areg(regs, 7) -= 2;
733: put_word (m68k_areg(regs, 7), 0);
734: }
735: m68k_areg(regs, 7) -= 2;
736: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
737: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
738: m68k_areg(regs, 7) -= 4;
739: put_long (m68k_areg(regs, 7), oldpc);
740: m68k_areg(regs, 7) -= 2;
741: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
742: } else if (regs.m && nr >= 24 && nr < 32) {
743: m68k_areg(regs, 7) -= 2;
744: put_word (m68k_areg(regs, 7), nr * 4);
745: m68k_areg(regs, 7) -= 4;
746: put_long (m68k_areg(regs, 7), currpc);
747: m68k_areg(regs, 7) -= 2;
748: put_word (m68k_areg(regs, 7), regs.sr);
749: regs.sr |= (1 << 13);
750: regs.msp = m68k_areg(regs, 7);
751: m68k_areg(regs, 7) = regs.isp;
752: m68k_areg(regs, 7) -= 2;
753: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
754: } else {
755: m68k_areg(regs, 7) -= 2;
756: put_word (m68k_areg(regs, 7), nr * 4);
757: }
758: }
1.1.1.3 root 759:
760: /* Push PC on stack: */
1.1 root 761: m68k_areg(regs, 7) -= 4;
762: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 763: /* Push SR on stack: */
1.1 root 764: m68k_areg(regs, 7) -= 2;
765: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 766:
767: /* 68000 bus/address errors: */
768: if (cpu_level==0 && (nr==2 || nr==3)) {
1.1.1.8 ! root 769: uae_u16 specialstatus = 0x2001;
! 770: /* Special status word emulation isn't perfect yet... :-( */
! 771: if (regs.sr & 0x2000)
! 772: specialstatus |= 0x4;
1.1.1.3 root 773: m68k_areg(regs, 7) -= 8;
774: if (nr == 3) { /* Address error */
1.1.1.8 ! root 775: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 776: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
777: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
778: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.8 ! root 779: if (bEnableDebug) {
! 780: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
! 781: DebugUI();
! 782: }
1.1.1.3 root 783: }
1.1.1.8 ! root 784: else { /* Bus error */
! 785: if (bBusErrorReadWrite)
! 786: specialstatus |= 0x10;
! 787: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 788: put_long (m68k_areg(regs, 7)+2, BusAddressLocation);
1.1.1.8 ! root 789: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
! 790: /* Check for double bus errors: */
! 791: if (regs.spcflags & SPCFLAG_BUSERROR) {
! 792: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
! 793: BusAddressLocation, (long)currpc);
! 794: unset_special(SPCFLAG_BUSERROR);
! 795: if (bEnableDebug)
! 796: DebugUI();
! 797: regs.intmask = 7;
! 798: m68k_setstopped(TRUE);
! 799: return;
! 800: }
! 801: if (bEnableDebug && BusAddressLocation!=0xff8a00) {
! 802: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n",BusAddressLocation,(long)currpc);
! 803: DebugUI();
! 804: }
! 805: }
1.1.1.3 root 806: }
807:
1.1.1.8 ! root 808: /* Set PC and flags */
! 809: if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) {
! 810: write_log("Uninitialized exception handler #%i!\n", nr);
! 811: }
1.1 root 812: m68k_setpc (get_long (regs.vbr + 4*nr));
813: fill_prefetch_0 ();
814: regs.t1 = regs.t0 = regs.m = 0;
815: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
1.1.1.6 root 816:
1.1.1.7 root 817: /* Handle exception cycles: */
818: if(nr >= 24 && nr <= 31)
819: {
1.1.1.8 ! root 820: M68000_AddCycles(44+4); /* Interrupt */
1.1.1.7 root 821: }
822: else if(nr >= 32 && nr <= 47)
823: {
1.1.1.8 ! root 824: M68000_AddCycles(34); /* Trap */
1.1.1.7 root 825: }
826: else switch(nr)
827: {
1.1.1.8 ! root 828: case 2: M68000_AddCycles(50); break; /* Bus error */
! 829: case 3: M68000_AddCycles(50); break; /* Address error */
! 830: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
! 831: case 5: M68000_AddCycles(38); break; /* Div by zero */
! 832: case 6: M68000_AddCycles(40); break; /* CHK */
! 833: case 7: M68000_AddCycles(34); break; /* TRAPV */
! 834: case 8: M68000_AddCycles(34); break; /* Privilege violation */
! 835: case 9: M68000_AddCycles(34); break; /* Trace */
! 836: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
! 837: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 838: default:
1.1.1.8 ! root 839: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 840: if(nr < 64)
1.1.1.8 ! root 841: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 842: else
1.1.1.8 ! root 843: M68000_AddCycles(24); /* Must be a MFP interrupt */
1.1.1.7 root 844: break;
1.1.1.6 root 845: }
1.1 root 846: }
847:
1.1.1.7 root 848:
1.1 root 849: static void Interrupt(int nr)
850: {
851: assert(nr < 8 && nr >= 0);
852: lastint_regs = regs;
853: lastint_no = nr;
854: Exception(nr+24, 0);
855:
856: regs.intmask = nr;
857: set_special (SPCFLAG_INT);
858: }
859:
1.1.1.7 root 860:
1.1.1.8 ! root 861: uae_u32 reg_caar, reg_cacr;
! 862: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 863:
1.1.1.7 root 864:
1.1 root 865: int m68k_move2c (int regno, uae_u32 *regp)
866: {
867: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
868: || (cpu_level < 4 && (regno & 0x7FF) > 2)
869: || (cpu_level == 4 && regno == 0x802))
870: {
871: op_illg (0x4E7B);
872: return 0;
873: } else {
874: switch (regno) {
875: case 0: regs.sfc = *regp & 7; break;
876: case 1: regs.dfc = *regp & 7; break;
1.1.1.8 ! root 877: case 2: reg_cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 878: case 3: tc = *regp & 0xc000; break;
879: /* Mask out fields that should be zero. */
880: case 4: itt0 = *regp & 0xffffe364; break;
881: case 5: itt1 = *regp & 0xffffe364; break;
882: case 6: dtt0 = *regp & 0xffffe364; break;
883: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 884:
1.1 root 885: case 0x800: regs.usp = *regp; break;
886: case 0x801: regs.vbr = *regp; break;
1.1.1.8 ! root 887: case 0x802: reg_caar = *regp & 0xfc; break;
1.1 root 888: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
889: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 890: case 0x805: mmusr = *regp; break;
891: case 0x806: urp = *regp; break;
892: case 0x807: srp = *regp; break;
1.1 root 893: default:
894: op_illg (0x4E7B);
895: return 0;
896: }
897: }
898: return 1;
899: }
900:
901: int m68k_movec2 (int regno, uae_u32 *regp)
902: {
903: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
904: || (cpu_level < 4 && (regno & 0x7FF) > 2)
905: || (cpu_level == 4 && regno == 0x802))
906: {
907: op_illg (0x4E7A);
908: return 0;
909: } else {
910: switch (regno) {
911: case 0: *regp = regs.sfc; break;
912: case 1: *regp = regs.dfc; break;
1.1.1.8 ! root 913: case 2: *regp = reg_cacr; break;
1.1 root 914: case 3: *regp = tc; break;
915: case 4: *regp = itt0; break;
916: case 5: *regp = itt1; break;
917: case 6: *regp = dtt0; break;
918: case 7: *regp = dtt1; break;
919: case 0x800: *regp = regs.usp; break;
920: case 0x801: *regp = regs.vbr; break;
1.1.1.8 ! root 921: case 0x802: *regp = reg_caar; break;
1.1 root 922: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
923: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
924: case 0x805: *regp = mmusr; break;
1.1.1.6 root 925: case 0x806: *regp = urp; break;
926: case 0x807: *regp = srp; break;
1.1 root 927: default:
928: op_illg (0x4E7A);
929: return 0;
930: }
931: }
932: return 1;
933: }
934:
935: STATIC_INLINE int
936: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
937: {
938: uae_u32 q = 0, cbit = 0;
939: int i;
940:
941: if (div <= src_hi) {
942: return 1;
943: }
944: for (i = 0 ; i < 32 ; i++) {
945: cbit = src_hi & 0x80000000ul;
946: src_hi <<= 1;
947: if (src_lo & 0x80000000ul) src_hi++;
948: src_lo <<= 1;
949: q = q << 1;
950: if (cbit || div <= src_hi) {
951: q |= 1;
952: src_hi -= div;
953: }
954: }
955: *quot = q;
956: *rem = src_hi;
957: return 0;
958: }
959:
960: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
961: {
962: #if defined(uae_s64)
963: if (src == 0) {
964: Exception (5, oldpc);
965: return;
966: }
967: if (extra & 0x800) {
968: /* signed variant */
969: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
970: uae_s64 quot, rem;
971:
972: if (extra & 0x400) {
973: a &= 0xffffffffu;
974: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
975: }
976: rem = a % (uae_s64)(uae_s32)src;
977: quot = a / (uae_s64)(uae_s32)src;
978: if ((quot & UVAL64(0xffffffff80000000)) != 0
979: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
980: {
981: SET_VFLG (1);
982: SET_NFLG (1);
983: SET_CFLG (0);
984: } else {
985: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
986: SET_VFLG (0);
987: SET_CFLG (0);
988: SET_ZFLG (((uae_s32)quot) == 0);
989: SET_NFLG (((uae_s32)quot) < 0);
990: m68k_dreg(regs, extra & 7) = rem;
991: m68k_dreg(regs, (extra >> 12) & 7) = quot;
992: }
993: } else {
994: /* unsigned */
995: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
996: uae_u64 quot, rem;
997:
998: if (extra & 0x400) {
999: a &= 0xffffffffu;
1000: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1001: }
1002: rem = a % (uae_u64)src;
1003: quot = a / (uae_u64)src;
1004: if (quot > 0xffffffffu) {
1005: SET_VFLG (1);
1006: SET_NFLG (1);
1007: SET_CFLG (0);
1008: } else {
1009: SET_VFLG (0);
1010: SET_CFLG (0);
1011: SET_ZFLG (((uae_s32)quot) == 0);
1012: SET_NFLG (((uae_s32)quot) < 0);
1013: m68k_dreg(regs, extra & 7) = rem;
1014: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1015: }
1016: }
1017: #else
1018: if (src == 0) {
1019: Exception (5, oldpc);
1020: return;
1021: }
1022: if (extra & 0x800) {
1023: /* signed variant */
1024: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1025: uae_s32 hi = lo < 0 ? -1 : 0;
1026: uae_s32 save_high;
1027: uae_u32 quot, rem;
1028: uae_u32 sign;
1029:
1030: if (extra & 0x400) {
1031: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1032: }
1033: save_high = hi;
1034: sign = (hi ^ src);
1035: if (hi < 0) {
1036: hi = ~hi;
1037: lo = -lo;
1038: if (lo == 0) hi++;
1039: }
1040: if ((uae_s32)src < 0) src = -src;
1041: if (div_unsigned(hi, lo, src, ", &rem) ||
1042: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1043: SET_VFLG (1);
1044: SET_NFLG (1);
1045: SET_CFLG (0);
1046: } else {
1047: if (sign & 0x80000000) quot = -quot;
1048: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1049: SET_VFLG (0);
1050: SET_CFLG (0);
1051: SET_ZFLG (((uae_s32)quot) == 0);
1052: SET_NFLG (((uae_s32)quot) < 0);
1053: m68k_dreg(regs, extra & 7) = rem;
1054: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1055: }
1056: } else {
1057: /* unsigned */
1058: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1059: uae_u32 hi = 0;
1060: uae_u32 quot, rem;
1061:
1062: if (extra & 0x400) {
1063: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1064: }
1065: if (div_unsigned(hi, lo, src, ", &rem)) {
1066: SET_VFLG (1);
1067: SET_NFLG (1);
1068: SET_CFLG (0);
1069: } else {
1070: SET_VFLG (0);
1071: SET_CFLG (0);
1072: SET_ZFLG (((uae_s32)quot) == 0);
1073: SET_NFLG (((uae_s32)quot) < 0);
1074: m68k_dreg(regs, extra & 7) = rem;
1075: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1076: }
1077: }
1078: #endif
1079: }
1080:
1081: STATIC_INLINE void
1082: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1083: {
1084: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1085: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1086: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1087: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1088: uae_u32 lo;
1089:
1090: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1091: if (lo < r0) r3++;
1092: r0 = lo;
1093: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1094: if (lo < r0) r3++;
1095: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1096: *dst_lo = lo;
1097: *dst_hi = r3;
1098: }
1099:
1100: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1101: {
1102: #if defined(uae_s64)
1103: if (extra & 0x800) {
1104: /* signed variant */
1105: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1106:
1107: a *= (uae_s64)(uae_s32)src;
1108: SET_VFLG (0);
1109: SET_CFLG (0);
1110: SET_ZFLG (a == 0);
1111: SET_NFLG (a < 0);
1112: if (extra & 0x400)
1113: m68k_dreg(regs, extra & 7) = a >> 32;
1114: else if ((a & UVAL64(0xffffffff80000000)) != 0
1115: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1116: {
1117: SET_VFLG (1);
1118: }
1119: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1120: } else {
1121: /* unsigned */
1122: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1123:
1124: a *= (uae_u64)src;
1125: SET_VFLG (0);
1126: SET_CFLG (0);
1127: SET_ZFLG (a == 0);
1128: SET_NFLG (((uae_s64)a) < 0);
1129: if (extra & 0x400)
1130: m68k_dreg(regs, extra & 7) = a >> 32;
1131: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1132: SET_VFLG (1);
1133: }
1134: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1135: }
1136: #else
1137: if (extra & 0x800) {
1138: /* signed variant */
1139: uae_s32 src1,src2;
1140: uae_u32 dst_lo,dst_hi;
1141: uae_u32 sign;
1142:
1143: src1 = (uae_s32)src;
1144: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1145: sign = (src1 ^ src2);
1146: if (src1 < 0) src1 = -src1;
1147: if (src2 < 0) src2 = -src2;
1148: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1149: if (sign & 0x80000000) {
1150: dst_hi = ~dst_hi;
1151: dst_lo = -dst_lo;
1152: if (dst_lo == 0) dst_hi++;
1153: }
1154: SET_VFLG (0);
1155: SET_CFLG (0);
1156: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1157: SET_NFLG (((uae_s32)dst_hi) < 0);
1158: if (extra & 0x400)
1159: m68k_dreg(regs, extra & 7) = dst_hi;
1160: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1161: && ((dst_hi & 0xffffffff) != 0xffffffff
1162: || (dst_lo & 0x80000000) != 0x80000000))
1163: {
1164: SET_VFLG (1);
1165: }
1166: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1167: } else {
1168: /* unsigned */
1169: uae_u32 dst_lo,dst_hi;
1170:
1171: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1172:
1173: SET_VFLG (0);
1174: SET_CFLG (0);
1175: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1176: SET_NFLG (((uae_s32)dst_hi) < 0);
1177: if (extra & 0x400)
1178: m68k_dreg(regs, extra & 7) = dst_hi;
1179: else if (dst_hi != 0) {
1180: SET_VFLG (1);
1181: }
1182: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1183: }
1184: #endif
1185: }
1.1.1.6 root 1186:
1.1 root 1187:
1188: void m68k_reset (void)
1189: {
1190: regs.s = 1;
1191: regs.m = 0;
1192: regs.stopped = 0;
1193: regs.t1 = 0;
1194: regs.t0 = 0;
1195: SET_ZFLG (0);
1196: SET_XFLG (0);
1197: SET_CFLG (0);
1198: SET_VFLG (0);
1199: SET_NFLG (0);
1.1.1.7 root 1200: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1201: regs.intmask = 7;
1202: regs.vbr = regs.sfc = regs.dfc = 0;
1203: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1204:
1205: m68k_areg(regs, 7) = get_long(0);
1206: m68k_setpc(get_long(4));
1207: refill_prefetch (m68k_getpc(), 0);
1.1 root 1208: }
1209:
1.1.1.8 ! root 1210:
1.1 root 1211: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1212: {
1.1.1.8 ! root 1213: #if 0
1.1 root 1214: uaecptr pc = m68k_getpc ();
1.1.1.8 ! root 1215: #endif
1.1.1.6 root 1216: if ((opcode & 0xF000) == 0xF000) {
1.1 root 1217: Exception(0xB,0);
1218: return 4;
1.1.1.6 root 1219: }
1220: if ((opcode & 0xF000) == 0xA000) {
1.1 root 1221: Exception(0xA,0);
1222: return 4;
1.1.1.6 root 1223: }
1.1.1.3 root 1224: #if 0
1.1.1.6 root 1225: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1226: #endif
1227: Exception (4,0);
1228: return 4;
1229: }
1230:
1.1.1.8 ! root 1231:
1.1 root 1232: void mmu_op(uae_u32 opcode, uae_u16 extra)
1233: {
1234: if ((opcode & 0xFE0) == 0x0500) {
1235: /* PFLUSH */
1236: mmusr = 0;
1237: write_log ("PFLUSH\n");
1238: } else if ((opcode & 0x0FD8) == 0x548) {
1239: /* PTEST */
1240: write_log ("PTEST\n");
1241: } else
1242: op_illg (opcode);
1243: }
1244:
1245:
1246: static uaecptr last_trace_ad = 0;
1247:
1248: static void do_trace (void)
1249: {
1250: if (regs.t0 && cpu_level >= 2) {
1251: uae_u16 opcode;
1252: /* should also include TRAP, CHK, SR modification FPcc */
1253: /* probably never used so why bother */
1254: /* We can afford this to be inefficient... */
1255: m68k_setpc (m68k_getpc ());
1256: fill_prefetch_0 ();
1257: opcode = get_word (regs.pc);
1258: if (opcode == 0x4e72 /* RTE */
1259: || opcode == 0x4e74 /* RTD */
1260: || opcode == 0x4e75 /* RTS */
1261: || opcode == 0x4e77 /* RTR */
1262: || opcode == 0x4e76 /* TRAPV */
1263: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1264: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1265: || (opcode & 0xff00) == 0x6100 /* BSR */
1266: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1267: && cctrue((opcode >> 8) & 0xf))
1268: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1269: && !cctrue((opcode >> 8) & 0xf)
1270: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1271: {
1272: last_trace_ad = m68k_getpc ();
1273: unset_special (SPCFLAG_TRACE);
1274: set_special (SPCFLAG_DOTRACE);
1275: }
1276: } else if (regs.t1) {
1277: last_trace_ad = m68k_getpc ();
1278: unset_special (SPCFLAG_TRACE);
1279: set_special (SPCFLAG_DOTRACE);
1280: }
1281: }
1282:
1283:
1.1.1.8 ! root 1284: /*
! 1285: * Handle special flags
! 1286: */
1.1 root 1287: static int do_specialties (void)
1288: {
1.1.1.7 root 1289: if(regs.spcflags & SPCFLAG_BUSERROR) {
1290: /* We can not execute bus errors directly in the memory handler
1291: * functions since the PC should point to the address of the next
1292: * instruction, so we're executing the bus errors here: */
1.1.1.8 ! root 1293: unset_special(SPCFLAG_BUSERROR);
1.1.1.7 root 1294: Exception(2,0);
1295: }
1296:
1.1.1.8 ! root 1297: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
! 1298: /* Add some extra cycles to simulate a wait state */
! 1299: unset_special(SPCFLAG_EXTRA_CYCLES);
! 1300: M68000_AddCycles(4);
! 1301: }
! 1302:
1.1 root 1303: if (regs.spcflags & SPCFLAG_DOTRACE) {
1304: Exception (9,last_trace_ad);
1305: }
1.1.1.8 ! root 1306:
1.1 root 1307: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.8 ! root 1308: if (regs.intmask > 5) {
! 1309: /* We still have to care about events when IPL==7 ! */
! 1310: Main_EventHandler();
! 1311: if (regs.spcflags & SPCFLAG_BRK) return 1;
! 1312: }
! 1313: M68000_AddCycles(4);
! 1314: if (PendingInterruptCount<=0 && PendingInterruptFunction) {
! 1315: CALL_VAR(PendingInterruptFunction);
! 1316: }
! 1317: if (regs.spcflags & SPCFLAG_MFP) {
! 1318: MFP_CheckPendingInterrupts();
! 1319: }
1.1.1.5 root 1320: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1321: int intr = intlev ();
1.1 root 1322: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1323: if (intr != -1 && intr > regs.intmask) {
1.1 root 1324: Interrupt (intr);
1325: regs.stopped = 0;
1326: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1327: }
1.1 root 1328: }
1329: }
1.1.1.8 ! root 1330:
1.1 root 1331: if (regs.spcflags & SPCFLAG_TRACE)
1332: do_trace ();
1333:
1334: if (regs.spcflags & SPCFLAG_DOINT) {
1.1.1.6 root 1335: int intr = intlev ();
1.1.1.8 ! root 1336: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1 root 1337: unset_special (SPCFLAG_DOINT);
1.1.1.6 root 1338: if (intr != -1 && intr > regs.intmask) {
1.1 root 1339: Interrupt (intr);
1340: regs.stopped = 0;
1.1.1.6 root 1341: }
1.1 root 1342: }
1343: if (regs.spcflags & SPCFLAG_INT) {
1344: unset_special (SPCFLAG_INT);
1345: set_special (SPCFLAG_DOINT);
1346: }
1.1.1.8 ! root 1347:
! 1348: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
! 1349: MFP_CheckPendingInterrupts();
! 1350: }
! 1351:
1.1 root 1352: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 ! root 1353: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1354: return 1;
1355: }
1.1.1.8 ! root 1356:
1.1 root 1357: return 0;
1358: }
1359:
1.1.1.3 root 1360:
1.1 root 1361: /* It's really sad to have two almost identical functions for this, but we
1362: do it all for performance... :( */
1363: static void m68k_run_1 (void)
1364: {
1365: #ifdef DEBUG_PREFETCH
1366: uae_u8 saved_bytes[20];
1367: uae_u16 *oldpcp;
1368: #endif
1.1.1.8 ! root 1369:
! 1370: for (;;) {
1.1 root 1371: int cycles;
1372: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 ! root 1373:
1.1 root 1374: #ifdef DEBUG_PREFETCH
1375: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1376: fprintf (stderr, "Prefetch differs from memory.\n");
1377: debugging = 1;
1378: return;
1379: }
1380: oldpcp = regs.pc_p;
1381: memcpy (saved_bytes, regs.pc_p, 20);
1382: #endif
1383:
1384: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1385: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1386:
1387: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1388: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1389: #if COUNT_INSTRS == 2
1390: if (table68k[opcode].handler != -1)
1391: instrcount[table68k[opcode].handler]++;
1392: #elif COUNT_INSTRS == 1
1393: instrcount[opcode]++;
1394: #endif
1.1.1.2 root 1395:
1.1.1.6 root 1396: cycles = (*cpufunctbl[opcode])(opcode);
1397:
1.1 root 1398: #ifdef DEBUG_PREFETCH
1399: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1400: fprintf (stderr, "Self-modifying code detected.\n");
1401: set_special (SPCFLAG_BRK);
1402: debugging = 1;
1403: }
1404: #endif
1.1.1.2 root 1405:
1.1.1.8 ! root 1406: M68000_AddCycles(cycles);
! 1407: if (PendingInterruptCount<=0 && PendingInterruptFunction)
! 1408: CALL_VAR(PendingInterruptFunction);
! 1409:
1.1 root 1410: if (regs.spcflags) {
1411: if (do_specialties ())
1412: return;
1413: }
1414: }
1415: }
1416:
1417:
1418: /* Same thing, but don't use prefetch to get opcode. */
1419: static void m68k_run_2 (void)
1420: {
1.1.1.8 ! root 1421: for (;;) {
1.1 root 1422: int cycles;
1423: uae_u32 opcode = get_iword (0);
1424:
1425: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1426: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1427:
1428: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1429: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1430: #if COUNT_INSTRS == 2
1431: if (table68k[opcode].handler != -1)
1432: instrcount[table68k[opcode].handler]++;
1433: #elif COUNT_INSTRS == 1
1434: instrcount[opcode]++;
1435: #endif
1.1.1.2 root 1436:
1.1.1.6 root 1437: cycles = (*cpufunctbl[opcode])(opcode);
1438:
1.1.1.8 ! root 1439: M68000_AddCycles(cycles);
! 1440: if (PendingInterruptCount<=0 && PendingInterruptFunction)
! 1441: CALL_VAR(PendingInterruptFunction);
! 1442:
1.1 root 1443: if (regs.spcflags) {
1444: if (do_specialties ())
1445: return;
1446: }
1447: }
1448: }
1449:
1450:
1451: void m68k_go (int may_quit)
1452: {
1.1.1.8 ! root 1453: static int in_m68k_go = 0;
! 1454:
1.1 root 1455: if (in_m68k_go || !may_quit) {
1456: write_log ("Bug! m68k_go is not reentrant.\n");
1457: abort ();
1458: }
1459:
1460: in_m68k_go++;
1.1.1.8 ! root 1461: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.2 root 1462: if(cpu_compatible)
1463: m68k_run_1();
1464: else
1465: m68k_run_2();
1.1 root 1466: }
1.1.1.8 ! root 1467: unset_special(SPCFLAG_BRK);
1.1 root 1468: in_m68k_go--;
1469: }
1470:
1.1.1.8 ! root 1471:
! 1472: /*
1.1 root 1473: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1474: {
1475: uae_u32 opcode, val;
1476: struct instr *dp;
1477:
1478: opcode = get_iword_1(0);
1479: last_op_for_exception_3 = opcode;
1480: m68kpc_offset = 2;
1481:
1.1.1.6 root 1482: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1483: opcode = 0x4AFC;
1484: }
1485: dp = table68k + opcode;
1486:
1487: if (dp->suse) {
1488: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1489: Exception (3, 0);
1490: return;
1491: }
1492: }
1493: if (dp->duse) {
1494: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1495: Exception (3, 0);
1496: return;
1497: }
1498: }
1499: }
1.1.1.8 ! root 1500: */
! 1501:
1.1 root 1502:
1503: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1504: {
1.1.1.8 ! root 1505: static const char* ccnames[] =
! 1506: { "T ","F ","HI","LS","CC","CS","NE","EQ",
! 1507: "VC","VS","PL","MI","GE","LT","GT","LE" };
! 1508:
1.1 root 1509: uaecptr newpc = 0;
1510: m68kpc_offset = addr - m68k_getpc ();
1511: while (cnt-- > 0) {
1512: char instrname[20],*ccpt;
1513: int opwords;
1514: uae_u32 opcode;
1515: struct mnemolookup *lookup;
1516: struct instr *dp;
1517: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1518: for (opwords = 0; opwords < 5; opwords++){
1519: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1520: }
1521: opcode = get_iword_1 (m68kpc_offset);
1522: m68kpc_offset += 2;
1.1.1.6 root 1523: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1524: opcode = 0x4AFC;
1525: }
1526: dp = table68k + opcode;
1527: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1528: ;
1529:
1530: strcpy (instrname, lookup->name);
1531: ccpt = strstr (instrname, "cc");
1532: if (ccpt != 0) {
1533: strncpy (ccpt, ccnames[dp->cc], 2);
1534: }
1535: fprintf (f, "%s", instrname);
1536: switch (dp->size){
1537: case sz_byte: fprintf (f, ".B "); break;
1538: case sz_word: fprintf (f, ".W "); break;
1539: case sz_long: fprintf (f, ".L "); break;
1540: default: fprintf (f, " "); break;
1541: }
1542:
1543: if (dp->suse) {
1544: newpc = m68k_getpc () + m68kpc_offset;
1545: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1546: }
1547: if (dp->suse && dp->duse)
1548: fprintf (f, ",");
1549: if (dp->duse) {
1550: newpc = m68k_getpc () + m68kpc_offset;
1551: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1552: }
1553: if (ccpt != 0) {
1554: if (cctrue(dp->cc))
1.1.1.5 root 1555: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1556: else
1.1.1.5 root 1557: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1558: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1559: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1560: fprintf (f, "\n");
1561: }
1562: if (nextpc)
1563: *nextpc = m68k_getpc () + m68kpc_offset;
1564: }
1565:
1566: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1567: {
1568: int i;
1569: for (i = 0; i < 8; i++){
1.1.1.5 root 1570: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1571: if ((i & 3) == 3) fprintf (f, "\n");
1572: }
1573: for (i = 0; i < 8; i++){
1.1.1.5 root 1574: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1575: if ((i & 3) == 3) fprintf (f, "\n");
1576: }
1577: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1578: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1579: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1580: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1581: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1582: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1583: regs.t1, regs.t0, regs.s, regs.m,
1584: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1585: for (i = 0; i < 8; i++){
1586: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1587: if ((i & 3) == 3) fprintf (f, "\n");
1588: }
1589: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1590: (regs.fpsr & 0x8000000) != 0,
1591: (regs.fpsr & 0x4000000) != 0,
1592: (regs.fpsr & 0x2000000) != 0,
1593: (regs.fpsr & 0x1000000) != 0);
1594: if (cpu_compatible)
1595: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1596:
1597: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1598: if (nextpc)
1.1.1.5 root 1599: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1600: }
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