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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.9 ! root 13: char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.36 2004/12/08 10:27:53 thothy Exp $";
1.1 root 14:
15: #include "sysdeps.h"
16: #include "hatari-glue.h"
17: #include "maccess.h"
18: #include "memory.h"
19: #include "newcpu.h"
1.1.1.5 root 20: #include "../includes/main.h"
1.1.1.7 root 21: #include "../includes/m68000.h"
1.1.1.8 root 22: #include "../includes/mfp.h"
1.1 root 23: #include "../includes/tos.h"
1.1.1.5 root 24: #include "../includes/vdi.h"
25: #include "../includes/cart.h"
26: #include "../includes/debugui.h"
1.1.1.8 root 27: #include "../includes/bios.h"
28: #include "../includes/xbios.h"
1.1 root 29:
30:
31: struct flag_struct regflags;
32:
33: /* Opcode of faulting instruction */
34: uae_u16 last_op_for_exception_3;
35: /* PC at fault time */
36: uaecptr last_addr_for_exception_3;
37: /* Address that generated the exception */
38: uaecptr last_fault_for_exception_3;
39:
40: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
41: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
42:
43: int movem_index1[256];
44: int movem_index2[256];
45: int movem_next[256];
46:
47: int fpp_movem_index1[256];
48: int fpp_movem_index2[256];
49: int fpp_movem_next[256];
50:
51: cpuop_func *cpufunctbl[65536];
52:
1.1.1.6 root 53:
1.1 root 54: #define COUNT_INSTRS 0
55:
56: #if COUNT_INSTRS
57: static unsigned long int instrcount[65536];
58: static uae_u16 opcodenums[65536];
59:
60: static int compfn (const void *el1, const void *el2)
61: {
62: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
63: }
64:
65: static char *icountfilename (void)
66: {
67: char *name = getenv ("INSNCOUNT");
68: if (name)
69: return name;
70: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
71: }
72:
73: void dump_counts (void)
74: {
75: FILE *f = fopen (icountfilename (), "w");
76: unsigned long int total;
77: int i;
78:
79: write_log ("Writing instruction count file...\n");
80: for (i = 0; i < 65536; i++) {
81: opcodenums[i] = i;
82: total += instrcount[i];
83: }
84: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
85:
86: fprintf (f, "Total: %lu\n", total);
87: for (i=0; i < 65536; i++) {
88: unsigned long int cnt = instrcount[opcodenums[i]];
89: struct instr *dp;
90: struct mnemolookup *lookup;
91: if (!cnt)
92: break;
93: dp = table68k + opcodenums[i];
94: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
95: ;
96: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
97: }
98: fclose (f);
99: }
100: #else
101: void dump_counts (void)
102: {
103: }
104: #endif
105:
106:
107: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
108:
109: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
110: {
1.1.1.6 root 111: op_illg (opcode);
1.1 root 112: return 4;
113: }
114:
1.1.1.4 root 115:
116: void build_cpufunctbl(void)
1.1 root 117: {
118: int i;
119: unsigned long opcode;
120: struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff
121: : cpu_level == 3 ? op_smalltbl_1_ff
122: : cpu_level == 2 ? op_smalltbl_2_ff
123: : cpu_level == 1 ? op_smalltbl_3_ff
124: : ! cpu_compatible ? op_smalltbl_4_ff
125: : op_smalltbl_5_ff);
126:
127: write_log ("Building CPU function table (%d %d %d).\n",
128: cpu_level, cpu_compatible, address_space_24);
129:
130: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 131: cpufunctbl[opcode] = op_illg_1;
1.1 root 132: for (i = 0; tbl[i].handler != NULL; i++) {
133: if (! tbl[i].specific)
1.1.1.6 root 134: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 135: }
136: for (opcode = 0; opcode < 65536; opcode++) {
137: cpuop_func *f;
138:
139: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
140: continue;
141:
142: if (table68k[opcode].handler != -1) {
1.1.1.6 root 143: f = cpufunctbl[table68k[opcode].handler];
1.1 root 144: if (f == op_illg_1)
145: abort();
1.1.1.6 root 146: cpufunctbl[opcode] = f;
1.1 root 147: }
148: }
149: for (i = 0; tbl[i].handler != NULL; i++) {
150: if (tbl[i].specific)
1.1.1.6 root 151: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 152: }
153:
1.1.1.6 root 154: /* Hatari's illegal opcodes: */
155: cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos;
1.1.1.7 root 156: cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit;
1.1.1.6 root 157: cpufunctbl[VDI_OPCODE] = OpCode_VDI;
1.1 root 158: }
159:
160:
161:
162: void init_m68k (void)
163: {
164: int i;
165:
166: for (i = 0 ; i < 256 ; i++) {
167: int j;
168: for (j = 0 ; j < 8 ; j++) {
169: if (i & (1 << j)) break;
170: }
171: movem_index1[i] = j;
172: movem_index2[i] = 7-j;
173: movem_next[i] = i & (~(1 << j));
174: }
175: for (i = 0 ; i < 256 ; i++) {
176: int j;
177: for (j = 7 ; j >= 0 ; j--) {
178: if (i & (1 << j)) break;
179: }
180: fpp_movem_index1[i] = 7-j;
181: fpp_movem_index2[i] = j;
182: fpp_movem_next[i] = i & (~(1 << j));
183: }
184: #if COUNT_INSTRS
185: {
186: FILE *f = fopen (icountfilename (), "r");
187: memset (instrcount, 0, sizeof instrcount);
188: if (f) {
189: uae_u32 opcode, count, total;
190: char name[20];
191: write_log ("Reading instruction count file...\n");
192: fscanf (f, "Total: %lu\n", &total);
193: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
194: instrcount[opcode] = count;
195: }
196: fclose(f);
197: }
198: }
199: #endif
200: write_log ("Building CPU table for configuration: 68");
201: if (address_space_24 && cpu_level > 1)
202: write_log ("EC");
203: switch (cpu_level) {
204: case 1:
205: write_log ("010");
206: break;
207: case 2:
208: write_log ("020");
209: break;
210: case 3:
211: write_log ("020/881");
212: break;
213: case 4:
214: /* Who is going to miss the MMU anyway...? :-) */
215: write_log ("040");
216: break;
217: default:
218: write_log ("000");
219: break;
220: }
221: if (cpu_compatible)
222: write_log (" (compatible mode)");
223: write_log ("\n");
1.1.1.7 root 224:
1.1 root 225: read_table68k ();
226: do_merges ();
227:
228: write_log ("%d CPU functions\n", nr_cpuop_funcs);
229:
230: build_cpufunctbl ();
231: }
232:
1.1.1.4 root 233:
1.1 root 234: struct regstruct regs, lastint_regs;
1.1.1.8 root 235: /* not used ATM:
1.1 root 236: static struct regstruct regs_backup[16];
237: static int backup_pointer = 0;
1.1.1.8 root 238: */
1.1 root 239: static long int m68kpc_offset;
240: int lastint_no;
241:
242: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
243: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
244: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
245:
246: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
247: {
248: uae_u16 dp;
249: uae_s8 disp8;
250: uae_s16 disp16;
251: int r;
252: uae_u32 dispreg;
253: uaecptr addr;
254: uae_s32 offset = 0;
255: char buffer[80];
256:
257: switch (mode){
258: case Dreg:
259: sprintf (buffer,"D%d", reg);
260: break;
261: case Areg:
262: sprintf (buffer,"A%d", reg);
263: break;
264: case Aind:
265: sprintf (buffer,"(A%d)", reg);
266: break;
267: case Aipi:
268: sprintf (buffer,"(A%d)+", reg);
269: break;
270: case Apdi:
271: sprintf (buffer,"-(A%d)", reg);
272: break;
273: case Ad16:
274: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
275: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
276: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
277: (unsigned long)addr);
278: break;
279: case Ad8r:
280: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
281: disp8 = dp & 0xFF;
282: r = (dp & 0x7000) >> 12;
283: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
284: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
285: dispreg <<= (dp >> 9) & 3;
286:
287: if (dp & 0x100) {
288: uae_s32 outer = 0, disp = 0;
289: uae_s32 base = m68k_areg(regs,reg);
290: char name[10];
291: sprintf (name,"A%d, ",reg);
292: if (dp & 0x80) { base = 0; name[0] = 0; }
293: if (dp & 0x40) dispreg = 0;
294: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
295: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
296: base += disp;
297:
298: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
299: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
300:
301: if (!(dp & 4)) base += dispreg;
302: if (dp & 3) base = get_long (base);
303: if (dp & 4) base += dispreg;
304:
305: addr = base + outer;
306: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
307: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
308: 1 << ((dp >> 9) & 3),
1.1.1.5 root 309: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 310: } else {
311: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
312: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
313: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
314: 1 << ((dp >> 9) & 3), disp8,
315: (unsigned long)addr);
316: }
317: break;
318: case PC16:
319: addr = m68k_getpc () + m68kpc_offset;
320: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
321: addr += (uae_s16)disp16;
322: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
323: break;
324: case PC8r:
325: addr = m68k_getpc () + m68kpc_offset;
326: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
327: disp8 = dp & 0xFF;
328: r = (dp & 0x7000) >> 12;
329: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
330: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
331: dispreg <<= (dp >> 9) & 3;
332:
333: if (dp & 0x100) {
334: uae_s32 outer = 0,disp = 0;
335: uae_s32 base = addr;
336: char name[10];
337: sprintf (name,"PC, ");
338: if (dp & 0x80) { base = 0; name[0] = 0; }
339: if (dp & 0x40) dispreg = 0;
340: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
341: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
342: base += disp;
343:
344: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
345: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
346:
347: if (!(dp & 4)) base += dispreg;
348: if (dp & 3) base = get_long (base);
349: if (dp & 4) base += dispreg;
350:
351: addr = base + outer;
352: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
353: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
354: 1 << ((dp >> 9) & 3),
1.1.1.5 root 355: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 356: } else {
357: addr += (uae_s32)((uae_s8)disp8) + dispreg;
358: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
359: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
360: disp8, (unsigned long)addr);
361: }
362: break;
363: case absw:
364: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
365: m68kpc_offset += 2;
366: break;
367: case absl:
368: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
369: m68kpc_offset += 4;
370: break;
371: case imm:
372: switch (size){
373: case sz_byte:
374: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
375: m68kpc_offset += 2;
376: break;
377: case sz_word:
378: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
379: m68kpc_offset += 2;
380: break;
381: case sz_long:
382: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
383: m68kpc_offset += 4;
384: break;
385: default:
386: break;
387: }
388: break;
389: case imm0:
390: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
391: m68kpc_offset += 2;
392: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
393: break;
394: case imm1:
395: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
396: m68kpc_offset += 2;
397: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
398: break;
399: case imm2:
400: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
401: m68kpc_offset += 4;
402: sprintf (buffer,"#$%08lx", (unsigned long)offset);
403: break;
404: case immi:
405: offset = (uae_s32)(uae_s8)(reg & 0xff);
406: sprintf (buffer,"#$%08lx", (unsigned long)offset);
407: break;
408: default:
409: break;
410: }
411: if (buf == 0)
412: fprintf (f, "%s", buffer);
413: else
414: strcat (buf, buffer);
415: return offset;
416: }
417:
1.1.1.8 root 418:
1.1 root 419: /* The plan is that this will take over the job of exception 3 handling -
420: * the CPU emulation functions will just do a longjmp to m68k_go whenever
421: * they hit an odd address. */
1.1.1.8 root 422: #if 0
1.1 root 423: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
424: {
425: uae_u16 dp;
426: uae_s8 disp8;
427: uae_s16 disp16;
428: int r;
429: uae_u32 dispreg;
430: uaecptr addr;
1.1.1.5 root 431: /*uae_s32 offset = 0;*/
1.1 root 432:
433: switch (mode){
434: case Dreg:
435: *val = m68k_dreg (regs, reg);
436: return 1;
437: case Areg:
438: *val = m68k_areg (regs, reg);
439: return 1;
440:
441: case Aind:
442: case Aipi:
443: addr = m68k_areg (regs, reg);
444: break;
445: case Apdi:
446: addr = m68k_areg (regs, reg);
447: break;
448: case Ad16:
449: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
450: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
451: break;
452: case Ad8r:
453: addr = m68k_areg (regs, reg);
454: d8r_common:
455: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
456: disp8 = dp & 0xFF;
457: r = (dp & 0x7000) >> 12;
458: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
459: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
460: dispreg <<= (dp >> 9) & 3;
461:
462: if (dp & 0x100) {
463: uae_s32 outer = 0, disp = 0;
464: uae_s32 base = addr;
465: if (dp & 0x80) base = 0;
466: if (dp & 0x40) dispreg = 0;
467: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
468: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
469: base += disp;
470:
471: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
472: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
473:
474: if (!(dp & 4)) base += dispreg;
475: if (dp & 3) base = get_long (base);
476: if (dp & 4) base += dispreg;
477:
478: addr = base + outer;
479: } else {
480: addr += (uae_s32)((uae_s8)disp8) + dispreg;
481: }
482: break;
483: case PC16:
484: addr = m68k_getpc () + m68kpc_offset;
485: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
486: addr += (uae_s16)disp16;
487: break;
488: case PC8r:
489: addr = m68k_getpc () + m68kpc_offset;
490: goto d8r_common;
491: case absw:
492: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
493: m68kpc_offset += 2;
494: break;
495: case absl:
496: addr = get_ilong_1 (m68kpc_offset);
497: m68kpc_offset += 4;
498: break;
499: case imm:
500: switch (size){
501: case sz_byte:
502: *val = get_iword_1 (m68kpc_offset) & 0xff;
503: m68kpc_offset += 2;
504: break;
505: case sz_word:
506: *val = get_iword_1 (m68kpc_offset) & 0xffff;
507: m68kpc_offset += 2;
508: break;
509: case sz_long:
510: *val = get_ilong_1 (m68kpc_offset);
511: m68kpc_offset += 4;
512: break;
513: default:
514: break;
515: }
516: return 1;
517: case imm0:
518: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
519: m68kpc_offset += 2;
520: return 1;
521: case imm1:
522: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
523: m68kpc_offset += 2;
524: return 1;
525: case imm2:
526: *val = get_ilong_1 (m68kpc_offset);
527: m68kpc_offset += 4;
528: return 1;
529: case immi:
530: *val = (uae_s32)(uae_s8)(reg & 0xff);
531: return 1;
532: default:
533: addr = 0;
534: break;
535: }
536: if ((addr & 1) == 0)
537: return 1;
538:
539: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
540: last_fault_for_exception_3 = addr;
541: return 0;
542: }
1.1.1.8 root 543: #endif
544:
1.1 root 545:
546: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
547: {
548: int reg = (dp >> 12) & 15;
549: uae_s32 regd = regs.regs[reg];
550: if ((dp & 0x800) == 0)
551: regd = (uae_s32)(uae_s16)regd;
552: regd <<= (dp >> 9) & 3;
553: if (dp & 0x100) {
554: uae_s32 outer = 0;
555: if (dp & 0x80) base = 0;
556: if (dp & 0x40) regd = 0;
557:
558: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
559: if ((dp & 0x30) == 0x30) base += next_ilong();
560:
561: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
562: if ((dp & 0x3) == 0x3) outer = next_ilong();
563:
564: if ((dp & 0x4) == 0) base += regd;
565: if (dp & 0x3) base = get_long (base);
566: if (dp & 0x4) base += regd;
567:
568: return base + outer;
569: } else {
570: return base + (uae_s32)((uae_s8)dp) + regd;
571: }
572: }
573:
574: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
575: {
576: int reg = (dp >> 12) & 15;
577: uae_s32 regd = regs.regs[reg];
578: #if 1
579: if ((dp & 0x800) == 0)
580: regd = (uae_s32)(uae_s16)regd;
581: return base + (uae_s8)dp + regd;
582: #else
583: /* Branch-free code... benchmark this again now that
584: * things are no longer inline. */
585: uae_s32 regd16;
586: uae_u32 mask;
587: mask = ((dp & 0x800) >> 11) - 1;
588: regd16 = (uae_s32)(uae_s16)regd;
589: regd16 &= mask;
590: mask = ~mask;
591: base += (uae_s8)dp;
592: regd &= mask;
593: regd |= regd16;
594: return base + regd;
595: #endif
596: }
597:
1.1.1.8 root 598:
599: /* Create the Status Register from the flags */
1.1 root 600: void MakeSR (void)
601: {
602: #if 0
603: assert((regs.t1 & 1) == regs.t1);
604: assert((regs.t0 & 1) == regs.t0);
605: assert((regs.s & 1) == regs.s);
606: assert((regs.m & 1) == regs.m);
607: assert((XFLG & 1) == XFLG);
608: assert((NFLG & 1) == NFLG);
609: assert((ZFLG & 1) == ZFLG);
610: assert((VFLG & 1) == VFLG);
611: assert((CFLG & 1) == CFLG);
612: #endif
613: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
614: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
615: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
616: | GET_CFLG);
617: }
618:
1.1.1.8 root 619:
620: /* Set up the flags from Status Register */
1.1 root 621: void MakeFromSR (void)
622: {
623: int oldm = regs.m;
624: int olds = regs.s;
625:
626: regs.t1 = (regs.sr >> 15) & 1;
627: regs.t0 = (regs.sr >> 14) & 1;
628: regs.s = (regs.sr >> 13) & 1;
629: regs.m = (regs.sr >> 12) & 1;
630: regs.intmask = (regs.sr >> 8) & 7;
631: SET_XFLG ((regs.sr >> 4) & 1);
632: SET_NFLG ((regs.sr >> 3) & 1);
633: SET_ZFLG ((regs.sr >> 2) & 1);
634: SET_VFLG ((regs.sr >> 1) & 1);
635: SET_CFLG (regs.sr & 1);
636: if (cpu_level >= 2) {
637: if (olds != regs.s) {
638: if (olds) {
639: if (oldm)
640: regs.msp = m68k_areg(regs, 7);
641: else
642: regs.isp = m68k_areg(regs, 7);
643: m68k_areg(regs, 7) = regs.usp;
644: } else {
645: regs.usp = m68k_areg(regs, 7);
646: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
647: }
648: } else if (olds && oldm != regs.m) {
649: if (oldm) {
650: regs.msp = m68k_areg(regs, 7);
651: m68k_areg(regs, 7) = regs.isp;
652: } else {
653: regs.isp = m68k_areg(regs, 7);
654: m68k_areg(regs, 7) = regs.msp;
655: }
656: }
657: } else {
658: if (olds != regs.s) {
659: if (olds) {
660: regs.isp = m68k_areg(regs, 7);
661: m68k_areg(regs, 7) = regs.usp;
662: } else {
663: regs.usp = m68k_areg(regs, 7);
664: m68k_areg(regs, 7) = regs.isp;
665: }
666: }
667: }
668:
1.1.1.8 root 669: /* Pending interrupts can occur again after a write to the SR: */
670: set_special (SPCFLAG_DOINT);
1.1 root 671: if (regs.t1 || regs.t0)
672: set_special (SPCFLAG_TRACE);
673: else
1.1.1.6 root 674: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
675: SR-modifying instructions (including STOP). */
676: unset_special (SPCFLAG_TRACE);
1.1 root 677: }
678:
1.1.1.5 root 679:
1.1 root 680: void Exception(int nr, uaecptr oldpc)
681: {
682: uae_u32 currpc = m68k_getpc ();
683:
1.1.1.2 root 684: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 685:
1.1.1.7 root 686: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
687: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
1.1.1.5 root 688: {
1.1.1.6 root 689: if(!VDI())
1.1.1.5 root 690: {
1.1.1.6 root 691: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
692: * This will call OpCode_VDI after completion of Trap call!
693: * Use to modify return structure from VDI */
694: VDI_OldPC = currpc;
695: currpc = CART_VDI_OPCODE_ADDR;
1.1.1.5 root 696: }
697: }
698:
1.1.1.8 root 699: #if 0
700: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
701: if (nr == 0x2d)
702: {
703: /* Intercept BIOS calls */
704: if (Bios()) return;
705: }
706: else if (nr == 0x2e)
707: {
708: /* Intercept XBIOS calls */
709: if (XBios()) return;
710: }
711: #endif
712:
1.1 root 713: MakeSR();
714:
1.1.1.8 root 715: /* Change to supervisor mode if necessary */
1.1 root 716: if (!regs.s) {
717: regs.usp = m68k_areg(regs, 7);
718: if (cpu_level >= 2)
719: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
720: else
721: m68k_areg(regs, 7) = regs.isp;
722: regs.s = 1;
723: }
1.1.1.8 root 724:
725: /* Build additional exception stack frame for 68010 and higher */
1.1 root 726: if (cpu_level > 0) {
727: if (nr == 2 || nr == 3) {
728: int i;
729: /* @@@ this is probably wrong (?) */
730: for (i = 0 ; i < 12 ; i++) {
731: m68k_areg(regs, 7) -= 2;
732: put_word (m68k_areg(regs, 7), 0);
733: }
734: m68k_areg(regs, 7) -= 2;
735: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
736: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
737: m68k_areg(regs, 7) -= 4;
738: put_long (m68k_areg(regs, 7), oldpc);
739: m68k_areg(regs, 7) -= 2;
740: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
741: } else if (regs.m && nr >= 24 && nr < 32) {
742: m68k_areg(regs, 7) -= 2;
743: put_word (m68k_areg(regs, 7), nr * 4);
744: m68k_areg(regs, 7) -= 4;
745: put_long (m68k_areg(regs, 7), currpc);
746: m68k_areg(regs, 7) -= 2;
747: put_word (m68k_areg(regs, 7), regs.sr);
748: regs.sr |= (1 << 13);
749: regs.msp = m68k_areg(regs, 7);
750: m68k_areg(regs, 7) = regs.isp;
751: m68k_areg(regs, 7) -= 2;
752: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
753: } else {
754: m68k_areg(regs, 7) -= 2;
755: put_word (m68k_areg(regs, 7), nr * 4);
756: }
757: }
1.1.1.3 root 758:
759: /* Push PC on stack: */
1.1 root 760: m68k_areg(regs, 7) -= 4;
761: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 762: /* Push SR on stack: */
1.1 root 763: m68k_areg(regs, 7) -= 2;
764: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 765:
766: /* 68000 bus/address errors: */
767: if (cpu_level==0 && (nr==2 || nr==3)) {
1.1.1.8 root 768: uae_u16 specialstatus = 0x2001;
769: /* Special status word emulation isn't perfect yet... :-( */
770: if (regs.sr & 0x2000)
771: specialstatus |= 0x4;
1.1.1.3 root 772: m68k_areg(regs, 7) -= 8;
773: if (nr == 3) { /* Address error */
1.1.1.8 root 774: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 775: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
776: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
777: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.8 root 778: if (bEnableDebug) {
779: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
780: DebugUI();
781: }
1.1.1.3 root 782: }
1.1.1.8 root 783: else { /* Bus error */
784: if (bBusErrorReadWrite)
785: specialstatus |= 0x10;
786: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 787: put_long (m68k_areg(regs, 7)+2, BusAddressLocation);
1.1.1.8 root 788: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
789: /* Check for double bus errors: */
790: if (regs.spcflags & SPCFLAG_BUSERROR) {
791: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
792: BusAddressLocation, (long)currpc);
793: unset_special(SPCFLAG_BUSERROR);
794: if (bEnableDebug)
795: DebugUI();
796: regs.intmask = 7;
797: m68k_setstopped(TRUE);
798: return;
799: }
800: if (bEnableDebug && BusAddressLocation!=0xff8a00) {
801: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n",BusAddressLocation,(long)currpc);
802: DebugUI();
803: }
804: }
1.1.1.3 root 805: }
806:
1.1.1.8 root 807: /* Set PC and flags */
808: if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) {
809: write_log("Uninitialized exception handler #%i!\n", nr);
810: }
1.1 root 811: m68k_setpc (get_long (regs.vbr + 4*nr));
812: fill_prefetch_0 ();
813: regs.t1 = regs.t0 = regs.m = 0;
814: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
1.1.1.6 root 815:
1.1.1.7 root 816: /* Handle exception cycles: */
817: if(nr >= 24 && nr <= 31)
818: {
1.1.1.8 root 819: M68000_AddCycles(44+4); /* Interrupt */
1.1.1.7 root 820: }
821: else if(nr >= 32 && nr <= 47)
822: {
1.1.1.8 root 823: M68000_AddCycles(34); /* Trap */
1.1.1.7 root 824: }
825: else switch(nr)
826: {
1.1.1.8 root 827: case 2: M68000_AddCycles(50); break; /* Bus error */
828: case 3: M68000_AddCycles(50); break; /* Address error */
829: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
830: case 5: M68000_AddCycles(38); break; /* Div by zero */
831: case 6: M68000_AddCycles(40); break; /* CHK */
832: case 7: M68000_AddCycles(34); break; /* TRAPV */
833: case 8: M68000_AddCycles(34); break; /* Privilege violation */
834: case 9: M68000_AddCycles(34); break; /* Trace */
835: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
836: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 837: default:
1.1.1.8 root 838: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 839: if(nr < 64)
1.1.1.8 root 840: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 841: else
1.1.1.8 root 842: M68000_AddCycles(24); /* Must be a MFP interrupt */
1.1.1.7 root 843: break;
1.1.1.6 root 844: }
1.1 root 845: }
846:
1.1.1.7 root 847:
1.1 root 848: static void Interrupt(int nr)
849: {
850: assert(nr < 8 && nr >= 0);
851: lastint_regs = regs;
852: lastint_no = nr;
853: Exception(nr+24, 0);
854:
855: regs.intmask = nr;
856: set_special (SPCFLAG_INT);
857: }
858:
1.1.1.7 root 859:
1.1.1.8 root 860: uae_u32 reg_caar, reg_cacr;
861: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 862:
1.1.1.7 root 863:
1.1 root 864: int m68k_move2c (int regno, uae_u32 *regp)
865: {
866: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
867: || (cpu_level < 4 && (regno & 0x7FF) > 2)
868: || (cpu_level == 4 && regno == 0x802))
869: {
870: op_illg (0x4E7B);
871: return 0;
872: } else {
873: switch (regno) {
874: case 0: regs.sfc = *regp & 7; break;
875: case 1: regs.dfc = *regp & 7; break;
1.1.1.8 root 876: case 2: reg_cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 877: case 3: tc = *regp & 0xc000; break;
878: /* Mask out fields that should be zero. */
879: case 4: itt0 = *regp & 0xffffe364; break;
880: case 5: itt1 = *regp & 0xffffe364; break;
881: case 6: dtt0 = *regp & 0xffffe364; break;
882: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 883:
1.1 root 884: case 0x800: regs.usp = *regp; break;
885: case 0x801: regs.vbr = *regp; break;
1.1.1.8 root 886: case 0x802: reg_caar = *regp & 0xfc; break;
1.1 root 887: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
888: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 889: case 0x805: mmusr = *regp; break;
890: case 0x806: urp = *regp; break;
891: case 0x807: srp = *regp; break;
1.1 root 892: default:
893: op_illg (0x4E7B);
894: return 0;
895: }
896: }
897: return 1;
898: }
899:
900: int m68k_movec2 (int regno, uae_u32 *regp)
901: {
902: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
903: || (cpu_level < 4 && (regno & 0x7FF) > 2)
904: || (cpu_level == 4 && regno == 0x802))
905: {
906: op_illg (0x4E7A);
907: return 0;
908: } else {
909: switch (regno) {
910: case 0: *regp = regs.sfc; break;
911: case 1: *regp = regs.dfc; break;
1.1.1.8 root 912: case 2: *regp = reg_cacr; break;
1.1 root 913: case 3: *regp = tc; break;
914: case 4: *regp = itt0; break;
915: case 5: *regp = itt1; break;
916: case 6: *regp = dtt0; break;
917: case 7: *regp = dtt1; break;
918: case 0x800: *regp = regs.usp; break;
919: case 0x801: *regp = regs.vbr; break;
1.1.1.8 root 920: case 0x802: *regp = reg_caar; break;
1.1 root 921: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
922: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
923: case 0x805: *regp = mmusr; break;
1.1.1.6 root 924: case 0x806: *regp = urp; break;
925: case 0x807: *regp = srp; break;
1.1 root 926: default:
927: op_illg (0x4E7A);
928: return 0;
929: }
930: }
931: return 1;
932: }
933:
934: STATIC_INLINE int
935: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
936: {
937: uae_u32 q = 0, cbit = 0;
938: int i;
939:
940: if (div <= src_hi) {
941: return 1;
942: }
943: for (i = 0 ; i < 32 ; i++) {
944: cbit = src_hi & 0x80000000ul;
945: src_hi <<= 1;
946: if (src_lo & 0x80000000ul) src_hi++;
947: src_lo <<= 1;
948: q = q << 1;
949: if (cbit || div <= src_hi) {
950: q |= 1;
951: src_hi -= div;
952: }
953: }
954: *quot = q;
955: *rem = src_hi;
956: return 0;
957: }
958:
959: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
960: {
961: #if defined(uae_s64)
962: if (src == 0) {
963: Exception (5, oldpc);
964: return;
965: }
966: if (extra & 0x800) {
967: /* signed variant */
968: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
969: uae_s64 quot, rem;
970:
971: if (extra & 0x400) {
972: a &= 0xffffffffu;
973: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
974: }
975: rem = a % (uae_s64)(uae_s32)src;
976: quot = a / (uae_s64)(uae_s32)src;
977: if ((quot & UVAL64(0xffffffff80000000)) != 0
978: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
979: {
980: SET_VFLG (1);
981: SET_NFLG (1);
982: SET_CFLG (0);
983: } else {
984: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
985: SET_VFLG (0);
986: SET_CFLG (0);
987: SET_ZFLG (((uae_s32)quot) == 0);
988: SET_NFLG (((uae_s32)quot) < 0);
989: m68k_dreg(regs, extra & 7) = rem;
990: m68k_dreg(regs, (extra >> 12) & 7) = quot;
991: }
992: } else {
993: /* unsigned */
994: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
995: uae_u64 quot, rem;
996:
997: if (extra & 0x400) {
998: a &= 0xffffffffu;
999: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1000: }
1001: rem = a % (uae_u64)src;
1002: quot = a / (uae_u64)src;
1003: if (quot > 0xffffffffu) {
1004: SET_VFLG (1);
1005: SET_NFLG (1);
1006: SET_CFLG (0);
1007: } else {
1008: SET_VFLG (0);
1009: SET_CFLG (0);
1010: SET_ZFLG (((uae_s32)quot) == 0);
1011: SET_NFLG (((uae_s32)quot) < 0);
1012: m68k_dreg(regs, extra & 7) = rem;
1013: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1014: }
1015: }
1016: #else
1017: if (src == 0) {
1018: Exception (5, oldpc);
1019: return;
1020: }
1021: if (extra & 0x800) {
1022: /* signed variant */
1023: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1024: uae_s32 hi = lo < 0 ? -1 : 0;
1025: uae_s32 save_high;
1026: uae_u32 quot, rem;
1027: uae_u32 sign;
1028:
1029: if (extra & 0x400) {
1030: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1031: }
1032: save_high = hi;
1033: sign = (hi ^ src);
1034: if (hi < 0) {
1035: hi = ~hi;
1036: lo = -lo;
1037: if (lo == 0) hi++;
1038: }
1039: if ((uae_s32)src < 0) src = -src;
1040: if (div_unsigned(hi, lo, src, ", &rem) ||
1041: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1042: SET_VFLG (1);
1043: SET_NFLG (1);
1044: SET_CFLG (0);
1045: } else {
1046: if (sign & 0x80000000) quot = -quot;
1047: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1048: SET_VFLG (0);
1049: SET_CFLG (0);
1050: SET_ZFLG (((uae_s32)quot) == 0);
1051: SET_NFLG (((uae_s32)quot) < 0);
1052: m68k_dreg(regs, extra & 7) = rem;
1053: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1054: }
1055: } else {
1056: /* unsigned */
1057: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1058: uae_u32 hi = 0;
1059: uae_u32 quot, rem;
1060:
1061: if (extra & 0x400) {
1062: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1063: }
1064: if (div_unsigned(hi, lo, src, ", &rem)) {
1065: SET_VFLG (1);
1066: SET_NFLG (1);
1067: SET_CFLG (0);
1068: } else {
1069: SET_VFLG (0);
1070: SET_CFLG (0);
1071: SET_ZFLG (((uae_s32)quot) == 0);
1072: SET_NFLG (((uae_s32)quot) < 0);
1073: m68k_dreg(regs, extra & 7) = rem;
1074: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1075: }
1076: }
1077: #endif
1078: }
1079:
1080: STATIC_INLINE void
1081: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1082: {
1083: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1084: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1085: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1086: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1087: uae_u32 lo;
1088:
1089: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1090: if (lo < r0) r3++;
1091: r0 = lo;
1092: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1093: if (lo < r0) r3++;
1094: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1095: *dst_lo = lo;
1096: *dst_hi = r3;
1097: }
1098:
1099: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1100: {
1101: #if defined(uae_s64)
1102: if (extra & 0x800) {
1103: /* signed variant */
1104: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1105:
1106: a *= (uae_s64)(uae_s32)src;
1107: SET_VFLG (0);
1108: SET_CFLG (0);
1109: SET_ZFLG (a == 0);
1110: SET_NFLG (a < 0);
1111: if (extra & 0x400)
1112: m68k_dreg(regs, extra & 7) = a >> 32;
1113: else if ((a & UVAL64(0xffffffff80000000)) != 0
1114: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1115: {
1116: SET_VFLG (1);
1117: }
1118: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1119: } else {
1120: /* unsigned */
1121: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1122:
1123: a *= (uae_u64)src;
1124: SET_VFLG (0);
1125: SET_CFLG (0);
1126: SET_ZFLG (a == 0);
1127: SET_NFLG (((uae_s64)a) < 0);
1128: if (extra & 0x400)
1129: m68k_dreg(regs, extra & 7) = a >> 32;
1130: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1131: SET_VFLG (1);
1132: }
1133: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1134: }
1135: #else
1136: if (extra & 0x800) {
1137: /* signed variant */
1138: uae_s32 src1,src2;
1139: uae_u32 dst_lo,dst_hi;
1140: uae_u32 sign;
1141:
1142: src1 = (uae_s32)src;
1143: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1144: sign = (src1 ^ src2);
1145: if (src1 < 0) src1 = -src1;
1146: if (src2 < 0) src2 = -src2;
1147: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1148: if (sign & 0x80000000) {
1149: dst_hi = ~dst_hi;
1150: dst_lo = -dst_lo;
1151: if (dst_lo == 0) dst_hi++;
1152: }
1153: SET_VFLG (0);
1154: SET_CFLG (0);
1155: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1156: SET_NFLG (((uae_s32)dst_hi) < 0);
1157: if (extra & 0x400)
1158: m68k_dreg(regs, extra & 7) = dst_hi;
1159: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1160: && ((dst_hi & 0xffffffff) != 0xffffffff
1161: || (dst_lo & 0x80000000) != 0x80000000))
1162: {
1163: SET_VFLG (1);
1164: }
1165: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1166: } else {
1167: /* unsigned */
1168: uae_u32 dst_lo,dst_hi;
1169:
1170: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1171:
1172: SET_VFLG (0);
1173: SET_CFLG (0);
1174: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1175: SET_NFLG (((uae_s32)dst_hi) < 0);
1176: if (extra & 0x400)
1177: m68k_dreg(regs, extra & 7) = dst_hi;
1178: else if (dst_hi != 0) {
1179: SET_VFLG (1);
1180: }
1181: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1182: }
1183: #endif
1184: }
1.1.1.6 root 1185:
1.1 root 1186:
1187: void m68k_reset (void)
1188: {
1189: regs.s = 1;
1190: regs.m = 0;
1191: regs.stopped = 0;
1192: regs.t1 = 0;
1193: regs.t0 = 0;
1194: SET_ZFLG (0);
1195: SET_XFLG (0);
1196: SET_CFLG (0);
1197: SET_VFLG (0);
1198: SET_NFLG (0);
1.1.1.7 root 1199: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1200: regs.intmask = 7;
1201: regs.vbr = regs.sfc = regs.dfc = 0;
1202: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1203:
1204: m68k_areg(regs, 7) = get_long(0);
1205: m68k_setpc(get_long(4));
1206: refill_prefetch (m68k_getpc(), 0);
1.1 root 1207: }
1208:
1.1.1.8 root 1209:
1.1 root 1210: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1211: {
1.1.1.8 root 1212: #if 0
1.1 root 1213: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1214: #endif
1.1.1.6 root 1215: if ((opcode & 0xF000) == 0xF000) {
1.1 root 1216: Exception(0xB,0);
1217: return 4;
1.1.1.6 root 1218: }
1219: if ((opcode & 0xF000) == 0xA000) {
1.1 root 1220: Exception(0xA,0);
1221: return 4;
1.1.1.6 root 1222: }
1.1.1.3 root 1223: #if 0
1.1.1.6 root 1224: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1225: #endif
1226: Exception (4,0);
1227: return 4;
1228: }
1229:
1.1.1.8 root 1230:
1.1 root 1231: void mmu_op(uae_u32 opcode, uae_u16 extra)
1232: {
1233: if ((opcode & 0xFE0) == 0x0500) {
1234: /* PFLUSH */
1235: mmusr = 0;
1236: write_log ("PFLUSH\n");
1237: } else if ((opcode & 0x0FD8) == 0x548) {
1238: /* PTEST */
1239: write_log ("PTEST\n");
1240: } else
1241: op_illg (opcode);
1242: }
1243:
1244:
1245: static uaecptr last_trace_ad = 0;
1246:
1247: static void do_trace (void)
1248: {
1249: if (regs.t0 && cpu_level >= 2) {
1250: uae_u16 opcode;
1251: /* should also include TRAP, CHK, SR modification FPcc */
1252: /* probably never used so why bother */
1253: /* We can afford this to be inefficient... */
1254: m68k_setpc (m68k_getpc ());
1255: fill_prefetch_0 ();
1256: opcode = get_word (regs.pc);
1257: if (opcode == 0x4e72 /* RTE */
1258: || opcode == 0x4e74 /* RTD */
1259: || opcode == 0x4e75 /* RTS */
1260: || opcode == 0x4e77 /* RTR */
1261: || opcode == 0x4e76 /* TRAPV */
1262: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1263: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1264: || (opcode & 0xff00) == 0x6100 /* BSR */
1265: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1266: && cctrue((opcode >> 8) & 0xf))
1267: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1268: && !cctrue((opcode >> 8) & 0xf)
1269: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1270: {
1271: last_trace_ad = m68k_getpc ();
1272: unset_special (SPCFLAG_TRACE);
1273: set_special (SPCFLAG_DOTRACE);
1274: }
1275: } else if (regs.t1) {
1276: last_trace_ad = m68k_getpc ();
1277: unset_special (SPCFLAG_TRACE);
1278: set_special (SPCFLAG_DOTRACE);
1279: }
1280: }
1281:
1282:
1.1.1.8 root 1283: /*
1284: * Handle special flags
1285: */
1.1 root 1286: static int do_specialties (void)
1287: {
1.1.1.7 root 1288: if(regs.spcflags & SPCFLAG_BUSERROR) {
1289: /* We can not execute bus errors directly in the memory handler
1290: * functions since the PC should point to the address of the next
1291: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1292: unset_special(SPCFLAG_BUSERROR);
1.1.1.7 root 1293: Exception(2,0);
1294: }
1295:
1.1.1.8 root 1296: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1297: /* Add some extra cycles to simulate a wait state */
1298: unset_special(SPCFLAG_EXTRA_CYCLES);
1299: M68000_AddCycles(4);
1300: }
1301:
1.1 root 1302: if (regs.spcflags & SPCFLAG_DOTRACE) {
1303: Exception (9,last_trace_ad);
1304: }
1.1.1.8 root 1305:
1.1 root 1306: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.8 root 1307: if (regs.intmask > 5) {
1308: /* We still have to care about events when IPL==7 ! */
1309: Main_EventHandler();
1310: if (regs.spcflags & SPCFLAG_BRK) return 1;
1311: }
1312: M68000_AddCycles(4);
1313: if (PendingInterruptCount<=0 && PendingInterruptFunction) {
1314: CALL_VAR(PendingInterruptFunction);
1315: }
1316: if (regs.spcflags & SPCFLAG_MFP) {
1317: MFP_CheckPendingInterrupts();
1318: }
1.1.1.5 root 1319: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1320: int intr = intlev ();
1.1 root 1321: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1322: if (intr != -1 && intr > regs.intmask) {
1.1 root 1323: Interrupt (intr);
1324: regs.stopped = 0;
1325: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1326: }
1.1 root 1327: }
1328: }
1.1.1.8 root 1329:
1.1 root 1330: if (regs.spcflags & SPCFLAG_TRACE)
1331: do_trace ();
1332:
1333: if (regs.spcflags & SPCFLAG_DOINT) {
1.1.1.6 root 1334: int intr = intlev ();
1.1.1.8 root 1335: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1 root 1336: unset_special (SPCFLAG_DOINT);
1.1.1.6 root 1337: if (intr != -1 && intr > regs.intmask) {
1.1 root 1338: Interrupt (intr);
1339: regs.stopped = 0;
1.1.1.6 root 1340: }
1.1 root 1341: }
1342: if (regs.spcflags & SPCFLAG_INT) {
1343: unset_special (SPCFLAG_INT);
1344: set_special (SPCFLAG_DOINT);
1345: }
1.1.1.8 root 1346:
1347: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1348: MFP_CheckPendingInterrupts();
1349: }
1350:
1.1 root 1351: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1352: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1353: return 1;
1354: }
1.1.1.8 root 1355:
1.1 root 1356: return 0;
1357: }
1358:
1.1.1.3 root 1359:
1.1 root 1360: /* It's really sad to have two almost identical functions for this, but we
1361: do it all for performance... :( */
1362: static void m68k_run_1 (void)
1363: {
1364: #ifdef DEBUG_PREFETCH
1365: uae_u8 saved_bytes[20];
1366: uae_u16 *oldpcp;
1367: #endif
1.1.1.8 root 1368:
1369: for (;;) {
1.1 root 1370: int cycles;
1371: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1372:
1.1 root 1373: #ifdef DEBUG_PREFETCH
1374: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1375: fprintf (stderr, "Prefetch differs from memory.\n");
1376: debugging = 1;
1377: return;
1378: }
1379: oldpcp = regs.pc_p;
1380: memcpy (saved_bytes, regs.pc_p, 20);
1381: #endif
1382:
1383: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1384: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1385:
1386: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1387: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1388: #if COUNT_INSTRS == 2
1389: if (table68k[opcode].handler != -1)
1390: instrcount[table68k[opcode].handler]++;
1391: #elif COUNT_INSTRS == 1
1392: instrcount[opcode]++;
1393: #endif
1.1.1.2 root 1394:
1.1.1.6 root 1395: cycles = (*cpufunctbl[opcode])(opcode);
1396:
1.1 root 1397: #ifdef DEBUG_PREFETCH
1398: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1399: fprintf (stderr, "Self-modifying code detected.\n");
1400: set_special (SPCFLAG_BRK);
1401: debugging = 1;
1402: }
1403: #endif
1.1.1.2 root 1404:
1.1.1.8 root 1405: M68000_AddCycles(cycles);
1406: if (PendingInterruptCount<=0 && PendingInterruptFunction)
1407: CALL_VAR(PendingInterruptFunction);
1408:
1.1 root 1409: if (regs.spcflags) {
1410: if (do_specialties ())
1411: return;
1412: }
1413: }
1414: }
1415:
1416:
1417: /* Same thing, but don't use prefetch to get opcode. */
1418: static void m68k_run_2 (void)
1419: {
1.1.1.8 root 1420: for (;;) {
1.1 root 1421: int cycles;
1422: uae_u32 opcode = get_iword (0);
1423:
1424: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1425: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1426:
1427: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1428: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1429: #if COUNT_INSTRS == 2
1430: if (table68k[opcode].handler != -1)
1431: instrcount[table68k[opcode].handler]++;
1432: #elif COUNT_INSTRS == 1
1433: instrcount[opcode]++;
1434: #endif
1.1.1.2 root 1435:
1.1.1.6 root 1436: cycles = (*cpufunctbl[opcode])(opcode);
1437:
1.1.1.8 root 1438: M68000_AddCycles(cycles);
1439: if (PendingInterruptCount<=0 && PendingInterruptFunction)
1440: CALL_VAR(PendingInterruptFunction);
1441:
1.1 root 1442: if (regs.spcflags) {
1443: if (do_specialties ())
1444: return;
1445: }
1446: }
1447: }
1448:
1449:
1450: void m68k_go (int may_quit)
1451: {
1.1.1.8 root 1452: static int in_m68k_go = 0;
1453:
1.1 root 1454: if (in_m68k_go || !may_quit) {
1455: write_log ("Bug! m68k_go is not reentrant.\n");
1456: abort ();
1457: }
1458:
1459: in_m68k_go++;
1.1.1.8 root 1460: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.2 root 1461: if(cpu_compatible)
1462: m68k_run_1();
1463: else
1464: m68k_run_2();
1.1 root 1465: }
1.1.1.8 root 1466: unset_special(SPCFLAG_BRK);
1.1 root 1467: in_m68k_go--;
1468: }
1469:
1.1.1.8 root 1470:
1471: /*
1.1 root 1472: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1473: {
1474: uae_u32 opcode, val;
1475: struct instr *dp;
1476:
1477: opcode = get_iword_1(0);
1478: last_op_for_exception_3 = opcode;
1479: m68kpc_offset = 2;
1480:
1.1.1.6 root 1481: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1482: opcode = 0x4AFC;
1483: }
1484: dp = table68k + opcode;
1485:
1486: if (dp->suse) {
1487: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1488: Exception (3, 0);
1489: return;
1490: }
1491: }
1492: if (dp->duse) {
1493: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1494: Exception (3, 0);
1495: return;
1496: }
1497: }
1498: }
1.1.1.8 root 1499: */
1500:
1.1 root 1501:
1502: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1503: {
1.1.1.8 root 1504: static const char* ccnames[] =
1505: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1506: "VC","VS","PL","MI","GE","LT","GT","LE" };
1507:
1.1 root 1508: uaecptr newpc = 0;
1509: m68kpc_offset = addr - m68k_getpc ();
1510: while (cnt-- > 0) {
1511: char instrname[20],*ccpt;
1512: int opwords;
1513: uae_u32 opcode;
1514: struct mnemolookup *lookup;
1515: struct instr *dp;
1516: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1517: for (opwords = 0; opwords < 5; opwords++){
1518: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1519: }
1520: opcode = get_iword_1 (m68kpc_offset);
1521: m68kpc_offset += 2;
1.1.1.6 root 1522: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1523: opcode = 0x4AFC;
1524: }
1525: dp = table68k + opcode;
1526: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1527: ;
1528:
1529: strcpy (instrname, lookup->name);
1530: ccpt = strstr (instrname, "cc");
1531: if (ccpt != 0) {
1532: strncpy (ccpt, ccnames[dp->cc], 2);
1533: }
1534: fprintf (f, "%s", instrname);
1535: switch (dp->size){
1536: case sz_byte: fprintf (f, ".B "); break;
1537: case sz_word: fprintf (f, ".W "); break;
1538: case sz_long: fprintf (f, ".L "); break;
1539: default: fprintf (f, " "); break;
1540: }
1541:
1542: if (dp->suse) {
1543: newpc = m68k_getpc () + m68kpc_offset;
1544: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1545: }
1546: if (dp->suse && dp->duse)
1547: fprintf (f, ",");
1548: if (dp->duse) {
1549: newpc = m68k_getpc () + m68kpc_offset;
1550: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1551: }
1552: if (ccpt != 0) {
1553: if (cctrue(dp->cc))
1.1.1.5 root 1554: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1555: else
1.1.1.5 root 1556: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1557: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1558: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1559: fprintf (f, "\n");
1560: }
1561: if (nextpc)
1562: *nextpc = m68k_getpc () + m68kpc_offset;
1563: }
1564:
1565: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1566: {
1567: int i;
1568: for (i = 0; i < 8; i++){
1.1.1.5 root 1569: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1570: if ((i & 3) == 3) fprintf (f, "\n");
1571: }
1572: for (i = 0; i < 8; i++){
1.1.1.5 root 1573: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1574: if ((i & 3) == 3) fprintf (f, "\n");
1575: }
1576: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1577: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1578: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1579: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1580: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1581: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1582: regs.t1, regs.t0, regs.s, regs.m,
1583: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1584: for (i = 0; i < 8; i++){
1585: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1586: if ((i & 3) == 3) fprintf (f, "\n");
1587: }
1588: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1589: (regs.fpsr & 0x8000000) != 0,
1590: (regs.fpsr & 0x4000000) != 0,
1591: (regs.fpsr & 0x2000000) != 0,
1592: (regs.fpsr & 0x1000000) != 0);
1593: if (cpu_compatible)
1594: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1595:
1596: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1597: if (nextpc)
1.1.1.5 root 1598: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1599: }
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