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1.1 root 1: /*
1.1.1.3 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * Read 68000 CPU specs from file "table68k"
5: *
6: * Copyright 1995,1996 Bernd Schmidt
1.1.1.3 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.11 root 10: * This file is distributed under the GNU General Public License, version 2
11: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.8 root 13:
14:
15: /* 2008/04/26 [NP] Handle sz_byte for Areg as a valid srcmode if current instruction is a MOVE */
16: /* (e.g. move.b a1,(a0) ($1089)) (fix Blood Money on Superior 65) */
1.1.1.12! root 17: /* 2014/08/15 [NP] Cancel change from 2008/04/26, sz_byte for Areg is not valid for MOVE, */
! 18: /* 'move.b a1,(a0)' should give an illegal exception */
1.1.1.8 root 19:
20:
1.1.1.10 root 21: const char ReadCpu_fileid[] = "Hatari readcpu.c : " __DATE__ " " __TIME__;
1.1 root 22:
23: #include <ctype.h>
1.1.1.2 root 24: #include <string.h>
25:
1.1 root 26: #include "readcpu.h"
27:
28: int nr_cpuop_funcs;
29:
1.1.1.6 root 30: const struct mnemolookup lookuptab[] = {
1.1 root 31: { i_ILLG, "ILLEGAL" },
32: { i_OR, "OR" },
33: { i_CHK, "CHK" },
34: { i_CHK2, "CHK2" },
35: { i_AND, "AND" },
36: { i_EOR, "EOR" },
37: { i_ORSR, "ORSR" },
38: { i_ANDSR, "ANDSR" },
39: { i_EORSR, "EORSR" },
40: { i_SUB, "SUB" },
41: { i_SUBA, "SUBA" },
42: { i_SUBX, "SUBX" },
43: { i_SBCD, "SBCD" },
44: { i_ADD, "ADD" },
45: { i_ADDA, "ADDA" },
46: { i_ADDX, "ADDX" },
47: { i_ABCD, "ABCD" },
48: { i_NEG, "NEG" },
49: { i_NEGX, "NEGX" },
50: { i_NBCD, "NBCD" },
51: { i_CLR, "CLR" },
52: { i_NOT, "NOT" },
53: { i_TST, "TST" },
54: { i_BTST, "BTST" },
55: { i_BCHG, "BCHG" },
56: { i_BCLR, "BCLR" },
57: { i_BSET, "BSET" },
58: { i_CMP, "CMP" },
59: { i_CMPM, "CMPM" },
60: { i_CMPA, "CMPA" },
61: { i_MVPRM, "MVPRM" },
62: { i_MVPMR, "MVPMR" },
63: { i_MOVE, "MOVE" },
64: { i_MOVEA, "MOVEA" },
65: { i_MVSR2, "MVSR2" },
66: { i_MV2SR, "MV2SR" },
67: { i_SWAP, "SWAP" },
68: { i_EXG, "EXG" },
69: { i_EXT, "EXT" },
70: { i_MVMEL, "MVMEL" },
71: { i_MVMLE, "MVMLE" },
72: { i_TRAP, "TRAP" },
73: { i_MVR2USP, "MVR2USP" },
74: { i_MVUSP2R, "MVUSP2R" },
75: { i_NOP, "NOP" },
76: { i_RESET, "RESET" },
77: { i_RTE, "RTE" },
78: { i_RTD, "RTD" },
79: { i_LINK, "LINK" },
80: { i_UNLK, "UNLK" },
81: { i_RTS, "RTS" },
82: { i_STOP, "STOP" },
83: { i_TRAPV, "TRAPV" },
84: { i_RTR, "RTR" },
85: { i_JSR, "JSR" },
86: { i_JMP, "JMP" },
87: { i_BSR, "BSR" },
88: { i_Bcc, "Bcc" },
89: { i_LEA, "LEA" },
90: { i_PEA, "PEA" },
91: { i_DBcc, "DBcc" },
92: { i_Scc, "Scc" },
93: { i_DIVU, "DIVU" },
94: { i_DIVS, "DIVS" },
95: { i_MULU, "MULU" },
96: { i_MULS, "MULS" },
97: { i_ASR, "ASR" },
98: { i_ASL, "ASL" },
99: { i_LSR, "LSR" },
100: { i_LSL, "LSL" },
101: { i_ROL, "ROL" },
102: { i_ROR, "ROR" },
103: { i_ROXL, "ROXL" },
104: { i_ROXR, "ROXR" },
105: { i_ASRW, "ASRW" },
106: { i_ASLW, "ASLW" },
107: { i_LSRW, "LSRW" },
108: { i_LSLW, "LSLW" },
109: { i_ROLW, "ROLW" },
110: { i_RORW, "RORW" },
111: { i_ROXLW, "ROXLW" },
112: { i_ROXRW, "ROXRW" },
113:
114: { i_MOVE2C, "MOVE2C" },
115: { i_MOVEC2, "MOVEC2" },
116: { i_CAS, "CAS" },
117: { i_CAS2, "CAS2" },
118: { i_MULL, "MULL" },
119: { i_DIVL, "DIVL" },
120: { i_BFTST, "BFTST" },
121: { i_BFEXTU, "BFEXTU" },
122: { i_BFCHG, "BFCHG" },
123: { i_BFEXTS, "BFEXTS" },
124: { i_BFCLR, "BFCLR" },
125: { i_BFFFO, "BFFFO" },
126: { i_BFSET, "BFSET" },
127: { i_BFINS, "BFINS" },
128: { i_PACK, "PACK" },
129: { i_UNPK, "UNPK" },
130: { i_TAS, "TAS" },
131: { i_BKPT, "BKPT" },
132: { i_CALLM, "CALLM" },
133: { i_RTM, "RTM" },
134: { i_TRAPcc, "TRAPcc" },
135: { i_MOVES, "MOVES" },
136: { i_FPP, "FPP" },
137: { i_FDBcc, "FDBcc" },
138: { i_FScc, "FScc" },
139: { i_FTRAPcc, "FTRAPcc" },
140: { i_FBcc, "FBcc" },
141: { i_FBcc, "FBcc" },
142: { i_FSAVE, "FSAVE" },
143: { i_FRESTORE, "FRESTORE" },
144:
145: { i_CINVL, "CINVL" },
146: { i_CINVP, "CINVP" },
147: { i_CINVA, "CINVA" },
148: { i_CPUSHL, "CPUSHL" },
149: { i_CPUSHP, "CPUSHP" },
150: { i_CPUSHA, "CPUSHA" },
151: { i_MOVE16, "MOVE16" },
152:
153: { i_MMUOP, "MMUOP" },
154: { i_ILLG, "" },
155: };
156:
157: struct instr *table68k;
158:
159: STATIC_INLINE amodes mode_from_str (const char *str)
160: {
161: if (strncmp (str, "Dreg", 4) == 0) return Dreg;
162: if (strncmp (str, "Areg", 4) == 0) return Areg;
163: if (strncmp (str, "Aind", 4) == 0) return Aind;
164: if (strncmp (str, "Apdi", 4) == 0) return Apdi;
165: if (strncmp (str, "Aipi", 4) == 0) return Aipi;
166: if (strncmp (str, "Ad16", 4) == 0) return Ad16;
167: if (strncmp (str, "Ad8r", 4) == 0) return Ad8r;
168: if (strncmp (str, "absw", 4) == 0) return absw;
169: if (strncmp (str, "absl", 4) == 0) return absl;
170: if (strncmp (str, "PC16", 4) == 0) return PC16;
171: if (strncmp (str, "PC8r", 4) == 0) return PC8r;
172: if (strncmp (str, "Immd", 4) == 0) return imm;
173: abort ();
174: return 0;
175: }
176:
177: STATIC_INLINE amodes mode_from_mr (int mode, int reg)
178: {
179: switch (mode) {
180: case 0: return Dreg;
181: case 1: return Areg;
182: case 2: return Aind;
183: case 3: return Aipi;
184: case 4: return Apdi;
185: case 5: return Ad16;
186: case 6: return Ad8r;
187: case 7:
188: switch (reg) {
189: case 0: return absw;
190: case 1: return absl;
191: case 2: return PC16;
192: case 3: return PC8r;
193: case 4: return imm;
194: case 5:
195: case 6:
196: case 7: return am_illg;
197: }
198: }
199: abort ();
200: return 0;
201: }
202:
203: static void build_insn (int insn)
204: {
205: int find = -1;
206: int variants;
1.1.1.3 root 207: int isjmp = 0;
1.1 root 208: struct instr_def id;
209: const char *opcstr;
1.1.1.5 root 210: int j;
1.1 root 211:
212: int flaglive = 0, flagdead = 0;
213:
214: id = defs68k[insn];
215:
1.1.1.3 root 216: /* Note: We treat anything with unknown flags as a jump. That
217: is overkill, but "the programmer" was lazy quite often, and
218: *this* programmer can't be bothered to work out what can and
219: can't trap. Usually, this will be overwritten with the gencomp
220: based information, anyway. */
221:
1.1.1.5 root 222: for (j = 0; j < 5; j++) {
223: switch (id.flaginfo[j].flagset){
1.1 root 224: case fa_unset: break;
1.1.1.3 root 225: case fa_isjmp: isjmp = 1; break;
226: case fa_isbranch: isjmp = 1; break;
1.1.1.5 root 227: case fa_zero: flagdead |= 1 << j; break;
228: case fa_one: flagdead |= 1 << j; break;
229: case fa_dontcare: flagdead |= 1 << j; break;
1.1.1.3 root 230: case fa_unknown: isjmp = 1; flagdead = -1; goto out1;
1.1.1.5 root 231: case fa_set: flagdead |= 1 << j; break;
1.1 root 232: }
233: }
234:
1.1.1.3 root 235: out1:
1.1.1.5 root 236: for (j = 0; j < 5; j++) {
237: switch (id.flaginfo[j].flaguse) {
1.1 root 238: case fu_unused: break;
1.1.1.5 root 239: case fu_isjmp: isjmp = 1; flaglive |= 1 << j; break;
240: case fu_maybecc: isjmp = 1; flaglive |= 1 << j; break;
241: case fu_unknown: isjmp = 1; flaglive |= 1 << j; break;
242: case fu_used: flaglive |= 1 << j; break;
1.1 root 243: }
244: }
245:
246: opcstr = id.opcstr;
247: for (variants = 0; variants < (1 << id.n_variable); variants++) {
248: int bitcnt[lastbit];
249: int bitval[lastbit];
250: int bitpos[lastbit];
251: int i;
252: uae_u16 opc = id.bits;
253: uae_u16 msk, vmsk;
254: int pos = 0;
255: int mnp = 0;
256: int bitno = 0;
257: char mnemonic[10];
258:
259: wordsizes sz = sz_long;
260: int srcgather = 0, dstgather = 0;
261: int usesrc = 0, usedst = 0;
262: int srctype = 0;
263: int srcpos = -1, dstpos = -1;
264:
265: amodes srcmode = am_unknown, destmode = am_unknown;
266: int srcreg = -1, destreg = -1;
267:
268: for (i = 0; i < lastbit; i++)
269: bitcnt[i] = bitval[i] = 0;
270:
271: vmsk = 1 << id.n_variable;
272:
273: for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {
274: if (!(msk & id.mask)) {
275: int currbit = id.bitpos[bitno++];
276: int bit_set;
277: vmsk >>= 1;
278: bit_set = variants & vmsk ? 1 : 0;
279: if (bit_set)
280: opc |= msk;
281: bitpos[currbit] = 15 - i;
282: bitcnt[currbit]++;
283: bitval[currbit] <<= 1;
284: bitval[currbit] |= bit_set;
285: }
286: }
287:
288: if (bitval[bitj] == 0) bitval[bitj] = 8;
289: /* first check whether this one does not match after all */
290: if (bitval[bitz] == 3 || bitval[bitC] == 1)
291: continue;
292: if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
293: continue;
294:
295: /* bitI and bitC get copied to biti and bitc */
296: if (bitcnt[bitI]) {
297: bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
298: }
299: if (bitcnt[bitC])
300: bitval[bitc] = bitval[bitC];
301:
302: pos = 0;
1.1.1.7 root 303: while (opcstr[pos] && !isspace((unsigned)opcstr[pos])) {
1.1 root 304: if (opcstr[pos] == '.') {
305: pos++;
306: switch (opcstr[pos]) {
307:
308: case 'B': sz = sz_byte; break;
309: case 'W': sz = sz_word; break;
310: case 'L': sz = sz_long; break;
311: case 'z':
312: switch (bitval[bitz]) {
313: case 0: sz = sz_byte; break;
314: case 1: sz = sz_word; break;
315: case 2: sz = sz_long; break;
316: default: abort();
317: }
318: break;
319: default: abort();
320: }
321: } else {
322: mnemonic[mnp] = opcstr[pos];
323: if (mnemonic[mnp] == 'f') {
324: find = -1;
325: switch (bitval[bitf]) {
326: case 0: mnemonic[mnp] = 'R'; break;
327: case 1: mnemonic[mnp] = 'L'; break;
328: default: abort();
329: }
330: }
331: mnp++;
332: }
333: pos++;
334: }
335: mnemonic[mnp] = 0;
336:
337: /* now, we have read the mnemonic and the size */
1.1.1.7 root 338: while (opcstr[pos] && isspace((unsigned)opcstr[pos]))
1.1 root 339: pos++;
340:
341: /* A goto a day keeps the D******a away. */
342: if (opcstr[pos] == 0)
343: goto endofline;
344:
345: /* parse the source address */
346: usesrc = 1;
347: switch (opcstr[pos++]) {
348: case 'D':
349: srcmode = Dreg;
350: switch (opcstr[pos++]) {
351: case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
352: case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
353: default: abort();
354: }
355:
356: break;
357: case 'A':
358: srcmode = Areg;
359: switch (opcstr[pos++]) {
360: case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
361: case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
362: default: abort();
363: }
364: switch (opcstr[pos]) {
365: case 'p': srcmode = Apdi; pos++; break;
366: case 'P': srcmode = Aipi; pos++; break;
367: }
368: break;
1.1.1.3 root 369: case 'L':
370: srcmode = absl;
371: break;
1.1 root 372: case '#':
373: switch (opcstr[pos++]) {
374: case 'z': srcmode = imm; break;
375: case '0': srcmode = imm0; break;
376: case '1': srcmode = imm1; break;
377: case '2': srcmode = imm2; break;
378: case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti];
379: if (CPU_EMU_SIZE < 4) {
380: /* Used for branch instructions */
381: srctype = 1;
382: srcgather = 1;
383: srcpos = bitpos[biti];
384: }
385: break;
386: case 'j': srcmode = immi; srcreg = bitval[bitj];
387: if (CPU_EMU_SIZE < 3) {
388: /* 1..8 for ADDQ/SUBQ and rotshi insns */
389: srcgather = 1;
390: srctype = 3;
391: srcpos = bitpos[bitj];
392: }
393: break;
394: case 'J': srcmode = immi; srcreg = bitval[bitJ];
395: if (CPU_EMU_SIZE < 5) {
396: /* 0..15 */
397: srcgather = 1;
398: srctype = 2;
399: srcpos = bitpos[bitJ];
400: }
401: break;
402: case 'k': srcmode = immi; srcreg = bitval[bitk];
403: if (CPU_EMU_SIZE < 3) {
404: srcgather = 1;
405: srctype = 4;
406: srcpos = bitpos[bitk];
407: }
408: break;
409: case 'K': srcmode = immi; srcreg = bitval[bitK];
410: if (CPU_EMU_SIZE < 5) {
411: /* 0..15 */
412: srcgather = 1;
413: srctype = 5;
414: srcpos = bitpos[bitK];
415: }
416: break;
1.1.1.3 root 417: case 'p': srcmode = immi; srcreg = bitval[bitK];
418: if (CPU_EMU_SIZE < 5) {
419: /* 0..3 */
420: srcgather = 1;
421: srctype = 7;
422: srcpos = bitpos[bitp];
423: }
424: break;
1.1 root 425: default: abort();
426: }
427: break;
428: case 'd':
429: srcreg = bitval[bitD];
430: srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);
431: if (srcmode == am_illg)
432: continue;
433: if (CPU_EMU_SIZE < 2 &&
434: (srcmode == Areg || srcmode == Dreg || srcmode == Aind
435: || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
436: || srcmode == Apdi))
437: {
438: srcgather = 1; srcpos = bitpos[bitD];
439: }
440: if (opcstr[pos] == '[') {
441: pos++;
442: if (opcstr[pos] == '!') {
443: /* exclusion */
444: do {
445: pos++;
446: if (mode_from_str(opcstr+pos) == srcmode)
447: goto nomatch;
448: pos += 4;
449: } while (opcstr[pos] == ',');
450: pos++;
451: } else {
452: if (opcstr[pos+4] == '-') {
453: /* replacement */
454: if (mode_from_str(opcstr+pos) == srcmode)
455: srcmode = mode_from_str(opcstr+pos+5);
456: else
457: goto nomatch;
458: pos += 10;
459: } else {
460: /* normal */
461: while(mode_from_str(opcstr+pos) != srcmode) {
462: pos += 4;
463: if (opcstr[pos] == ']')
464: goto nomatch;
465: pos++;
466: }
467: while(opcstr[pos] != ']') pos++;
468: pos++;
469: break;
470: }
471: }
472: }
473: /* Some addressing modes are invalid as destination */
474: if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
475: goto nomatch;
476: break;
477: case 's':
478: srcreg = bitval[bitS];
479: srcmode = mode_from_mr(bitval[bits],bitval[bitS]);
480:
481: if (srcmode == am_illg)
482: continue;
483: if (CPU_EMU_SIZE < 2 &&
484: (srcmode == Areg || srcmode == Dreg || srcmode == Aind
485: || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
486: || srcmode == Apdi))
487: {
488: srcgather = 1; srcpos = bitpos[bitS];
489: }
490: if (opcstr[pos] == '[') {
491: pos++;
492: if (opcstr[pos] == '!') {
493: /* exclusion */
494: do {
495: pos++;
496: if (mode_from_str(opcstr+pos) == srcmode)
497: goto nomatch;
498: pos += 4;
499: } while (opcstr[pos] == ',');
500: pos++;
501: } else {
502: if (opcstr[pos+4] == '-') {
503: /* replacement */
504: if (mode_from_str(opcstr+pos) == srcmode)
505: srcmode = mode_from_str(opcstr+pos+5);
506: else
507: goto nomatch;
508: pos += 10;
509: } else {
510: /* normal */
511: while(mode_from_str(opcstr+pos) != srcmode) {
512: pos += 4;
513: if (opcstr[pos] == ']')
514: goto nomatch;
515: pos++;
516: }
517: while(opcstr[pos] != ']') pos++;
518: pos++;
519: }
520: }
521: }
522: break;
523: default: abort();
524: }
525: /* safety check - might have changed */
526: if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
527: && srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
528: && srcmode != Apdi && srcmode != immi)
529: {
530: srcgather = 0;
531: }
1.1.1.12! root 532: if (srcmode == Areg && sz == sz_byte)
1.1 root 533: goto nomatch;
534:
535: if (opcstr[pos] != ',')
536: goto endofline;
537: pos++;
538:
539: /* parse the destination address */
540: usedst = 1;
541: switch (opcstr[pos++]) {
542: case 'D':
543: destmode = Dreg;
544: switch (opcstr[pos++]) {
545: case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
546: case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
547: default: abort();
548: }
1.1.1.3 root 549: if (dstpos < 0 || dstpos >= 32)
550: abort ();
1.1 root 551: break;
552: case 'A':
553: destmode = Areg;
554: switch (opcstr[pos++]) {
555: case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
556: case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
1.1.1.3 root 557: case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
1.1 root 558: default: abort();
559: }
1.1.1.3 root 560: if (dstpos < 0 || dstpos >= 32)
561: abort ();
1.1 root 562: switch (opcstr[pos]) {
563: case 'p': destmode = Apdi; pos++; break;
564: case 'P': destmode = Aipi; pos++; break;
565: }
566: break;
1.1.1.3 root 567: case 'L':
568: destmode = absl;
569: break;
1.1 root 570: case '#':
571: switch (opcstr[pos++]) {
572: case 'z': destmode = imm; break;
573: case '0': destmode = imm0; break;
574: case '1': destmode = imm1; break;
575: case '2': destmode = imm2; break;
576: case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break;
577: case 'j': destmode = immi; destreg = bitval[bitj]; break;
578: case 'J': destmode = immi; destreg = bitval[bitJ]; break;
579: case 'k': destmode = immi; destreg = bitval[bitk]; break;
580: case 'K': destmode = immi; destreg = bitval[bitK]; break;
581: default: abort();
582: }
583: break;
584: case 'd':
585: destreg = bitval[bitD];
586: destmode = mode_from_mr(bitval[bitd],bitval[bitD]);
587: if (destmode == am_illg)
588: continue;
589: if (CPU_EMU_SIZE < 1 &&
590: (destmode == Areg || destmode == Dreg || destmode == Aind
591: || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
592: || destmode == Apdi))
593: {
594: dstgather = 1; dstpos = bitpos[bitD];
595: }
596:
597: if (opcstr[pos] == '[') {
598: pos++;
599: if (opcstr[pos] == '!') {
600: /* exclusion */
601: do {
602: pos++;
603: if (mode_from_str(opcstr+pos) == destmode)
604: goto nomatch;
605: pos += 4;
606: } while (opcstr[pos] == ',');
607: pos++;
608: } else {
609: if (opcstr[pos+4] == '-') {
610: /* replacement */
611: if (mode_from_str(opcstr+pos) == destmode)
612: destmode = mode_from_str(opcstr+pos+5);
613: else
614: goto nomatch;
615: pos += 10;
616: } else {
617: /* normal */
618: while(mode_from_str(opcstr+pos) != destmode) {
619: pos += 4;
620: if (opcstr[pos] == ']')
621: goto nomatch;
622: pos++;
623: }
624: while(opcstr[pos] != ']') pos++;
625: pos++;
626: break;
627: }
628: }
629: }
630: /* Some addressing modes are invalid as destination */
631: if (destmode == imm || destmode == PC16 || destmode == PC8r)
632: goto nomatch;
633: break;
634: case 's':
635: destreg = bitval[bitS];
636: destmode = mode_from_mr(bitval[bits],bitval[bitS]);
637:
638: if (destmode == am_illg)
639: continue;
640: if (CPU_EMU_SIZE < 1 &&
641: (destmode == Areg || destmode == Dreg || destmode == Aind
642: || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
643: || destmode == Apdi))
644: {
645: dstgather = 1; dstpos = bitpos[bitS];
646: }
647:
648: if (opcstr[pos] == '[') {
649: pos++;
650: if (opcstr[pos] == '!') {
651: /* exclusion */
652: do {
653: pos++;
654: if (mode_from_str(opcstr+pos) == destmode)
655: goto nomatch;
656: pos += 4;
657: } while (opcstr[pos] == ',');
658: pos++;
659: } else {
660: if (opcstr[pos+4] == '-') {
661: /* replacement */
662: if (mode_from_str(opcstr+pos) == destmode)
663: destmode = mode_from_str(opcstr+pos+5);
664: else
665: goto nomatch;
666: pos += 10;
667: } else {
668: /* normal */
669: while(mode_from_str(opcstr+pos) != destmode) {
670: pos += 4;
671: if (opcstr[pos] == ']')
672: goto nomatch;
673: pos++;
674: }
675: while(opcstr[pos] != ']') pos++;
676: pos++;
677: }
678: }
679: }
680: break;
681: default: abort();
682: }
683: /* safety check - might have changed */
684: if (destmode != Areg && destmode != Dreg && destmode != Aind
685: && destmode != Ad16 && destmode != Ad8r && destmode != Aipi
686: && destmode != Apdi)
687: {
688: dstgather = 0;
689: }
690:
691: if (destmode == Areg && sz == sz_byte)
692: goto nomatch;
693: #if 0
694: if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
695: dstgather = 0;
696: }
697: #endif
698: endofline:
699: /* now, we have a match */
700: if (table68k[opc].mnemo != i_ILLG)
701: fprintf(stderr, "Double match: %x: %s\n", opc, opcstr);
702: if (find == -1) {
703: for (find = 0;; find++) {
704: if (strcmp(mnemonic, lookuptab[find].name) == 0) {
705: table68k[opc].mnemo = lookuptab[find].mnemo;
706: break;
707: }
708: if (strlen(lookuptab[find].name) == 0) abort();
709: }
710: }
711: else {
712: table68k[opc].mnemo = lookuptab[find].mnemo;
713: }
714: table68k[opc].cc = bitval[bitc];
715: if (table68k[opc].mnemo == i_BTST
716: || table68k[opc].mnemo == i_BSET
717: || table68k[opc].mnemo == i_BCLR
718: || table68k[opc].mnemo == i_BCHG)
719: {
720: sz = destmode == Dreg ? sz_long : sz_byte;
721: }
722: table68k[opc].size = sz;
723: table68k[opc].sreg = srcreg;
724: table68k[opc].dreg = destreg;
725: table68k[opc].smode = srcmode;
726: table68k[opc].dmode = destmode;
727: table68k[opc].spos = srcgather ? srcpos : -1;
728: table68k[opc].dpos = dstgather ? dstpos : -1;
729: table68k[opc].suse = usesrc;
730: table68k[opc].duse = usedst;
731: table68k[opc].stype = srctype;
732: table68k[opc].plev = id.plevel;
733: table68k[opc].clev = id.cpulevel;
734: #if 0
735: for (i = 0; i < 5; i++) {
736: table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
737: table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
738: }
739: #endif
740: table68k[opc].flagdead = flagdead;
741: table68k[opc].flaglive = flaglive;
1.1.1.3 root 742: table68k[opc].isjmp = isjmp;
743: nomatch:
1.1 root 744: /* FOO! */;
745: }
746: }
747:
748:
749: void read_table68k (void)
750: {
751: int i;
752:
753: table68k = (struct instr *)malloc (65536 * sizeof (struct instr));
754: for (i = 0; i < 65536; i++) {
755: table68k[i].mnemo = i_ILLG;
756: table68k[i].handler = -1;
757: }
758: for (i = 0; i < n_defs68k; i++) {
759: build_insn (i);
760: }
761: }
762:
763: static int mismatch;
764:
765: static void handle_merges (long int opcode)
766: {
767: uae_u16 smsk;
768: uae_u16 dmsk;
769: int sbitdst, dstend;
770: int srcreg, dstreg;
771:
772: if (table68k[opcode].spos == -1) {
773: sbitdst = 1; smsk = 0;
774: } else {
775: switch (table68k[opcode].stype) {
776: case 0:
777: smsk = 7; sbitdst = 8; break;
778: case 1:
779: smsk = 255; sbitdst = 256; break;
780: case 2:
781: smsk = 15; sbitdst = 16; break;
782: case 3:
783: smsk = 7; sbitdst = 8; break;
784: case 4:
785: smsk = 7; sbitdst = 8; break;
786: case 5:
787: smsk = 63; sbitdst = 64; break;
1.1.1.3 root 788: case 7:
789: smsk = 3; sbitdst = 4; break;
1.1 root 790: default:
791: smsk = 0; sbitdst = 0;
792: abort();
793: break;
794: }
795: smsk <<= table68k[opcode].spos;
796: }
797: if (table68k[opcode].dpos == -1) {
798: dstend = 1; dmsk = 0;
799: } else {
800: dmsk = 7 << table68k[opcode].dpos;
801: dstend = 8;
802: }
803: for (srcreg=0; srcreg < sbitdst; srcreg++) {
804: for (dstreg=0; dstreg < dstend; dstreg++) {
805: uae_u16 code = opcode;
806:
807: code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
808: code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
809:
810: /* Check whether this is in fact the same instruction.
811: * The instructions should never differ, except for the
812: * Bcc.(BW) case. */
813: if (table68k[code].mnemo != table68k[opcode].mnemo
814: || table68k[code].size != table68k[opcode].size
815: || table68k[code].suse != table68k[opcode].suse
816: || table68k[code].duse != table68k[opcode].duse)
817: {
818: mismatch++; continue;
819: }
820: if (table68k[opcode].suse
821: && (table68k[opcode].spos != table68k[code].spos
822: || table68k[opcode].smode != table68k[code].smode
823: || table68k[opcode].stype != table68k[code].stype))
824: {
825: mismatch++; continue;
826: }
827: if (table68k[opcode].duse
828: && (table68k[opcode].dpos != table68k[code].dpos
829: || table68k[opcode].dmode != table68k[code].dmode))
830: {
831: mismatch++; continue;
832: }
833:
834: if (code != opcode)
835: table68k[code].handler = opcode;
836: }
837: }
838: }
839:
840: void do_merges (void)
841: {
842: long int opcode;
843: int nr = 0;
844: mismatch = 0;
845: for (opcode = 0; opcode < 65536; opcode++) {
846: if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG)
847: continue;
848: nr++;
849: handle_merges (opcode);
850: }
851: nr_cpuop_funcs = nr;
852: }
853:
854: int get_no_mismatches (void)
855: {
856: return mismatch;
857: }
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