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1.1 root 1: /*
1.1.1.3 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * Read 68000 CPU specs from file "table68k"
5: *
6: * Copyright 1995,1996 Bernd Schmidt
1.1.1.3 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.8 root 13:
14:
15: /* 2008/04/26 [NP] Handle sz_byte for Areg as a valid srcmode if current instruction is a MOVE */
16: /* (e.g. move.b a1,(a0) ($1089)) (fix Blood Money on Superior 65) */
17:
18:
19:
1.1.1.9 ! root 20: const char ReadCpu_rcsid[] = "Hatari $Id: readcpu.c,v 1.9 2008-04-27 11:22:38 npomarede Exp $";
1.1 root 21:
22: #include <ctype.h>
1.1.1.2 root 23: #include <string.h>
24:
1.1 root 25: #include "readcpu.h"
26:
27: int nr_cpuop_funcs;
28:
1.1.1.6 root 29: const struct mnemolookup lookuptab[] = {
1.1 root 30: { i_ILLG, "ILLEGAL" },
31: { i_OR, "OR" },
32: { i_CHK, "CHK" },
33: { i_CHK2, "CHK2" },
34: { i_AND, "AND" },
35: { i_EOR, "EOR" },
36: { i_ORSR, "ORSR" },
37: { i_ANDSR, "ANDSR" },
38: { i_EORSR, "EORSR" },
39: { i_SUB, "SUB" },
40: { i_SUBA, "SUBA" },
41: { i_SUBX, "SUBX" },
42: { i_SBCD, "SBCD" },
43: { i_ADD, "ADD" },
44: { i_ADDA, "ADDA" },
45: { i_ADDX, "ADDX" },
46: { i_ABCD, "ABCD" },
47: { i_NEG, "NEG" },
48: { i_NEGX, "NEGX" },
49: { i_NBCD, "NBCD" },
50: { i_CLR, "CLR" },
51: { i_NOT, "NOT" },
52: { i_TST, "TST" },
53: { i_BTST, "BTST" },
54: { i_BCHG, "BCHG" },
55: { i_BCLR, "BCLR" },
56: { i_BSET, "BSET" },
57: { i_CMP, "CMP" },
58: { i_CMPM, "CMPM" },
59: { i_CMPA, "CMPA" },
60: { i_MVPRM, "MVPRM" },
61: { i_MVPMR, "MVPMR" },
62: { i_MOVE, "MOVE" },
63: { i_MOVEA, "MOVEA" },
64: { i_MVSR2, "MVSR2" },
65: { i_MV2SR, "MV2SR" },
66: { i_SWAP, "SWAP" },
67: { i_EXG, "EXG" },
68: { i_EXT, "EXT" },
69: { i_MVMEL, "MVMEL" },
70: { i_MVMLE, "MVMLE" },
71: { i_TRAP, "TRAP" },
72: { i_MVR2USP, "MVR2USP" },
73: { i_MVUSP2R, "MVUSP2R" },
74: { i_NOP, "NOP" },
75: { i_RESET, "RESET" },
76: { i_RTE, "RTE" },
77: { i_RTD, "RTD" },
78: { i_LINK, "LINK" },
79: { i_UNLK, "UNLK" },
80: { i_RTS, "RTS" },
81: { i_STOP, "STOP" },
82: { i_TRAPV, "TRAPV" },
83: { i_RTR, "RTR" },
84: { i_JSR, "JSR" },
85: { i_JMP, "JMP" },
86: { i_BSR, "BSR" },
87: { i_Bcc, "Bcc" },
88: { i_LEA, "LEA" },
89: { i_PEA, "PEA" },
90: { i_DBcc, "DBcc" },
91: { i_Scc, "Scc" },
92: { i_DIVU, "DIVU" },
93: { i_DIVS, "DIVS" },
94: { i_MULU, "MULU" },
95: { i_MULS, "MULS" },
96: { i_ASR, "ASR" },
97: { i_ASL, "ASL" },
98: { i_LSR, "LSR" },
99: { i_LSL, "LSL" },
100: { i_ROL, "ROL" },
101: { i_ROR, "ROR" },
102: { i_ROXL, "ROXL" },
103: { i_ROXR, "ROXR" },
104: { i_ASRW, "ASRW" },
105: { i_ASLW, "ASLW" },
106: { i_LSRW, "LSRW" },
107: { i_LSLW, "LSLW" },
108: { i_ROLW, "ROLW" },
109: { i_RORW, "RORW" },
110: { i_ROXLW, "ROXLW" },
111: { i_ROXRW, "ROXRW" },
112:
113: { i_MOVE2C, "MOVE2C" },
114: { i_MOVEC2, "MOVEC2" },
115: { i_CAS, "CAS" },
116: { i_CAS2, "CAS2" },
117: { i_MULL, "MULL" },
118: { i_DIVL, "DIVL" },
119: { i_BFTST, "BFTST" },
120: { i_BFEXTU, "BFEXTU" },
121: { i_BFCHG, "BFCHG" },
122: { i_BFEXTS, "BFEXTS" },
123: { i_BFCLR, "BFCLR" },
124: { i_BFFFO, "BFFFO" },
125: { i_BFSET, "BFSET" },
126: { i_BFINS, "BFINS" },
127: { i_PACK, "PACK" },
128: { i_UNPK, "UNPK" },
129: { i_TAS, "TAS" },
130: { i_BKPT, "BKPT" },
131: { i_CALLM, "CALLM" },
132: { i_RTM, "RTM" },
133: { i_TRAPcc, "TRAPcc" },
134: { i_MOVES, "MOVES" },
135: { i_FPP, "FPP" },
136: { i_FDBcc, "FDBcc" },
137: { i_FScc, "FScc" },
138: { i_FTRAPcc, "FTRAPcc" },
139: { i_FBcc, "FBcc" },
140: { i_FBcc, "FBcc" },
141: { i_FSAVE, "FSAVE" },
142: { i_FRESTORE, "FRESTORE" },
143:
144: { i_CINVL, "CINVL" },
145: { i_CINVP, "CINVP" },
146: { i_CINVA, "CINVA" },
147: { i_CPUSHL, "CPUSHL" },
148: { i_CPUSHP, "CPUSHP" },
149: { i_CPUSHA, "CPUSHA" },
150: { i_MOVE16, "MOVE16" },
151:
152: { i_MMUOP, "MMUOP" },
153: { i_ILLG, "" },
154: };
155:
156: struct instr *table68k;
157:
158: STATIC_INLINE amodes mode_from_str (const char *str)
159: {
160: if (strncmp (str, "Dreg", 4) == 0) return Dreg;
161: if (strncmp (str, "Areg", 4) == 0) return Areg;
162: if (strncmp (str, "Aind", 4) == 0) return Aind;
163: if (strncmp (str, "Apdi", 4) == 0) return Apdi;
164: if (strncmp (str, "Aipi", 4) == 0) return Aipi;
165: if (strncmp (str, "Ad16", 4) == 0) return Ad16;
166: if (strncmp (str, "Ad8r", 4) == 0) return Ad8r;
167: if (strncmp (str, "absw", 4) == 0) return absw;
168: if (strncmp (str, "absl", 4) == 0) return absl;
169: if (strncmp (str, "PC16", 4) == 0) return PC16;
170: if (strncmp (str, "PC8r", 4) == 0) return PC8r;
171: if (strncmp (str, "Immd", 4) == 0) return imm;
172: abort ();
173: return 0;
174: }
175:
176: STATIC_INLINE amodes mode_from_mr (int mode, int reg)
177: {
178: switch (mode) {
179: case 0: return Dreg;
180: case 1: return Areg;
181: case 2: return Aind;
182: case 3: return Aipi;
183: case 4: return Apdi;
184: case 5: return Ad16;
185: case 6: return Ad8r;
186: case 7:
187: switch (reg) {
188: case 0: return absw;
189: case 1: return absl;
190: case 2: return PC16;
191: case 3: return PC8r;
192: case 4: return imm;
193: case 5:
194: case 6:
195: case 7: return am_illg;
196: }
197: }
198: abort ();
199: return 0;
200: }
201:
202: static void build_insn (int insn)
203: {
204: int find = -1;
205: int variants;
1.1.1.3 root 206: int isjmp = 0;
1.1 root 207: struct instr_def id;
208: const char *opcstr;
1.1.1.5 root 209: int j;
1.1 root 210:
211: int flaglive = 0, flagdead = 0;
212:
213: id = defs68k[insn];
214:
1.1.1.3 root 215: /* Note: We treat anything with unknown flags as a jump. That
216: is overkill, but "the programmer" was lazy quite often, and
217: *this* programmer can't be bothered to work out what can and
218: can't trap. Usually, this will be overwritten with the gencomp
219: based information, anyway. */
220:
1.1.1.5 root 221: for (j = 0; j < 5; j++) {
222: switch (id.flaginfo[j].flagset){
1.1 root 223: case fa_unset: break;
1.1.1.3 root 224: case fa_isjmp: isjmp = 1; break;
225: case fa_isbranch: isjmp = 1; break;
1.1.1.5 root 226: case fa_zero: flagdead |= 1 << j; break;
227: case fa_one: flagdead |= 1 << j; break;
228: case fa_dontcare: flagdead |= 1 << j; break;
1.1.1.3 root 229: case fa_unknown: isjmp = 1; flagdead = -1; goto out1;
1.1.1.5 root 230: case fa_set: flagdead |= 1 << j; break;
1.1 root 231: }
232: }
233:
1.1.1.3 root 234: out1:
1.1.1.5 root 235: for (j = 0; j < 5; j++) {
236: switch (id.flaginfo[j].flaguse) {
1.1 root 237: case fu_unused: break;
1.1.1.5 root 238: case fu_isjmp: isjmp = 1; flaglive |= 1 << j; break;
239: case fu_maybecc: isjmp = 1; flaglive |= 1 << j; break;
240: case fu_unknown: isjmp = 1; flaglive |= 1 << j; break;
241: case fu_used: flaglive |= 1 << j; break;
1.1 root 242: }
243: }
244:
245: opcstr = id.opcstr;
246: for (variants = 0; variants < (1 << id.n_variable); variants++) {
247: int bitcnt[lastbit];
248: int bitval[lastbit];
249: int bitpos[lastbit];
250: int i;
251: uae_u16 opc = id.bits;
252: uae_u16 msk, vmsk;
253: int pos = 0;
254: int mnp = 0;
255: int bitno = 0;
256: char mnemonic[10];
257:
258: wordsizes sz = sz_long;
259: int srcgather = 0, dstgather = 0;
260: int usesrc = 0, usedst = 0;
261: int srctype = 0;
262: int srcpos = -1, dstpos = -1;
263:
264: amodes srcmode = am_unknown, destmode = am_unknown;
265: int srcreg = -1, destreg = -1;
266:
267: for (i = 0; i < lastbit; i++)
268: bitcnt[i] = bitval[i] = 0;
269:
270: vmsk = 1 << id.n_variable;
271:
272: for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {
273: if (!(msk & id.mask)) {
274: int currbit = id.bitpos[bitno++];
275: int bit_set;
276: vmsk >>= 1;
277: bit_set = variants & vmsk ? 1 : 0;
278: if (bit_set)
279: opc |= msk;
280: bitpos[currbit] = 15 - i;
281: bitcnt[currbit]++;
282: bitval[currbit] <<= 1;
283: bitval[currbit] |= bit_set;
284: }
285: }
286:
287: if (bitval[bitj] == 0) bitval[bitj] = 8;
288: /* first check whether this one does not match after all */
289: if (bitval[bitz] == 3 || bitval[bitC] == 1)
290: continue;
291: if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
292: continue;
293:
294: /* bitI and bitC get copied to biti and bitc */
295: if (bitcnt[bitI]) {
296: bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
297: }
298: if (bitcnt[bitC])
299: bitval[bitc] = bitval[bitC];
300:
301: pos = 0;
1.1.1.7 root 302: while (opcstr[pos] && !isspace((unsigned)opcstr[pos])) {
1.1 root 303: if (opcstr[pos] == '.') {
304: pos++;
305: switch (opcstr[pos]) {
306:
307: case 'B': sz = sz_byte; break;
308: case 'W': sz = sz_word; break;
309: case 'L': sz = sz_long; break;
310: case 'z':
311: switch (bitval[bitz]) {
312: case 0: sz = sz_byte; break;
313: case 1: sz = sz_word; break;
314: case 2: sz = sz_long; break;
315: default: abort();
316: }
317: break;
318: default: abort();
319: }
320: } else {
321: mnemonic[mnp] = opcstr[pos];
322: if (mnemonic[mnp] == 'f') {
323: find = -1;
324: switch (bitval[bitf]) {
325: case 0: mnemonic[mnp] = 'R'; break;
326: case 1: mnemonic[mnp] = 'L'; break;
327: default: abort();
328: }
329: }
330: mnp++;
331: }
332: pos++;
333: }
334: mnemonic[mnp] = 0;
335:
336: /* now, we have read the mnemonic and the size */
1.1.1.7 root 337: while (opcstr[pos] && isspace((unsigned)opcstr[pos]))
1.1 root 338: pos++;
339:
340: /* A goto a day keeps the D******a away. */
341: if (opcstr[pos] == 0)
342: goto endofline;
343:
344: /* parse the source address */
345: usesrc = 1;
346: switch (opcstr[pos++]) {
347: case 'D':
348: srcmode = Dreg;
349: switch (opcstr[pos++]) {
350: case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
351: case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
352: default: abort();
353: }
354:
355: break;
356: case 'A':
357: srcmode = Areg;
358: switch (opcstr[pos++]) {
359: case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
360: case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
361: default: abort();
362: }
363: switch (opcstr[pos]) {
364: case 'p': srcmode = Apdi; pos++; break;
365: case 'P': srcmode = Aipi; pos++; break;
366: }
367: break;
1.1.1.3 root 368: case 'L':
369: srcmode = absl;
370: break;
1.1 root 371: case '#':
372: switch (opcstr[pos++]) {
373: case 'z': srcmode = imm; break;
374: case '0': srcmode = imm0; break;
375: case '1': srcmode = imm1; break;
376: case '2': srcmode = imm2; break;
377: case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti];
378: if (CPU_EMU_SIZE < 4) {
379: /* Used for branch instructions */
380: srctype = 1;
381: srcgather = 1;
382: srcpos = bitpos[biti];
383: }
384: break;
385: case 'j': srcmode = immi; srcreg = bitval[bitj];
386: if (CPU_EMU_SIZE < 3) {
387: /* 1..8 for ADDQ/SUBQ and rotshi insns */
388: srcgather = 1;
389: srctype = 3;
390: srcpos = bitpos[bitj];
391: }
392: break;
393: case 'J': srcmode = immi; srcreg = bitval[bitJ];
394: if (CPU_EMU_SIZE < 5) {
395: /* 0..15 */
396: srcgather = 1;
397: srctype = 2;
398: srcpos = bitpos[bitJ];
399: }
400: break;
401: case 'k': srcmode = immi; srcreg = bitval[bitk];
402: if (CPU_EMU_SIZE < 3) {
403: srcgather = 1;
404: srctype = 4;
405: srcpos = bitpos[bitk];
406: }
407: break;
408: case 'K': srcmode = immi; srcreg = bitval[bitK];
409: if (CPU_EMU_SIZE < 5) {
410: /* 0..15 */
411: srcgather = 1;
412: srctype = 5;
413: srcpos = bitpos[bitK];
414: }
415: break;
1.1.1.3 root 416: case 'p': srcmode = immi; srcreg = bitval[bitK];
417: if (CPU_EMU_SIZE < 5) {
418: /* 0..3 */
419: srcgather = 1;
420: srctype = 7;
421: srcpos = bitpos[bitp];
422: }
423: break;
1.1 root 424: default: abort();
425: }
426: break;
427: case 'd':
428: srcreg = bitval[bitD];
429: srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);
430: if (srcmode == am_illg)
431: continue;
432: if (CPU_EMU_SIZE < 2 &&
433: (srcmode == Areg || srcmode == Dreg || srcmode == Aind
434: || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
435: || srcmode == Apdi))
436: {
437: srcgather = 1; srcpos = bitpos[bitD];
438: }
439: if (opcstr[pos] == '[') {
440: pos++;
441: if (opcstr[pos] == '!') {
442: /* exclusion */
443: do {
444: pos++;
445: if (mode_from_str(opcstr+pos) == srcmode)
446: goto nomatch;
447: pos += 4;
448: } while (opcstr[pos] == ',');
449: pos++;
450: } else {
451: if (opcstr[pos+4] == '-') {
452: /* replacement */
453: if (mode_from_str(opcstr+pos) == srcmode)
454: srcmode = mode_from_str(opcstr+pos+5);
455: else
456: goto nomatch;
457: pos += 10;
458: } else {
459: /* normal */
460: while(mode_from_str(opcstr+pos) != srcmode) {
461: pos += 4;
462: if (opcstr[pos] == ']')
463: goto nomatch;
464: pos++;
465: }
466: while(opcstr[pos] != ']') pos++;
467: pos++;
468: break;
469: }
470: }
471: }
472: /* Some addressing modes are invalid as destination */
473: if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
474: goto nomatch;
475: break;
476: case 's':
477: srcreg = bitval[bitS];
478: srcmode = mode_from_mr(bitval[bits],bitval[bitS]);
479:
480: if (srcmode == am_illg)
481: continue;
482: if (CPU_EMU_SIZE < 2 &&
483: (srcmode == Areg || srcmode == Dreg || srcmode == Aind
484: || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
485: || srcmode == Apdi))
486: {
487: srcgather = 1; srcpos = bitpos[bitS];
488: }
489: if (opcstr[pos] == '[') {
490: pos++;
491: if (opcstr[pos] == '!') {
492: /* exclusion */
493: do {
494: pos++;
495: if (mode_from_str(opcstr+pos) == srcmode)
496: goto nomatch;
497: pos += 4;
498: } while (opcstr[pos] == ',');
499: pos++;
500: } else {
501: if (opcstr[pos+4] == '-') {
502: /* replacement */
503: if (mode_from_str(opcstr+pos) == srcmode)
504: srcmode = mode_from_str(opcstr+pos+5);
505: else
506: goto nomatch;
507: pos += 10;
508: } else {
509: /* normal */
510: while(mode_from_str(opcstr+pos) != srcmode) {
511: pos += 4;
512: if (opcstr[pos] == ']')
513: goto nomatch;
514: pos++;
515: }
516: while(opcstr[pos] != ']') pos++;
517: pos++;
518: }
519: }
520: }
521: break;
522: default: abort();
523: }
524: /* safety check - might have changed */
525: if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
526: && srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
527: && srcmode != Apdi && srcmode != immi)
528: {
529: srcgather = 0;
530: }
1.1.1.8 root 531: // if (srcmode == Areg && sz == sz_byte)
532: if (srcmode == Areg && sz == sz_byte && strcmp ( mnemonic , "MOVE" ) != 0 ) // [NP] move.b is valid on 68000
1.1 root 533: goto nomatch;
534:
535: if (opcstr[pos] != ',')
536: goto endofline;
537: pos++;
538:
539: /* parse the destination address */
540: usedst = 1;
541: switch (opcstr[pos++]) {
542: case 'D':
543: destmode = Dreg;
544: switch (opcstr[pos++]) {
545: case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
546: case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
547: default: abort();
548: }
1.1.1.3 root 549: if (dstpos < 0 || dstpos >= 32)
550: abort ();
1.1 root 551: break;
552: case 'A':
553: destmode = Areg;
554: switch (opcstr[pos++]) {
555: case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
556: case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
1.1.1.3 root 557: case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
1.1 root 558: default: abort();
559: }
1.1.1.3 root 560: if (dstpos < 0 || dstpos >= 32)
561: abort ();
1.1 root 562: switch (opcstr[pos]) {
563: case 'p': destmode = Apdi; pos++; break;
564: case 'P': destmode = Aipi; pos++; break;
565: }
566: break;
1.1.1.3 root 567: case 'L':
568: destmode = absl;
569: break;
1.1 root 570: case '#':
571: switch (opcstr[pos++]) {
572: case 'z': destmode = imm; break;
573: case '0': destmode = imm0; break;
574: case '1': destmode = imm1; break;
575: case '2': destmode = imm2; break;
576: case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break;
577: case 'j': destmode = immi; destreg = bitval[bitj]; break;
578: case 'J': destmode = immi; destreg = bitval[bitJ]; break;
579: case 'k': destmode = immi; destreg = bitval[bitk]; break;
580: case 'K': destmode = immi; destreg = bitval[bitK]; break;
581: default: abort();
582: }
583: break;
584: case 'd':
585: destreg = bitval[bitD];
586: destmode = mode_from_mr(bitval[bitd],bitval[bitD]);
587: if (destmode == am_illg)
588: continue;
589: if (CPU_EMU_SIZE < 1 &&
590: (destmode == Areg || destmode == Dreg || destmode == Aind
591: || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
592: || destmode == Apdi))
593: {
594: dstgather = 1; dstpos = bitpos[bitD];
595: }
596:
597: if (opcstr[pos] == '[') {
598: pos++;
599: if (opcstr[pos] == '!') {
600: /* exclusion */
601: do {
602: pos++;
603: if (mode_from_str(opcstr+pos) == destmode)
604: goto nomatch;
605: pos += 4;
606: } while (opcstr[pos] == ',');
607: pos++;
608: } else {
609: if (opcstr[pos+4] == '-') {
610: /* replacement */
611: if (mode_from_str(opcstr+pos) == destmode)
612: destmode = mode_from_str(opcstr+pos+5);
613: else
614: goto nomatch;
615: pos += 10;
616: } else {
617: /* normal */
618: while(mode_from_str(opcstr+pos) != destmode) {
619: pos += 4;
620: if (opcstr[pos] == ']')
621: goto nomatch;
622: pos++;
623: }
624: while(opcstr[pos] != ']') pos++;
625: pos++;
626: break;
627: }
628: }
629: }
630: /* Some addressing modes are invalid as destination */
631: if (destmode == imm || destmode == PC16 || destmode == PC8r)
632: goto nomatch;
633: break;
634: case 's':
635: destreg = bitval[bitS];
636: destmode = mode_from_mr(bitval[bits],bitval[bitS]);
637:
638: if (destmode == am_illg)
639: continue;
640: if (CPU_EMU_SIZE < 1 &&
641: (destmode == Areg || destmode == Dreg || destmode == Aind
642: || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
643: || destmode == Apdi))
644: {
645: dstgather = 1; dstpos = bitpos[bitS];
646: }
647:
648: if (opcstr[pos] == '[') {
649: pos++;
650: if (opcstr[pos] == '!') {
651: /* exclusion */
652: do {
653: pos++;
654: if (mode_from_str(opcstr+pos) == destmode)
655: goto nomatch;
656: pos += 4;
657: } while (opcstr[pos] == ',');
658: pos++;
659: } else {
660: if (opcstr[pos+4] == '-') {
661: /* replacement */
662: if (mode_from_str(opcstr+pos) == destmode)
663: destmode = mode_from_str(opcstr+pos+5);
664: else
665: goto nomatch;
666: pos += 10;
667: } else {
668: /* normal */
669: while(mode_from_str(opcstr+pos) != destmode) {
670: pos += 4;
671: if (opcstr[pos] == ']')
672: goto nomatch;
673: pos++;
674: }
675: while(opcstr[pos] != ']') pos++;
676: pos++;
677: }
678: }
679: }
680: break;
681: default: abort();
682: }
683: /* safety check - might have changed */
684: if (destmode != Areg && destmode != Dreg && destmode != Aind
685: && destmode != Ad16 && destmode != Ad8r && destmode != Aipi
686: && destmode != Apdi)
687: {
688: dstgather = 0;
689: }
690:
691: if (destmode == Areg && sz == sz_byte)
692: goto nomatch;
693: #if 0
694: if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
695: dstgather = 0;
696: }
697: #endif
698: endofline:
699: /* now, we have a match */
700: if (table68k[opc].mnemo != i_ILLG)
701: fprintf(stderr, "Double match: %x: %s\n", opc, opcstr);
702: if (find == -1) {
703: for (find = 0;; find++) {
704: if (strcmp(mnemonic, lookuptab[find].name) == 0) {
705: table68k[opc].mnemo = lookuptab[find].mnemo;
706: break;
707: }
708: if (strlen(lookuptab[find].name) == 0) abort();
709: }
710: }
711: else {
712: table68k[opc].mnemo = lookuptab[find].mnemo;
713: }
714: table68k[opc].cc = bitval[bitc];
715: if (table68k[opc].mnemo == i_BTST
716: || table68k[opc].mnemo == i_BSET
717: || table68k[opc].mnemo == i_BCLR
718: || table68k[opc].mnemo == i_BCHG)
719: {
720: sz = destmode == Dreg ? sz_long : sz_byte;
721: }
722: table68k[opc].size = sz;
723: table68k[opc].sreg = srcreg;
724: table68k[opc].dreg = destreg;
725: table68k[opc].smode = srcmode;
726: table68k[opc].dmode = destmode;
727: table68k[opc].spos = srcgather ? srcpos : -1;
728: table68k[opc].dpos = dstgather ? dstpos : -1;
729: table68k[opc].suse = usesrc;
730: table68k[opc].duse = usedst;
731: table68k[opc].stype = srctype;
732: table68k[opc].plev = id.plevel;
733: table68k[opc].clev = id.cpulevel;
734: #if 0
735: for (i = 0; i < 5; i++) {
736: table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
737: table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
738: }
739: #endif
740: table68k[opc].flagdead = flagdead;
741: table68k[opc].flaglive = flaglive;
1.1.1.3 root 742: table68k[opc].isjmp = isjmp;
743: nomatch:
1.1 root 744: /* FOO! */;
745: }
746: }
747:
748:
749: void read_table68k (void)
750: {
751: int i;
752:
753: table68k = (struct instr *)malloc (65536 * sizeof (struct instr));
754: for (i = 0; i < 65536; i++) {
755: table68k[i].mnemo = i_ILLG;
756: table68k[i].handler = -1;
757: }
758: for (i = 0; i < n_defs68k; i++) {
759: build_insn (i);
760: }
761: }
762:
763: static int mismatch;
764:
765: static void handle_merges (long int opcode)
766: {
767: uae_u16 smsk;
768: uae_u16 dmsk;
769: int sbitdst, dstend;
770: int srcreg, dstreg;
771:
772: if (table68k[opcode].spos == -1) {
773: sbitdst = 1; smsk = 0;
774: } else {
775: switch (table68k[opcode].stype) {
776: case 0:
777: smsk = 7; sbitdst = 8; break;
778: case 1:
779: smsk = 255; sbitdst = 256; break;
780: case 2:
781: smsk = 15; sbitdst = 16; break;
782: case 3:
783: smsk = 7; sbitdst = 8; break;
784: case 4:
785: smsk = 7; sbitdst = 8; break;
786: case 5:
787: smsk = 63; sbitdst = 64; break;
1.1.1.3 root 788: case 7:
789: smsk = 3; sbitdst = 4; break;
1.1 root 790: default:
791: smsk = 0; sbitdst = 0;
792: abort();
793: break;
794: }
795: smsk <<= table68k[opcode].spos;
796: }
797: if (table68k[opcode].dpos == -1) {
798: dstend = 1; dmsk = 0;
799: } else {
800: dmsk = 7 << table68k[opcode].dpos;
801: dstend = 8;
802: }
803: for (srcreg=0; srcreg < sbitdst; srcreg++) {
804: for (dstreg=0; dstreg < dstend; dstreg++) {
805: uae_u16 code = opcode;
806:
807: code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
808: code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
809:
810: /* Check whether this is in fact the same instruction.
811: * The instructions should never differ, except for the
812: * Bcc.(BW) case. */
813: if (table68k[code].mnemo != table68k[opcode].mnemo
814: || table68k[code].size != table68k[opcode].size
815: || table68k[code].suse != table68k[opcode].suse
816: || table68k[code].duse != table68k[opcode].duse)
817: {
818: mismatch++; continue;
819: }
820: if (table68k[opcode].suse
821: && (table68k[opcode].spos != table68k[code].spos
822: || table68k[opcode].smode != table68k[code].smode
823: || table68k[opcode].stype != table68k[code].stype))
824: {
825: mismatch++; continue;
826: }
827: if (table68k[opcode].duse
828: && (table68k[opcode].dpos != table68k[code].dpos
829: || table68k[opcode].dmode != table68k[code].dmode))
830: {
831: mismatch++; continue;
832: }
833:
834: if (code != opcode)
835: table68k[code].handler = opcode;
836: }
837: }
838: }
839:
840: void do_merges (void)
841: {
842: long int opcode;
843: int nr = 0;
844: mismatch = 0;
845: for (opcode = 0; opcode < 65536; opcode++) {
846: if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG)
847: continue;
848: nr++;
849: handle_merges (opcode);
850: }
851: nr_cpuop_funcs = nr;
852: }
853:
854: int get_no_mismatches (void)
855: {
856: return mismatch;
857: }
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