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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /**
26: * Copyright (c) 1994-1996 NeXT Software, Inc. All rights reserved.
27: * Copyright 1993-1995 by Apple Computer, Inc., all rights reserved.
28: * Copyright 1997 Apple Computer Inc. All Rights Reserved.
29: * @author Martin Minow mailto:[email protected]
30: * @revision 1997.02.13 Initial conversion from AMDPCSCSIDriver sources.
31: *
32: * Set tabs every 4 characters.
33: *
34: * Apple96Curio.h - Hardware (chip) definitions for Apple 53c96 SCSI interface.
35: * Apple96SCSI is closely based on Doug Mitchell's AMD 53C974/79C974 driver
36: * using design concepts from Copland DR2 Curio and MESH SCSI plugins.
37: *
38: * Edit History
39: * 1997.02.13 MM Initial conversion from AMDPCSCSIDriver sources.
40: */
41:
42: #import "Apple96SCSI.h"
43: /*
44: * Define offsets into the SCSI 53c96 chip. Use the READ_REG and WRITE_REG
45: * macros to access the chip.
46: */
47: typedef enum {
48: rXCL = 0x00, /* Transfer counter LSB (r/w) */
49: rXCM = 0x10, /* Transfer counter MSB (r/w) */
50: rFFO = 0x20, /* Fifo (r/w) */
51: rCMD = 0x30, /* Command (r/w) */
52: rSTA = 0x40, /* Status (r) or Destination bus ID (w) */
53: rINT = 0x50, /* Interrupt (r) or Select/reselect timeout (w) */
54: rSQS = 0x60, /* Sequence step (r) or Synch Period (w) */
55: rFOS = 0x70, /* FIFO Flags/Sequence Step (r) or Sync Offset (w) */
56: rCF1 = 0x80, /* Configuration 1 (r/w) */
57: rCKF = 0x90, /* Clock Conversion Factor (w) */
58: rTST = 0xA0, /* Test (w) */
59: rCF2 = 0xB0, /* Configuration 2 (r/w) */
60: rCF3 = 0xC0, /* Configuration 3 (r/w) */
61: rCF4 = 0xD0, /* Configuration 4 (r/w) */
62: rTCH = 0xE0, /* Transfer counter high/ID (r/w) */
63: rDMA = 0xF0 /* Pseudo-DMA (r/w) */
64: } CurioChipRegisters;
65:
66: /*
67: * SCSI 53C96 (ASC) Command Set
68: */
69: enum {
70: cNOP = 0x00, /* NOP command */
71: cFlshFFO = 0x01, /* flush FIFO command */
72: cRstSChp = 0x02, /* reset SCSI chip */
73: cRstSBus = 0x03, /* reset SCSI bus */
74:
75: cIOXfer = 0x10, /* non-DMA Transfer command */
76: cCmdComp = 0x11, /* Initiator Command Complete Seq */
77: cMsgAcep = 0x12, /* Message Accepted */
78: cXferPad = 0x18, /* Transfer pad */
79: cDisconnect = 0x23, /* Disconnect from the SCSI bus */
80: cSlctNoAtn = 0x41, /* Select Without ATN Sequence */
81: cSlctAtn = 0x42, /* Select With ATN Sequence */
82: cSlctAtnStp = 0x43, /* Select With ATN and Stop Seq */
83: cEnSelResel = 0x44, /* Enable Selection/Reselection */
84: cDsSelResel = 0x45, /* Disable Selection/Reselection */
85: cSlctAtn3 = 0x46, /* Select with ATN, send 3 byte msg */
86:
87: cSetAtn = 0x1A, /* Set ATN command */
88: cRstAtn = 0x1B, /* Reset ATN command */
89:
90: bDMDEnBit = 0x80, /* Enable bit for DMA commands */
91: bDscCmdState = 0x40, /* Disconnected State Group Cmd's */
92:
93: cDMAXfer = ( bDMDEnBit | cIOXfer ), /* DMA Transfer Cmd */
94: cDMAXferPad = ( bDMDEnBit | cXferPad ), /* DMA Transfer Pad */
95: cDMASelWOAtn = ( bDMDEnBit | cSlctNoAtn ), /* Sel w/o ATN + DMA */
96: cDMASelWAtn = ( bDMDEnBit | cSlctAtn ) /* Sel With ATN use DMA */
97: };
98:
99: /*
100: * SCSI 53C95 (ASC) Bit Definitions.
101: * Note: these are duplicated so I don't have to retype the entire
102: * state machine.
103: */
104:
105: /*
106: * Bits in the Interrupt (rINT) register.
107: */
108: enum {
109: iSelected = 0x01, /* selected bit */
110: iSelectWAtn = 0x02, /* selected w/ ATN bit */
111: iReselected = 0x04, /* reselected bit */
112: iFuncComp = 0x08, /* function complete bit */
113: iBusService = 0x10, /* bus service bit */
114: iDisconnect = 0x20, /* disconnected bit */
115: iIlegalCmd = 0x40, /* illegal command bit */
116: iResetDetect = 0x80 /* SCSI reset detected bit */
117: };
118: //enum { /* As used in AppleChip.m */
119: // IS_SCSIRESET = iResetDetect,
120: // IS_ILLEGALCMD = iIlegalCmd,
121: // IS_DISCONNECT = iDisconnect,
122: // IS_SERVICE_REQ = iBusService,
123: // IS_SUCCESSFUL_OP = iFuncComp,
124: // IS_RESELECTED = iReselected,
125: // IS_SELECT_ATN = iSelectWAtn,
126: // IS_SELECTED = iSelected
127: //};
128:
129: /*
130: * Bits in the Status (rSTA) register.
131: */
132: enum {
133: sIO = 0x01, /* I/O bit */
134: sCD = 0x02, /* C/D bit */
135: sMsg = 0x04, /* MSG bit */
136: sCmdComp = 0x08, /* function complete bit */
137: sTermCount = 0x10, /* bus service bit */
138: sParityErr = 0x20, /* disconnected bit */
139: sGrossErr = 0x40, /* illegal command bit */
140: sIntPend = 0x80, /* SCSI interrupt pending */
141: mPhase = (sIO | sCD | sMsg), /* the phase bitmask */
142: sTCIntPend = (sTermCount | sIntPend) /* TC int pending */
143: };
144: enum { /* As used in AppleChip.m */
145: SS_INTERRUPT = sIntPend,
146: // SS_ILLEGALOP = sGrossErr,
147: SS_PARITYERROR = sParityErr,
148: SS_COUNTZERO = sTermCount,
149: // SS_PHASEMASK = mPhase
150: };
151:
152: /*
153: * Bits in the FIFO Count/Sequence Step (rFOS) register.
154: */
155: enum {
156: kFIFOCountMask = 0x1F, /* mask to get FIFO count */
157: mSeqStep = 0xE0 /* mask to get sequence step */
158: };
159: /*
160: * internal state register (internState)
161: * Hmm: I'm not sure if these exist on the Curio.
162: */
163: #define INS_SYNC_FULL 0x10 // sync offset buffer full
164: #define INS_STATE_MASK 0x07
165:
166: /*
167: * Clock Conversion Values (based on SCSI chip clock - not CPU clock)
168: */
169: enum {
170: ccf10MHz = 0x02, /* CLK conv factor 10.0Mhz */
171: ccf11to15MHz = 0x03, /* CLK conv factor 10.01 to 15.0Mhz */
172: ccf16to20MHz = 0x04, /* CLK conv factor 15.01 to 20.0Mhz */
173: ccf21to25MHz = 0x05, /* CLK conv factor 20.01 to 25.0Mhz */
174: ccf26to30MHz = 0x06, /* CLK conv factor 25.01 to 30.0Mhz */
175: ccf31to35MHz = 0x07, /* CLK conv factor 30.01 to 35.0Mhz */
176: ccf36to40MHz = 0x00 /* CLK conv factor 35.01 to 40.0Mhz (0 <- 8) */
177: };
178:
179: /*
180: * Select timeout values (these are the values stored in the chip register).
181: * The "Mhz" value is the SCSI bus speed, returned by the Registry.
182: */
183: enum {
184: SelTO16Mhz = 126, /* (0x7e) using the formula: RV (regr value) */
185: /* 126 = (16MHz * 250mS)/ (7682 * 4) */
186: /* 250mS is ANSI standard. */
187: SelTO25Mhz = 167, /* (0xa7) using the formula: RV (regr value) */
188: /* 163 = (25MHz * 250mS)/ (7682 * 5) */
189: /* 250mS is ANSI standard. */
190: SelTO33Mhz = 167, /* (0xa7) using the formula: RV (regr value) */
191: /* 153 = (33MHz * 250mS)/ (7682 * 7) */
192: /* 250mS is ANSI standard. */
193: SelTO40Mhz = 167 /* (0xa7) using the formula: RV (regr value) */
194: /* 163 = (40MHz * 250mS)/ (7682 * 8) */
195: /* 250mS is ANSI standard. */
196: };
197:
198: /*
199: * Configuration Register 1 bit definition
200: */
201: enum {
202: CF1_SLOW = 0x80, /* Slow Cable Mode enabled bit */
203: CF1_SRD = 0x40, /* SCSI Reset Reporting Intrp Disabled bit */
204: CF1_PTEST = 0x20, /* Parity Test Mode bit */
205: CF1_ENABPAR = 0x10, /* Enable Parity Checking bit */
206: CF1_CHIPTEST = 0x08, /* Enable Chip Test Mode bit */
207: CF1_DEFAULT_ID_MASK = 0x07 /* The default host SCSI ID mask. */
208: };
209:
210: /*
211: * Configuration Register 2 bit definition
212: */
213: enum {
214: CF2_RFB = 0x80, /* Reserve FIFO Byte */
215: CF2_ENFEATURES = 0x40, /* Enable features */
216: CF2_EBC = 0x20, /* Enable Byte Control */
217: CF2_DREQHIZ = 0x10, /* Force DREQ to HI-Z state */
218: CF2_SCSI2 = 0x08, /* SCSI-2 features */
219: CF2_BPA = 0x04, /* Target:bad parity abort */
220: CF2_RPE = 0x02, /* Rregister parity enable */
221: CF2_DPE = 0x01 /* DMA parity enable */
222: };
223:
224: /*
225: * Configuration Register 3 bit definition
226: */
227: enum {
228: CF3_MSGID = 0x80, /* Check for valid ID message */
229: CF3_QTAG = 0x40, /* Enable 3 byte QTAG messages */
230: CF3_CDB10 = 0x20, /* Recognize 10 bytes CDBs */
231: CF3_FASTCLOCK = 0x10, /* Enable fast clock for fast SCSI */
232: CF3_FASTSCSI = 0x08, /* Enable fast SCSI */
233: CF3_SRB = 0x04, /* Save residual byte */
234: CF3_ALTDMA = 0x02, /* Alternate DMA (for threshold 8 only) */
235: CF3_T8 = 0x01, /* Force 8-byte DMA caching */
236: CONFIG_FOR_DMA = (CF3_SRB | CF3_ALTDMA | CF3_T8),
237: CONFIG_FOR_NON_DMA = (CF3_SRB)
238: };
239:
240: /*
241: * Configuration Register 4 bit definitions.
242: */
243: enum {
244: CF4_ACTIVENEGATION = 0x04,
245: CF4_TRANSFERCOUNTTEST = 0x02,
246: CF4_BACKTOBACK = 0x01
247: };
248:
249: /*
250: * Miscellaneous Defines.
251: */
252: enum {
253: kDefaultInitiatorID = 7, /* SCSI Bus Initiator ID */
254: /*
255: * The maximum transfer size is set *below* the absolute max of 65536 to avoid
256: * the problem of understanding the value zero, which means either 65536 bytes
257: * or zero bytes remaining to transfer.
258: */
259: kMaxC96TransferSize = (65536 - 4096),
260: // ** ** ** NEED VALUE
261: kChipFastBusClockMHz = 00, /* Fast bus clock rate */
262: kChipDefaultBusClockMHz = 25 /* Default 53c96 clock rate in MHz */
263: };
264:
265: enum { /* Values for SyncParms MESH register: */
266: /* 1st nibble is offset, 2nd is period. */
267: /* Zero offset means async. */
268: /* Note: the external bus does not support */
269: /* either fast or synchronous modes, so the */
270: /* following definitions are irrelevant. */
271: /* However, they will be necessary for the */
272: /* internal bus on the PowerMac 8100 */
273: kSyncParmsNone = 0x00, /* No synchronous negotiation needed */
274: kSyncParmsAsync = 0x02, /* Async with min period = 2 */
275: kSyncParmsFast = 0xF0 /* offset = 15, period = Fast (10 MB/s) */
276: };
277:
278: /*
279: * DMA alignment requirements.
280: */
281: enum {
282: AMIC_ReadStartAlignment = 8,
283: AMIC_WriteStartAlighment = 8,
284: AMIC_ReadLengthAlignment = 0,
285: AMIC_WriteLengthAlignment = 0,
286: DBDMA_ReadStartAlignment = 0,
287: DBDMA_WriteStartAlignment = 0,
288: DBDMA_ReadLengthAlignment = 0,
289: DBDMA_WriteLengthAlignment = 0
290: };
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