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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /**
26: * Copyright (c) 1994-1996 NeXT Software, Inc. All rights reserved.
27: * Copyright 1997 Apple Computer Inc. All Rights Reserved.
28: * @author Martin Minow mailto:[email protected]
29: * @revision 1997.02.13 Initial conversion from AMDPCSCSIDriver sources.
30: *
31: * Set tabs every 4 characters.
32: *
33: * Apple96PCIDBDMA.h - Minimal DBDMA Handler for the Apple 96 PCI driver. This is
34: * a temporary file until "real" DBDMA support appears.
35: *
36: * Edit History
37: * 1997.02.13 MM Initial conversion from AMDPCSCSIDriver sources.
38: */
39:
40: #import "Apple96SCSI.h"
41:
42: /**
43: * Copyright 1984-1997 Apple Computer Inc. All Rights Reserved.
44: * @author Martin Minow mailto:[email protected]
45: * @revision 1997.02.13 Initial conversion from Copland D12 DBDMA.Rev 9 sources.
46: *
47: * Set tabs every 4 characters.
48: *
49: * AppleDBDMADefinitions.h - registers and inline functions for the DBDMA memory controller.
50: *
51: * Edit History
52: * 1997.02.13 MM Initial conversion from AMDPCSCSIDriver sources.
53: */
54:
55: /*
56: * The class must provide the following instance or local variable:
57: * DBDMAInfoRecord gDBDMAInfoRecord
58: */
59: /*
60: This structure defines the DB-DMA channel command descriptor.
61: *** WARNING: Endian-ness issues must be considered when performing load/store! ***
62: *** DB-DMA specifies memory organization as quadlets so it is not correct
63: *** to think of either the operation or result field as two 16-bit fields.
64: *** This would have undesirable effects on the byte ordering within their
65: *** respective quadlets. Use the accessor macros provided below.
66: */
67: struct DBDMADescriptor {
68: unsigned long operation; /* cmd || key || i || b || w || reqCount*/
69: unsigned long address;
70: unsigned long cmdDep;
71: unsigned long result; /* xferStatus || resCount*/
72: };
73: typedef struct DBDMADescriptor DBDMADescriptor;
74:
75: typedef DBDMADescriptor *DBDMADescriptorPtr;
76:
77:
78: /* This structure defines the standard set of DB-DMA channel registers.*/
79: /** ** ** ** Shouldn't these be marked volatile ** ** ** **/
80: struct DBDMAChannelRegisters {
81: unsigned long channelControl;
82: unsigned long channelStatus;
83: unsigned long commandPtrHi; /* implementation optional*/
84: unsigned long commandPtrLo;
85: unsigned long interruptSelect; /* implementation optional*/
86: unsigned long branchSelect; /* implementation optional*/
87: unsigned long waitSelect; /* implementation optional*/
88: unsigned long transferModes; /* implementation optional*/
89: unsigned long data2PtrHi; /* implementation optional*/
90: unsigned long data2PtrLo; /* implementation optional*/
91:
92: unsigned long reserved1;
93: unsigned long addressHi; /* implementation optional*/
94: unsigned long reserved2[4];
95: unsigned long unimplemented[16];
96:
97: /* This structure must remain fully padded to 256 bytes.*/
98: unsigned long undefined[32];
99: };
100: typedef struct DBDMAChannelRegisters DBDMAChannelRegisters;
101:
102: /* These constants define the DB-DMA channel control words and status flags.*/
103:
104: enum {
105: kdbdmaSetRun = 0x80008000,
106: kdbdmaClrRun = 0x80000000,
107: kdbdmaSetPause = 0x40004000,
108: kdbdmaClrPause = 0x40000000,
109: kdbdmaSetFlush = 0x20002000,
110: kdbdmaSetWake = 0x10001000,
111: kdbdmaClrDead = 0x08000000,
112: kdbdmaSetS7 = 0x00800080,
113: kdbdmaClrS7 = 0x00800000,
114: kdbdmaSetS6 = 0x00400040,
115: kdbdmaClrS6 = 0x00400000,
116: kdbdmaSetS5 = 0x00200020,
117: kdbdmaClrS5 = 0x00200000,
118: kdbdmaSetS4 = 0x00100010,
119: kdbdmaClrS4 = 0x00100000,
120: kdbdmaSetS3 = 0x00080008,
121: kdbdmaClrS3 = 0x00080000,
122: kdbdmaSetS2 = 0x00040004,
123: kdbdmaClrS2 = 0x00040000,
124: kdbdmaSetS1 = 0x00020002,
125: kdbdmaClrS1 = 0x00020000,
126: kdbdmaSetS0 = 0x00010001,
127: kdbdmaClrS0 = 0x00010000,
128: kdbdmaClrAll = 0xFFFF0000
129: };
130:
131:
132: enum {
133: kdbdmaRun = 0x00008000,
134: kdbdmaPause = 0x00004000,
135: kdbdmaFlush = 0x00002000,
136: kdbdmaWake = 0x00001000,
137: kdbdmaDead = 0x00000800,
138: kdbdmaActive = 0x00000400,
139: kdbdmaBt = 0x00000100,
140: kdbdmaS7 = 0x00000080,
141: kdbdmaS6 = 0x00000040,
142: kdbdmaS5 = 0x00000020,
143: kdbdmaS4 = 0x00000010,
144: kdbdmaS3 = 0x00000008,
145: kdbdmaS2 = 0x00000004,
146: kdbdmaS1 = 0x00000002,
147: kdbdmaS0 = 0x00000001
148: };
149:
150: /* These constants define the DB-DMA channel command operations and modifiers.*/
151:
152: enum {
153: /* Command.cmd operations*/
154: OUTPUT_MORE = 0x00000000,
155: OUTPUT_LAST = 0x10000000,
156: INPUT_MORE = 0x20000000,
157: INPUT_LAST = 0x30000000,
158: STORE_QUAD = 0x40000000,
159: LOAD_QUAD = 0x50000000,
160: NOP_CMD = 0x60000000,
161: STOP_CMD = 0x70000000,
162: kdbdmaCmdMask = 0xF0000000
163: };
164:
165:
166: enum {
167: /* Command.key modifiers (choose one for INPUT, OUTPUT, LOAD, and STORE)*/
168: KEY_STREAM0 = 0x00000000, /* default modifier*/
169: KEY_STREAM1 = 0x01000000,
170: KEY_STREAM2 = 0x02000000,
171: KEY_STREAM3 = 0x03000000,
172: KEY_REGS = 0x05000000,
173: KEY_SYSTEM = 0x06000000,
174: KEY_DEVICE = 0x07000000,
175: kdbdmaKeyMask = 0x07000000, /* Command.i modifiers (choose one for INPUT, OUTPUT, LOAD, STORE, and NOP)*/
176: kIntNever = 0x00000000, /* default modifier*/
177: kIntIfTrue = 0x00100000,
178: kIntIfFalse = 0x00200000,
179: kIntAlways = 0x00300000,
180: kdbdmaIMask = 0x00300000, /* Command.b modifiers (choose one for INPUT, OUTPUT, and NOP)*/
181: kBranchNever = 0x00000000, /* default modifier*/
182: kBranchIfTrue = 0x00040000,
183: kBranchIfFalse = 0x00080000,
184: kBranchAlways = 0x000C0000,
185: kdbdmaBMask = 0x000C0000, /* Command.w modifiers (choose one for INPUT, OUTPUT, LOAD, STORE, and NOP)*/
186: kWaitNever = 0x00000000, /* default modifier*/
187: kWaitIfTrue = 0x00010000,
188: kWaitIfFalse = 0x00020000,
189: kWaitAlways = 0x00030000,
190: kdbdmaWMask = 0x00030000, /* operation masks*/
191: kdbdmaCommandMask = 0xFFFF0000,
192: kdbdmaReqCountMask = 0x0000FFFF
193: };
194:
195: /* These constants define the DB-DMA channel command results.*/
196:
197: enum {
198: kXferStatusRun = kdbdmaRun << 16,
199: kXferStatusPause = kdbdmaPause << 16,
200: kXferStatusFlush = kdbdmaFlush << 16,
201: kXferStatusWake = kdbdmaWake << 16,
202: kXferStatusDead = kdbdmaDead << 16,
203: kXferStatusActive = kdbdmaActive << 16,
204: kXferStatusBt = kdbdmaBt << 16,
205: kXferStatusS7 = kdbdmaS7 << 16,
206: kXferStatusS6 = kdbdmaS6 << 16,
207: kXferStatusS5 = kdbdmaS5 << 16,
208: kXferStatusS4 = kdbdmaS4 << 16,
209: kXferStatusS3 = kdbdmaS3 << 16,
210: kXferStatusS2 = kdbdmaS2 << 16,
211: kXferStatusS1 = kdbdmaS1 << 16,
212: kXferStatusS0 = kdbdmaS0 << 16, /* result masks*/
213: kdbdmaResCountMask = 0x0000FFFF,
214: kdbdmaXferStatusMask = kdbdmaResCountMask << 16
215: };
216:
217:
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