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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Copyright (c) 1998-1999 by Apple Computer, Inc., All rights reserved.
27: *
28: * MII protocol and PHY register definitions.
29: *
30: * HISTORY
31: *
32: */
33:
34: /*
35: * MII command frame (32-bits) as documented in IEEE 802.3u
36: */
37: #ifdef ppc
38: #define _BIG_ENDIAN
39: #endif
40:
41: typedef union {
42: unsigned int data;
43: #ifdef _BIG_ENDIAN
44: struct {
45: unsigned int
46: st:2, // start of frame
47: #define MII_ST 0x01
48: op:2, // operation code
49: #define MII_OP_READ 0x02
50: #define MII_OP_WRITE 0x01
51: phyad:5, // PHY address
52: regad:5, // register address
53: ta:2, // turnaround
54: data:16; // 16-bit data field
55: } bit;
56: #else _BIG_ENDIAN
57: struct {
58: unsigned int
59: data:16, // 16-bit data field
60: ta:2, // turnaround
61: regad:5, // register address
62: phyad:5, // PHY address
63: op:2, // operation code
64: st:2; // start of frame
65: } bit;
66: #endif _BIG_ENDIAN
67: } miiFrameUnion;
68:
69: #define MII_FRAME_PREAMBLE 0xFFFFFFFF
70: #define MII_FRAME_SIZE 32
71: #define MII_FRAME_READ 0x60000000
72: #define MII_FRAME_WRITE 0x50020000
73:
74: #define MII_MAX_PHY 32
75:
76: /* MII Registers */
77: #define MII_CONTROL 0
78: #define MII_STATUS 1
79: #define MII_ID0 2
80: #define MII_ID1 3
81: #define MII_ADVERTISEMENT 4
82: #define MII_LINKPARTNER 5
83: #define MII_EXPANSION 6
84: #define MII_NEXTPAGE 7
85:
86: /* MII Control register bits */
87: #define MII_CONTROL_RESET 0x8000
88: #define MII_CONTROL_LOOPBACK 0x4000
89: #define MII_CONTROL_SPEED_SELECTION 0x2000
90: #define MII_CONTROL_AUTONEGOTIATION 0x1000
91: #define MII_CONTROL_POWERDOWN 0x800
92: #define MII_CONTROL_ISOLATE 0x400
93: #define MII_CONTROL_RESTART_NEGOTIATION 0x200
94: #define MII_CONTROL_FULLDUPLEX 0x100
95: #define MII_CONTROL_COLLISION_TEST 0x80
96:
97: /* MII Status register bits */
98: #define MII_STATUS_100BASET4 0x8000
99: #define MII_STATUS_100BASETX_FD 0x4000
100: #define MII_STATUS_100BASETX 0x2000
101: #define MII_STATUS_10BASET_FD 0x1000
102: #define MII_STATUS_10BASET 0x800
103: #define MII_STATUS_NEGOTIATION_COMPLETE 0x20
104: #define MII_STATUS_REMOTE_FAULT 0x10
105: #define MII_STATUS_NEGOTIATION_ABILITY 0x8
106: #define MII_STATUS_LINK_STATUS 0x4
107: #define MII_STATUS_JABBER_DETECT 0x2
108: #define MII_STATUS_EXTENDED_CAPABILITY 0x1
109:
110: /* MII ANAR register bits */
111: #define MII_ANAR_100BASET4 0x200
112: #define MII_ANAR_100BASETX_FD 0x100
113: #define MII_ANAR_100BASETX 0x80
114: #define MII_ANAR_10BASET_FD 0x40
115: #define MII_ANAR_10BASET 0x20
116:
117: /* MII ST10040 Specific */
118:
119: /* MII ST10040 ID */
120: #define MII_ST10040_OUI 0x1e0400
121: #define MII_ST10040_MODEL 0x00
122: #define MII_ST10040_REV 0x01
123: #define MII_ST10040_ID ((MII_ST10040_OUI << 10) | (MII_ST10040_MODEL << 4))
124: #define MII_ST10040_MASK 0xfffffff0
125:
126: #define MII_ST10040_DELAY 1
127:
128: /* MII ST10040 Regs */
129: #define MII_ST10040_CHIPST 0x14
130:
131: /* MII ST10040 CHIPST register bits */
132: #define MII_ST10040_CHIPST_LINK 0x2000
133: #define MII_ST10040_CHIPST_DUPLEX 0x1000
134: #define MII_ST10040_CHIPST_SPEED 0x0800
135: #define MII_ST10040_CHIPST_NEGOTIATION 0x0020
136:
137:
138: /* MII DP83843 Specific */
139:
140: /* MII DP83843 ID */
141: #define MII_DP83843_OUI 0x080017
142: #define MII_DP83843_MODEL 0x01
143: #define MII_DP83843_REV 0x00
144: #define MII_DP83843_ID ((MII_DP83843_OUI << 10) | (MII_DP83843_MODEL << 4))
145: #define MII_DP83843_MASK 0xfffffff0
146:
147: #define MII_DP83843_DELAY 20
148:
149: /* MII DP83843 PHYSTS register bits */
150: #define MII_DP83843_PHYSTS 0x10
151: #define MII_DP83843_PHYSTS_LINK 0x0001
152: #define MII_DP83843_PHYSTS_SPEED10 0x0002
153: #define MII_DP83843_PHYSTS_DUPLEX 0x0004
154: #define MII_DP83843_PHYSTS_NEGOTIATION 0x0020
155:
156:
157: /* MII timeout */
158: #define MII_DEFAULT_DELAY 20
159: #define MII_RESET_TIMEOUT 100
160: #define MII_RESET_DELAY 10
161:
162: #define MII_LINK_TIMEOUT 5000
163: #define MII_LINK_DELAY 20
164:
165: @interface BMacEnet(MII)
166:
167: - (BOOL)miiReadWord:(unsigned short *)dataPtr reg:(unsigned short)reg
168: phy:(unsigned char)phy;
169: - (BOOL)miiWriteWord:(unsigned short)data reg:(unsigned short)reg
170: phy:(unsigned char)phy;
171: - (void)miiWrite:(unsigned int)miiData size:(unsigned int)dataSize;
172: - (int)miiReadBit;
173: - (BOOL)miiCheckZeroBit;
174: - (void)miiOutThreeState;
175: - (BOOL)miiResetPHY:(unsigned char)phy;
176: - (BOOL)miiWaitForLink:(unsigned char)phy;
177: - (BOOL)miiWaitForAutoNegotiation:(unsigned char)phy;
178: - (void)miiRestartAutoNegotiation:(unsigned char)phy;
179: - (BOOL)miiFindPHY:(unsigned char *)phy_num;
180: - (BOOL)miiInitializePHY:(unsigned char)phy;
181:
182: @end
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