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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Copyright (c) 1995-1996 NeXT Software, Inc.
27: *
28: * Inline definitions for the DECchip 21X40.
29: *
30: * HISTORY
31: *
32: * 26-Apr-95 Rakesh Dubey (rdubey) at NeXT
33: * Created.
34: */
35:
36: #import <machdep/ppc/proc_reg.h>
37: #import "DECchip2104xRegisters.h"
38:
39: //#define DEBUG
40:
41: static __inline__
42: unsigned int readCsr(IOPPCAddress base, unsigned short offset)
43: {
44: unsigned int data;
45: //kprintf("R%8x:", base + offset);
46: data = lwbrx(base + offset);
47: //kprintf("%8x ", data);
48:
49: return data;
50: }
51:
52: static __inline__
53: void writeCsr(IOPPCAddress base, unsigned short offset,
54: unsigned int value)
55: {
56: //kprintf("W%8x:%8x ", base + offset, value);
57: stwbrx(value, base + offset);
58: eieio();
59: }
60:
61: static __inline__
62: void getStationAddress(IOPPCAddress base, enet_addr_t *ea)
63: {
64: int i;
65: csrRegUnion reg;
66:
67: writeCsr(base, DEC_21X40_CSR9, 0x0);
68: for (i = 0; i < sizeof (*ea); i++) {
69: do {
70: reg.data = readCsr(base, DEC_21X40_CSR9);
71: IOSleep(1);
72: } while (reg.csr90.dtnv == YES);
73: ea->ea_byte[i] = reg.csr90.dt;
74: }
75: }
76:
77:
78: /*
79: * If this procedure for reading EEPROM seems arcane to you, see the DEC's
80: * Hardware Reference Manual for DECchip21140.
81: */
82: static __inline__
83: unsigned char clock_out_bit(IOPPCAddress base)
84: {
85: csrRegUnion reg;
86: unsigned char val;
87:
88: reg.data = 0x00004800;
89:
90: reg.csr91.scs = 1; reg.csr91.sclk = 1;
91: writeCsr(base, DEC_21X40_CSR9, reg.data);
92: IODelay(250);
93:
94: reg.data = readCsr(base, DEC_21X40_CSR9);
95: IODelay(250);
96: val = reg.csr91.sdo;
97:
98: reg.data = 0x00004800;
99: reg.csr91.scs = 1; reg.csr91.sclk = 0;
100: writeCsr(base, DEC_21X40_CSR9, reg.data);
101: IODelay(250);
102:
103: return val;
104: }
105:
106: static __inline__
107: void clock_in_bit(IOPPCAddress base , unsigned int val)
108: {
109: csrRegUnion reg;
110:
111: reg.data = 0x00004800;
112:
113: if (val != 0 && val != 1) {
114: IOLog("bogus data in clock_in_bit\n");
115: return;
116: }
117:
118: reg.csr91.sdi = val;
119:
120: reg.csr91.scs = 1; reg.csr91.sclk = 0;
121: writeCsr(base, DEC_21X40_CSR9, reg.data);
122: IODelay(250);
123:
124: reg.csr91.scs = 1; reg.csr91.sclk = 1;
125: writeCsr(base, DEC_21X40_CSR9, reg.data);
126: IODelay(250);
127:
128: reg.csr91.scs = 1; reg.csr91.sclk = 0;
129: writeCsr(base, DEC_21X40_CSR9, reg.data);
130: IODelay(250);
131: }
132:
133: static __inline__
134: void reset_and_select_srom(IOPPCAddress base)
135: {
136: csrRegUnion reg;
137:
138: reg.data = 0x00004800;
139:
140: /* first reset */
141: writeCsr(base, DEC_21X40_CSR9, reg.data);
142: IODelay(250);
143:
144: /* select the serial rom */
145: clock_in_bit(base, 0);
146:
147: /* send it the read command (110) */
148: clock_in_bit(base, 1);
149: clock_in_bit(base, 1);
150: clock_in_bit(base, 0);
151: }
152:
153: static __inline__
154: unsigned short read_srom(IOPPCAddress base, unsigned int addr,
155: unsigned int addr_len)
156: {
157: unsigned short data, val;
158: int i;
159:
160: /* send out the address we want to read from */
161: for (i = 0; i < addr_len; i++) {
162: val = addr >> (addr_len-i-1);
163: clock_in_bit(base, val & 1);
164: }
165:
166: /* Now read in the 16-bit data */
167: data = 0;
168: for (i = 0; i < 16; i++) {
169: val = clock_out_bit(base);
170: data <<= 1;
171: data |= val;
172: }
173:
174: return data;
175: }
176:
177: static __inline__
178: unsigned int
179: _atoi(const char *s)
180: {
181: char *cptr;
182: unsigned int val;
183:
184: cptr = (char *)s;
185: while (*cptr && ((*cptr == ' ') || (*cptr == '\t') || (*cptr == '\n')))
186: cptr++;
187:
188: val = 0;
189: if (*cptr == '\0')
190: return 0;
191:
192: while ((*cptr != ' ') && (*cptr != '\t') && (*cptr != '\n')) {
193:
194: if ((*cptr >= '0') && (*cptr <= '9'))
195: val = val * 10 + (*cptr - '0');
196:
197: ++cptr;
198:
199: if (*cptr == '\0')
200: break;
201: }
202:
203: return val;
204: }
205:
206:
207: /*
208: * Useful for testing.
209: */
210: static __inline__
211: void _dump_srom(IOPPCAddress base, unsigned char sromAddressBits)
212: {
213: unsigned short data;
214: int i;
215:
216: for (i = 0; i < 128; i++) {
217: reset_and_select_srom(base);
218: data = read_srom(base, i, sromAddressBits);
219: IOLog("%x = %x ", i, data);
220: if (i % 10 == 0) IOLog("\n");
221: }
222: }
223:
224:
225:
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