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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Copyright (c) 1995-1996 NeXT Software, Inc.
27: *
28: * Hardware definitions and data structures for the DECchip 2104x
29: *
30: * HISTORY
31: *
32: * 26-Apr-95 Rakesh Dubey (rdubey) at NeXT
33: * Created.
34: * 07-Feb-96 Dieter Siegmund (dieter) at NeXT
35: * Crank down the size of netbufs we allocate to eliminate
36: * confusion.
37: */
38:
39: #define DEC_21X40_ALIGNMENT 4
40: #define DEC_21X40_DESCRIPTOR_ALIGNMENT 16 /* only long-word is needed */
41:
42: #define TRANSMIT_QUEUE_SIZE 64
43:
44: // 1514 + 4 + 2(align to multiple of 4)
45: #define NETWORK_BUFSIZE (ETHERMAXPACKET + ETHERCRC + 2)
46: #define NETWORK_BUFALIGNMENT 32
47:
48: #define DEC_21X40_RX_RING_LENGTH 32
49: #define DEC_21X40_TX_RING_LENGTH 16
50:
51: #define DEC_21X40_DESC_OWNED_BY_HOST 0
52: #define DEC_21X40_DESC_OWNED_BY_CTRL 1
53:
54: #define DEC_21X40_REGISTER_SPACE 128
55:
56: #define PCI_CBIO_OFFSET 0x10
57: #define PCI_CFCS_OFFSET 0x04
58:
59: /*
60: * Command and Status Register Offsets.
61: */
62: #define DEC_21X40_CSR0 0x00
63: #define DEC_21X40_CSR1 0x08
64: #define DEC_21X40_CSR2 0x10
65: #define DEC_21X40_CSR3 0x18
66: #define DEC_21X40_CSR4 0x20
67: #define DEC_21X40_CSR5 0x28
68: #define DEC_21X40_CSR6 0x30
69: #define DEC_21X40_CSR7 0x38
70: #define DEC_21X40_CSR8 0x40
71: #define DEC_21X40_CSR9 0x48
72: #define DEC_21X40_CSR10 0x50
73: #define DEC_21X40_CSR11 0x58
74: #define DEC_21X40_CSR12 0x60
75: #define DEC_21X40_CSR13 0x68
76: #define DEC_21X40_CSR14 0x70
77: #define DEC_21X40_CSR15 0x78
78:
79: /*
80: * Command and Status Register Definitions.
81: */
82: typedef struct csr0Struct {
83: unsigned int
84: rsvd :11,
85: dbo :1, /* descriptor byte ordering */
86: tap :3, /* transmit auto polling */
87: das :1, /* diagnostic address space */
88: cal :2, /* cache alignment */
89: pbl :6, /* programmable burst length */
90: ble :1, /* big/little endian */
91: dsl :5, /* descriptor skip length */
92: bar :1, /* bus arbitration */
93: swr :1; /* software reset */
94: } busModeRegister_t;
95:
96: typedef struct csr1Struct {
97: unsigned int
98: rsvd :31,
99: tpd :1; /* transmit poll demand */
100: } transmitPollDemand_t;
101:
102: typedef struct csr2Struct{
103: unsigned int
104: rsvd :31,
105: rpd :1; /* receive poll demand */
106: } receivePollDemand_t;
107:
108: typedef struct csr3Struct {
109: unsigned int
110: rdlba :32; /* receive desc. list base address */
111: } receiveListBaseAddress_t;
112:
113: typedef struct csr4Struct {
114: unsigned int
115: tdlba :32; /* transmit desc. list base address */
116: } transmitListBaseAddress_t;
117:
118: typedef struct csr5Struct {
119: unsigned int
120: rsvd3 :6,
121: eb :3, /* error bits */
122: ts :3, /* transmission process state */
123: rs :3, /* receive process state */
124: nis :1, /* normal interrupt summary */
125: ais :1, /* abnormal interrupt summary */
126: rsvd2 :1,
127: se :1, /* system error */
128: lnf :1, /* link fail */
129: fd :1, /* full-duplex short frame received */
130: at :1, /* AUI/TP pin */
131: rwt :1, /* receive watchdog timeout */
132: rps :1, /* receive process stopped */
133: ru :1, /* receive buffer unavailable */
134: ri :1, /* receive interrupt */
135: unf :1, /* transmit underflow */
136: rsvd :1,
137: tjt :1, /* transmit jabber time-out */
138: tu :1, /* transmit buffer unavailable */
139: tps :1, /* transmit process stopped */
140: ti :1; /* transmit interrupt */
141: } statusRegister_t;
142:
143: typedef struct csr5Struct_41 {
144: unsigned int
145: rsvd3 :6,
146: eb :3, /* error bits */
147: ts :3, /* transmission process state */
148: rs :3, /* receive process state */
149: nis :1, /* normal interrupt summary */
150: ais :1, /* abnormal interrupt summary */
151: er :1, /* early receive */
152: se :1, /* system error */
153: lnf :1, /* link fail */
154: tm :1, /* full-duplex short frame received */
155: rsvd1 :1, /* AUI/TP pin */
156: rwt :1, /* receive watchdog timeout */
157: rps :1, /* receive process stopped */
158: ru :1, /* receive buffer unavailable */
159: ri :1, /* receive interrupt */
160: unf :1, /* transmit underflow */
161: lnp :1, /* link pass */
162: tjt :1, /* transmit jabber time-out */
163: tu :1, /* transmit buffer unavailable */
164: tps :1, /* transmit process stopped */
165: ti :1; /* transmit interrupt */
166: } statusRegister_41_t;
167:
168: typedef struct csr6Struct {
169: unsigned int
170: sc :1,
171: rsvd :13,
172: ca :1, /* capture effect enable */
173: rsvd2 :1,
174: tr :2, /* threshold control bits */
175: st :1, /* start/stop transmission command */
176: fc :1, /* force collision mode */
177: om :2, /* operating mode */
178: fd :1, /* full-duplex mode */
179: fkd :1, /* flakey oscillator disable */
180: pm :1, /* pass all multicast */
181: pr :1, /* promiscuous mode */
182: sb :1, /* start/stop backoff counter */
183: inf :1, /* inverse filtering */
184: pb :1, /* pass bad frames */
185: ho :1, /* hash-only filtering mode */
186: sr :1, /* start/stop receive */
187: hp :1; /* hash/perfect receive filt. mode */
188: } operationModeRegister_t;
189:
190: typedef struct csr7Struct {
191: unsigned int
192: rsvd3 :15,
193: nim :1, /* normal interrupt summary mask */
194: aim :1, /* abnormal interrupt summary mask */
195: rsvd2 :1,
196: sem :1, /* system error mask */
197: lfm :1, /* link fail mask */
198: fdm :1, /* full-duplex mask */
199: atm :1, /* AUI/TP switch mask */
200: rwm :1, /* receive watchdog timeout mask */
201: rsm :1, /* receive stopped mask */
202: rum :1, /* receive buffer unavail. mask */
203: rim :1, /* receive interrupt mask */
204: unm :1, /* underflow interrupt mask */
205: rsvd1 :1,
206: tjm :1, /* transmit jabber time-out mask */
207: tum :1, /* transmit buffer unavail. mask */
208: tsm :1, /* transmit stopped mask */
209: tim :1; /* transmit interrupt mask */
210: } interruptMaskRegister_t;
211:
212: typedef struct csr8Struct {
213: unsigned int
214: rsvd :15,
215: mfo :1, /* missed frame overflow */
216: mfc :16; /* missed frame counter */
217: } missedFrameCounter_t;
218:
219:
220: /*
221: * This is CSR9 for DECchip21040.
222: */
223:
224: typedef struct csr90Struct {
225: unsigned int
226: dtnv :1, /* data not valid */
227: rsvd :23,
228: dt :8; /* data */
229: } ethernetROMRegister_t;
230:
231: /*
232: * This is CSR9 for DECchip21041.
233: */
234: typedef struct csr91Struct {
235: unsigned int
236: rsvd :16,
237: mod :1, /* mode select */
238: sro :1, /* read operation */
239: swo :1, /* write opration */
240: sbr :1,
241: ssr :1, /* select serial ROM */
242: sreg :1, /* select external register */
243: rsvd1 :6,
244: sdo :1, /* data out */
245: sdi :1, /* data in */
246: sclk :1, /* serial clock */
247: scs :1; /* chip select */
248: // mdo :1, /* MII management data out */
249: // mmd :2, /* MII management mode */
250: // mdi :1, /* MII management data in */
251: // rsvd4 :12;
252: } serialROMRegister_t;
253:
254: /*
255: * CSR 10 is reserved so we omit it.
256: */
257: struct csr10Struct {
258: unsigned int
259: rsvd :32;
260: };
261:
262: typedef struct csr11Struct {
263: unsigned int
264: rsvd :15,
265: CON :1,
266: fdacv :16; /* full-duplex auto-conf value */
267: } fullDuplexRegister_t;
268:
269: /*
270: * Serial Interface Attachment CSRs.
271: */
272:
273: typedef struct csr12Struct {
274: unsigned int
275: rsvd :24,
276: dao :1, /* PLL all one */
277: daz :1, /* PLL all zero */
278: dsp :1, /* PLL self-test pass */
279: dsd :1, /* PLL self-test done */
280: aps :1, /* auto polarity state */
281: lkf :1, /* link fail status */
282: ncr :1, /* network connection error */
283: paui :1; /* pin AUI_TP detection */
284: } siaStatusRegister_t;
285:
286: typedef struct csr12Struct_41 {
287: unsigned int
288: lpc :16, /* link-partner's link code word */
289: lpn :1, /* link-partner negotiable */
290: ans :3, /* auto-negotiate arbitratione state */
291: anr_fds :1, /* auto-negotiation restart/ */
292: /* full-duplex selected */
293: nsn :1, /* non-stable NLPs detected */
294: nra :1, /* non-selected port activity */
295: sra :1, /* selected port activity */
296: dao :1, /* PLL all one */
297: daz :1, /* PLL all zero */
298: dsp :1, /* PLL self-test pass */
299: dsd :1, /* PLL self-test done */
300: aps :1, /* auto polarity state */
301: lkf :1, /* link fail status */
302: ncr :1, /* network connection error */
303: rsvd :1;
304: } siaStatusRegister_41_t;
305:
306: typedef struct csr13Struct {
307: unsigned int
308: rsvd :16,
309: oe57 :1, /* output enable 5 6 7 */
310: oe24 :1, /* output enable 2 4 */
311: oe13 :1, /* outut enable 1 3 */
312: ie :1, /* input enable */
313: sel :4, /* ext. port output multiplx. select */
314: ase :1, /* APLL start enable */
315: sim :1, /* serial interface input multiplx. */
316: eni :1, /* encoder input multiplexer */
317: edp :1, /* SIA PLL external input enable */
318: aui :1, /* 10Base-T or AUI */
319: cac :1, /* CSR auto configuration */
320: ps :1, /* pin AUI/TP selection */
321: srl :1; /* SIA reset */
322: } siaConnectivityRegister_t;
323:
324: typedef struct csr14Struct {
325: unsigned int
326: rsvd2 :17,
327: spp :1, /* set polarity plus */
328: ape :1, /* auto polarity enable */
329: lte :1, /* link test enable */
330: sqe :1, /* signal quality gen. en. */
331: cld :1, /* collision detect enable */
332: csq :1, /* collision squelch enable */
333: rsq :1, /* receive squelch enable */
334: rsvd1 :2,
335: cpen :2, /* compensation enable */
336: lse :1, /* link pulse send enable */
337: dren :1, /* driver enable */
338: lbk :1, /* loopback enable */
339: ecen :1; /* encoder enable */
340: } siaTransmitReceiveRegister_t;
341:
342: typedef struct csr14Struct_41 {
343: unsigned int
344: rsvd :16,
345: tas :1, /* 10BASE-T/AUI autosensing enable */
346: spp :1, /* set polarity plus */
347: ape :1, /* auto polarity enable */
348: lte :1, /* link test enable */
349: sqe :1, /* signal quality gen. en. */
350: cld :1, /* collision detect enable */
351: csq :1, /* collision squelch enable */
352: rsq :1, /* receive squelch enable */
353: ane :1, /* auto-negotiation enable */
354: hde :1, /* half-duplex enable */
355: cpen :2, /* compensation enable */
356: lse :1, /* link pulse send enable */
357: dren :1, /* driver enable */
358: lbk :1, /* loopback enable */
359: ecen :1; /* encoder enable */
360: } siaTransmitReceiveRegister_41_t;
361:
362: typedef struct csr15Struct {
363: unsigned int
364: rsvd4 :18,
365: frl :1, /* force receive low */
366: dpst :1, /* PLL self-test start */
367: rsvd3 :1,
368: flf :1, /* force link fail */
369: fusq :1, /* force unsquelch */
370: tsck :1, /* test clock */
371: rsvd2 :2,
372: rwr :1, /* receive watchdog release */
373: rwd :1, /* receive watchdog disable */
374: rsvd1 :1,
375: jck :1, /* jabber clock */
376: huj :1, /* host unjab */
377: jbd :1; /* jabber disable */
378: } siaGeneralRegister_t;
379:
380: /*
381: * This is done for convenience in accessing registers.
382: */
383: typedef union {
384: struct csr0Struct csr0;
385: struct csr1Struct csr1;
386: struct csr2Struct csr2;
387: struct csr3Struct csr3;
388: struct csr4Struct csr4;
389: struct csr5Struct csr5;
390: struct csr5Struct_41 csr5_41;
391: struct csr6Struct csr6;
392: struct csr7Struct csr7;
393: struct csr8Struct csr8;
394: struct csr90Struct csr90;
395: struct csr91Struct csr91;
396: struct csr10Struct csr10;
397: struct csr11Struct csr11;
398: struct csr12Struct csr12;
399: struct csr12Struct_41 csr12_41;
400: struct csr13Struct csr13;
401: struct csr14Struct csr14;
402: struct csr15Struct csr15;
403: unsigned int data;
404: } csrRegUnion;
405:
406: /*
407: * Descriptor structures
408: */
409:
410: typedef union {
411: struct _tdes0 {
412: unsigned int
413: own :1, /* ownership (1 == 21X40) */
414: rsvd2 :15,
415: es :1, /* error summary */
416: to :1, /* transmit jabber timeout */
417: rsvd1 :2,
418: lo :1, /* loss of carrier */
419: nc :1, /* no carrier */
420: lc :1, /* late collision */
421: ec :1, /* excessive collisions */
422: hf :1, /* heartbeat fail */
423: cc :4, /* collision count */
424: lf :1, /* link fail */
425: uf :1, /* underflow error */
426: de :1; /* deferred */
427: } reg;
428: unsigned int data;
429: } tdes0;
430:
431: typedef union {
432: struct {
433: unsigned int
434: ic :1, /* interrupt on completion */
435: ls :1, /* last segment */
436: fs :1, /* first segment */
437: ft1 :1, /* filtering type */
438: set :1, /* setup packet */
439: ac :1, /* add CRC disable */
440: ter :1, /* transmit end of ring */
441: tch :1, /* second address chained */
442: dpd :1, /* disabled padding */
443: fto :1, /* filtering type */
444: byteCountBuffer2 :11, /* buffer 2 size */
445: byteCountBuffer1 :11; /* buffer 1 size */
446: } reg;
447: unsigned int data;
448: } tdes1;
449:
450: typedef struct _txDescriptorStruct {
451: tdes0 status;
452: tdes1 control;
453: unsigned int bufferAddress1;
454: unsigned int bufferAddress2;
455: } txDescriptorStruct;
456:
457: typedef union {
458: struct {
459: unsigned int
460: own :1, /* ownership (1 == 21X40) */
461: fl :15, /* frame length */
462: es :1, /* error summary */
463: le :1, /* length error */
464: dt :2, /* data type */
465: rf :1, /* runt frame */
466: mf :1, /* multicast frame */
467: fs :1, /* first descriptor */
468: ls :1, /* last descriptor */
469: tl :1, /* frame too long */
470: cs :1, /* collision seen */
471: ft :1, /* frame type */
472: rj :1, /* receive watchdog */
473: rsvd :1,
474: db :1, /* dribbling bit */
475: ce :1, /* CRC error */
476: of :1; /* overflow */
477: } reg;
478: unsigned int data;
479: } rdes0;
480:
481: typedef union {
482: struct {
483: unsigned int
484: rsvd2 :6,
485: rer :1, /* receive end of ring */
486: rch :1, /* second address chained */
487: rsvd1 :2,
488: byteCountBuffer2 :11, /* buffer 2 size */
489: byteCountBuffer1 :11; /* buffer 1 size */
490: } reg;
491: unsigned int data;
492: } rdes1;
493:
494: typedef struct _rxDescriptorStruct {
495: rdes0 status;
496: rdes1 control;
497: unsigned int bufferAddress1;
498: unsigned int bufferAddress2;
499: } rxDescriptorStruct;
500:
501: #define DEC21040_VENDOR_DEVICE_ID 0x00021011
502: #define DEC21041_VENDOR_DEVICE_ID 0x00141011
503:
504: #define DEC_21X40_SETUP_PERFECT_ENTRIES 16
505: #define DEC_21X40_SETUP_PERFECT_MCAST_ENTRIES 14
506:
507: typedef struct {
508: unsigned long physicalAddress[DEC_21X40_SETUP_PERFECT_ENTRIES][3];
509: } setupBuffer_t;
510:
511: #ifdef undef
512: void *
513: IOMallocPage(int page_size, void * * actual_ptr,
514: int * actual_size)
515: {
516: void * mem_ptr;
517:
518: if (page_size != PAGE_SIZE)
519: return (NULL);
520:
521: *actual_size = PAGE_SIZE * 2;
522: mem_ptr = IOMalloc(PAGE_SIZE * 2);
523: if (mem_ptr == NULL)
524: return (NULL);
525: *actual_ptr = mem_ptr;
526: return ((void *)round_page(mem_ptr));
527: }
528: #endif undef
529:
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