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Annotation of kernel/bsd/dev/ppc/drvPPCATA/Cmd646xRegs.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
        !             3:  *
        !             4:  * @APPLE_LICENSE_HEADER_START@
        !             5:  * 
        !             6:  * Portions Copyright (c) 1999 Apple Computer, Inc.  All Rights
        !             7:  * Reserved.  This file contains Original Code and/or Modifications of
        !             8:  * Original Code as defined in and that are subject to the Apple Public
        !             9:  * Source License Version 1.1 (the "License").  You may not use this file
        !            10:  * except in compliance with the License.  Please obtain a copy of the
        !            11:  * License at http://www.apple.com/publicsource and read it before using
        !            12:  * this file.
        !            13:  * 
        !            14:  * The Original Code and all software distributed under the License are
        !            15:  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
        !            16:  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
        !            17:  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
        !            18:  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
        !            19:  * License for the specific language governing rights and limitations
        !            20:  * under the License.
        !            21:  * 
        !            22:  * @APPLE_LICENSE_HEADER_END@
        !            23:  */
        !            24: 
        !            25: /*
        !            26:  *     PCI Control registers for Cmd646X chipset 
        !            27:  *
        !            28:  */
        !            29: #define        kCmd646xCFR                             0x50            /* Configuration */
        !            30: #define kCmd646xCFR_DSA1                       0x40
        !            31: #define kCmd646xCFR_IDEIntPRI                  0x04
        !            32: 
        !            33: #define kCmd646xCNTRL                          0x51            /* Drive 0/1 Control Register */
        !            34: #define kCmd646xCNTRL_Drive1ReadAhead          0x80
        !            35: #define kCmd646xCNTRL_Drive0ReadAhead          0x40
        !            36: #define kCmd646xCNTRL_EnableSDY                        0x08
        !            37: #define kCmd646xCNTRL_EnablePRI                        0x04
        !            38: 
        !            39: #define kCmd646xCMDTIM                         0x52            /* Task file timing (all drives) */
        !            40: #define kCmd646xCMDTIM_Drive01CmdActive                0xF0
        !            41: #define kCmd646xCMDTIM_Drive01CmdRecovery      0x0F
        !            42: 
        !            43: #define kCmd646xARTTIM0                                0x53            /* Drive 0 Address Setup */
        !            44: #define kCmd646xARTTIM0_Drive0AddrSetup                0xC0
        !            45: 
        !            46: #define kCmd646xDRWTIM0                                0x54            /* Drive 0 Data Read/Write - DACK Time  */
        !            47: #define kCmd646xDRWTIM0_Drive0DataActive       0xF0
        !            48: #define kCmd646xDRWTIM0_Drive0DataRecovery     0x0F
        !            49: 
        !            50: #define kCmd646xARTTIM1                                0x55            /* Drive 1 Address Setup */
        !            51: #define kCmd646xARTTIM1_Drive1AddrSetup                0xC0
        !            52: 
        !            53: #define kCmd646xDRWTIM1                                0x56            /* Drive 1 Data Read/Write - DACK Time */
        !            54: #define kCmd646xDRWTIM1_Drive1DataActive       0xF0
        !            55: #define kCmd646xDRWTIM1_Drive1DataRecover      0x0F
        !            56: 
        !            57: #define kCmd646xARTTIM23                       0x57            /* Drive 2/3 Control/Status */
        !            58: #define kCmd646xARTTIM23_AddrSetup             0xC0
        !            59: #define kCmd646xARTTIM23_IDEIntSDY             0x10
        !            60: #define kCmd646xARTTIM23_Drive3ReadAhead       0x08
        !            61: #define kCmd646xARTTIM23_Drive2ReadAhead       0x04
        !            62: 
        !            63: #define kCmd646xDRWTIM2                                0x58            /* Drive 2 Read/Write - DACK Time */
        !            64: #define kCmd646xDRWTIM2_Drive2DataActive       0xF0    
        !            65: #define kCmd646xDRWTIM2_Drive2DataRecovery     0x0F
        !            66: 
        !            67: #define kCmd646xBRST                           0x59            /* Read Ahead Count */
        !            68: 
        !            69: #define kCmd646xDRWTIM3                                0x5B            /* Drive 3 Read/Write - DACK Time */
        !            70: #define kCmd646xDRWTIM3_Drive3DataActive       0xF0
        !            71: #define kCmd646xDRWTIM3_Drive3DataRecover      0x0F
        !            72: 
        !            73: #define kCmd646xBMIDECR0                       0x70            /* BusMaster Command Register - Primary */
        !            74: #define kCmd646xBMIDECR0_PCIWritePRI           0x08
        !            75: #define kCmd646xBMIDECR0_StartDMAPRI           0x01
        !            76: 
        !            77: #define kCmd646xMRDMODE                                0x71            /* DMA Master Read Mode Select */
        !            78: #define kCmd646xMRDMODE_PCIReadMask            0x03
        !            79: #define kCmd646xMRDMODE_PCIRead                        0x00
        !            80: #define kCmd646xMRDMODE_PCIReadMultiple                0x01
        !            81: #define kCmd646xMRDMODE_IDEIntPRI              0x04
        !            82: #define kCmd646xMRDMODE_IDEIntSDY              0x08
        !            83: #define kCmd646xMRDMODE_IntEnablePRI           0x10
        !            84: #define kCmd646xMRDMODE_IntEnableSDY           0x20
        !            85: #define kCmd646xMRDMODE_ResetAll               0x40
        !            86: 
        !            87: #define kCmd646xBMIDESR0                       0x72            /* BusMaster Status Register - Primary */
        !            88: #define kCmd646xBMIDESR0_Simplex               0x80
        !            89: #define kCmd646xBMIDESR0_Drive1DMACap          0x40
        !            90: #define kCmd646xBMIDESR0_Drive0DMACap          0x20
        !            91: #define kCmd646xBMIDESR0_DMAIntPRI             0x04
        !            92: #define kCmd646xBMIDESR0_DMAErrorPRI           0x02
        !            93: #define kCmd646xBMIDESR0_DMAActivePRI          0x01
        !            94: 
        !            95: #define kCmd646xUDIDETCR0                      0x73            /* Ultra DMA Timing Control Register - Primary */
        !            96: #define kCmd646xUDIDETCR0_Drive1UDMACycleTime  0xC0
        !            97: #define kCmd646xUDIDETCR0_Drive0UDMACycleTime  0x30
        !            98: #define kCmd646xUDIDETCR0_Drive1UDMAEnable     0x02
        !            99: #define kCmd646xUDIDETCR0_Drive0UDMAEnable     0x01
        !           100: 
        !           101: #define kCmd646xDTPR0                          0x74            /* Descriptor Table Pointer - Primary */
        !           102: 
        !           103: #define kCmd646xBMIDECR1                       0x78            /* BusMaster Command Register - Secondary */
        !           104: #define kCmd646xBMIDECR1_PCIWriteSDY           0x08
        !           105: #define kCmd646xBMIDECR1_StartDMASDY           0x01
        !           106: 
        !           107: #define kCmd646xBMIDESR1                       0x7A            /* BusMaster Status Register - Secondary */
        !           108: #define kCmd646xBMIDESR1_Simplex               0x80
        !           109: #define kCmd646xBMIDESR1_Drive3DMACap          0x40
        !           110: #define kCmd646xBMIDESR1_Drive2DMACap          0x20
        !           111: #define kCmd646xBMIDESR1_DMAIntSDY             0x04
        !           112: #define kCmd646xBMIDESR1_DMAErrorSDY           0x02
        !           113: #define kCmd646xBMIDESR1_DMAActiveSDY          0x01
        !           114: 
        !           115: #define kCmd646xUDIDETCR1                      0x7B            /* Ultra DMA Timing Control Register - Secondary */
        !           116: #define kCmd646xUDIDETCR1_Drive3UDMACycleTime  0xC0
        !           117: #define kCmd646xUDIDETCR1_Drive2UDMACycleTime  0x30
        !           118: #define kCmd646xUDIDETCR1_Drive3UDMAEnable     0x02
        !           119: #define kCmd646xUDIDETCR1_Drive2UDMAEnable     0x01
        !           120: 
        !           121: #define kCmd646xDTPR1                          0x7C            /* Descriptor Table Pointer - Primary */
        !           122: 

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