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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Copyright (c) 1998 Apple Computer Inc.
27: *
28: * Symbios8xx Controller.
29: *
30: */
31:
32: /* SymBios 8xx register addressing definitions */
33:
34: #define SCNTL0_SIZE 0x01
35: #define SCNTL0 0x00000000
36: #define SCNTL0_INIT 0xCA /* Scsi control 0 */
37: /* ARB1 1 */
38: /* ARB0 1 : Full arbitration */
39: /* START 0 : Start sequence */
40: /* WATN 0 : Select with ATN */
41: /* EPC 1 : enable SCSI bus parity checking */
42: /* RES */
43: /* AAP 1 : Assert ATN on SCSI parity error */
44: /* TRG 0 : Target mode. 720 is Initiator */
45:
46: #define SCNTL1_SIZE 0x01
47: #define SCNTL1 0x00000001
48: #define SCNTL1_INIT 0x00 /* Scsi control 1 */
49: /* EXC 0 : Extra clock cycle data setup (Sdtr) */
50: /* ADB 0 : Assert SCSI data bus */
51: /* DHP 0 : Target only Disable halt parity error */
52: /* CON 0 : 820 connected to SCSI bus */
53: /* RST 0 : Assert SCSI RST signal */
54: /* AESP 0 : Force bad parity */
55: /* IARB 0 : Immediate arbitration */
56: /* SST 0 : Start SCSI transfer */
57:
58: #define SCNTL1_SCSI_RST 0x08 /* force scsi reset in scntl1 reg */
59:
60: #define SCNTL2_SIZE 0x01
61: #define SCNTL2 0x00000002
62: #define SCNTL2_INIT 0x00 /* Scsi control 2 */
63: #define SDU 0x80 /* SDU 0 : SCSI Disconnect Unexpected */
64: #define CHM 0x40 /* CHM 0 : Chained mode */
65: #define SLPMD 0x40 /* SLPMD 0 : SLPAR Mode Bit */
66: #define SLPHBEN 0x40 /* SLPHBEN : SLPAR High Byte Enable */
67: #define WSS 0x08 /* WSS 0 : Wide Scsi Send */
68: #define VUE0 0x40 /* VUE0 : Vendor Uniq Enhancements Bit 0 */
69: #define VUE1 0x40 /* VUE1 : Vendor Uniq Enhancements Bit 1 */
70: #define WSR 0x01 /* WSR 0 : Wide Scsi Receive */
71:
72: #define SCNTL3_SIZE 0x01
73: #define SCNTL3 0x00000003
74: #define SCNTL3_INIT 0x03 /* Scsi control 3 for 40Mhz sys clock */
75: #define SCNTL3_INIT_875 0x05 /* Scsi control 3 for 80Mhz sys clock */
76: #define SCNTL3_INIT_875_ULTRA 0x95 /* Scsi control 3 for 80Mhz sys clock */
77: #define SCNTL3_INIT_875_FAST 0x35 /* Scsi control 3 for 80Mhz sys clock */
78: #define SCNTL3_INIT_875_SLOW 0x55 /* Scsi control 3 for 80Mhz sys clock */
79: /* RES */
80: #define SCF 0x70 /* SCF 0 : Sync clock conversion factor 0-2 */
81: #define EWS 0x08 /* EWS 0 : Enable Wide SCSI (wdtr) */
82: #define CCF 0x07 /* CCF 0 : Async clock conversion factor 0-2 */
83:
84: #define SCID_SIZE 0x01
85: #define SCID 0x00000004
86: #define SCID_INIT 0x40 /* Scsi chip Id */
87: /* RES */
88: /* RRE 1 : Enable response to reselection */
89: /* SRE 0 : Disable response to selection */
90: /* RES */
91: /* ID3 0 */
92: /* ID2 0 */
93: /* ID1 0 */
94: /* ID0 0 : Encoded 53825 chip SCSI Id */
95:
96: #define SXFER_SIZE 0x01
97: #define SXFER 0x00000005
98: #define SXFER_INIT 0x00 /* Scsi Transfer */
99: /* TP2 0 */
100: /* TP1 0 */
101: /* TP0 0 : Scsi sync Transfer Period (4)(Sdtr) */
102: /* RES */
103: /* MO3 0 */
104: /* MO2 0 */
105: /* MO1 0 */
106: /* MO0 0 : Max Scsi Sync ReqAck offset (async) (Sdtr) */
107:
108: #define SDID_SIZE 0x01
109: #define SDID 0x00000006
110: #define SDID_INIT 0x00 /* Scsi destination Id */
111: /* RES */
112: /* RES */
113: /* RES */
114: /* RES */
115: /* ID3 0 */
116: /* ID2 0 */
117: /* ID1 0 */
118: /* ID0 0 : Encoded destination Scsi Id */
119:
120: #define GPREG_SIZE 0x01
121: #define GPREG 0x00000007
122: #define GPREG_INIT 0x00 /* Read/write general purpose */
123: #define GPIO3 0x08 /* GPIO bit 3 */
124: /* RES */
125: /* RES */
126: /* RES */
127: /* GPO 0 : General purpose output */
128: /* GPI3 0 */
129: /* GPI2 0 */
130: /* GPI1 0 */
131: /* GPI0 0 : General purpose inputs */
132:
133: #define SFBR_SIZE 0x01
134: #define SFBR 0x00000008
135: #define SFBR_INIT 0x00
136: /* SCSI First Byte Received */
137:
138: #define SOCL_SIZE 0x01
139: #define SOCL 0x00000009
140: #define SOCL_INIT 0x00
141: #define SREQ 0x80 /* REQ 0 : Assert SCSI REQ signal */
142: #define SACK 0x40 /* ACK 0 : ACK */
143: #define SBSY 0x20 /* BSY 0 : BSY */
144: #define SSEL 0x10 /* SEL 0 : SEL */
145: #define SATN 0x08 /* ATN 0 : ATN */
146: #define SMSG 0x04 /* MSG 0 : MSG */
147: #define SC_D 0x02 /* C/D 0 : C/D */
148: #define SI_O 0x01 /* I/O 0 : I/O */
149:
150: #define SSID_SIZE 0x01
151: #define SSID 0x0000000A /* Read Only */
152: /* VAL Scsi Valid Bit */
153: /* RES */
154: /* RES */
155: /* RES */
156: /* ID3 */
157: /* ID2 */
158: /* ID1 */
159: /* ID0 Encoded Destination Scsi Id */
160:
161: #define SBCL_SIZE 0x01
162: #define SBCL 0x0000000B /* Scsi Bus Control Lines Read only */
163: /* REQ */
164: /* ACK */
165: /* BSY */
166: /* SEL */
167: /* ATN */
168: /* MSG */
169: /* C/D */
170: /* I/O */
171:
172: #define DSTAT_SIZE 0x01
173: #define DSTAT 0x0000000C /* DMA status Read only */
174: #define DFE 0x80 /* DSTAT DMA FIFO Empty */
175: #define MDPE 0x40 /* Master Data Parity Error */
176: #define BF 0x20 /* Bus Fault */
177: #define DABRT 0x10 /* Abort occurred */
178: #define SSI 0x08 /* Script Step Interrupt */
179: #define SIR 0x04 /* Script Interrupt Inst Received */
180: #ifdef notdef
181: #define WTD 0x02 /* was watchdog timer, now reserved */
182: #endif /* notdef */
183: #define IID 0x01 /* Illegal Instruction Detected */
184:
185: #define SSTAT0_SIZE 0x01
186: #define SSTAT0 0x0000000D /* SCSI status zero Read only */
187: #define ILF 0x80 /* ILF SIDL least significant byte full */
188: #define ORF 0x40 /* ORF SODR least significant byte full */
189: #define OLF 0x20 /* OLF SODL least significant byte full */
190: #define AIP 0x10 /* AIP Arbitration in progress */
191: #define LOA 0x08 /* LOA Lost arbitration */
192: #define WOA 0x04 /* WOA Won arbitration */
193: #define RSTB 0x02 /* RST Scsi reset signal */
194: #define SDP0 0x01 /* SDP0 Scsi SDP0 parity signal */
195:
196: #define SSTAT1_SIZE 0x01
197: #define SSTAT1 0x0000000E /* SCSI status one Read only */
198: /* FF3-0 Bytes or word in the Scsi FIFO */
199: /* SDP Latched Scsi parity */
200: /* MSG Scsi phase status */
201: /* C/D */
202: /* I/O */
203:
204: #define SSTAT2_SIZE 0x01
205: #define SSTAT2 0x0000000F /* Scsi status two Read only */
206: #define ILF1 0x80 /* ILF1 SIDL most significant byte full */
207: #define ORF1 0x40 /* ORF1 SODR " " " " */
208: #define OLF1 0x20 /* OLF1 SODL " " " " */
209: /* RES */
210: #define SPL1 0x08 /* SPL1 Latched Scsi parity for SIDL15-8 */
211: #define FF4 0x04 /* FIFO Flags Bit 4 */
212: #define LDSC 0x02 /* LDSC Last disconnect */
213: #define SDP1 0x01 /* SDP1 Scsi SDP1 Signal */
214:
215: #define DSA_SIZE 0x04
216: #define DSA 0x00000010
217: #define DSA_INIT 0x00000000 /* Data structure address */
218:
219: #define ISTAT_SIZE 0x01
220: #define ISTAT 0x00000014
221: #define ISTAT_INIT 0x00 /* Interrupt Status */
222: #define ABRT 0x80 /* Abort Operation */
223: #define RST 0x40 /* Software reset */
224: #define SIGP 0x20 /* Signal process */
225: #define SEM 0x10 /* Semaphore */
226: #define ISTAT_CON 0X08 /* Connected to target. */
227: #define INTF 0x04 /* Interrupt on the fly */
228: #define SIP 0x02 /* SCSI Interrupt Pending */
229: #define DIP 0x01 /* DMA Interrupt Pending */
230:
231: #define CTEST0_SIZE 0x01
232: #define CTEST0 0x00000018
233: #define CTEST0_INIT 0x00 /* Chip test zero (now general purpose, rph) */
234:
235: #define CTEST1_SIZE 0x01
236: #define CTEST1 0x00000019 /* Chip test one Read only */
237: /* FMT3-0 0 : Byte empty in DMA FIFO */
238: /* FFL3-0 0 : Byte full in DMA FIFO */
239:
240: #define CTEST2_SIZE 0x01
241: #define CTEST2 0x0000001A /* Chip test two Read only */
242: /* DDIR Data transfer direction (1 : Scsi bus -> host) */
243: /* SIGP Signal process (Clear SIGP ISTAT when read) */
244: /* CIO (read-only, indicates chip configured as I/O space) */
245: /* CM (read-only, indicates configured as memory space) */
246: /* RES */
247: /* TEOP Scsi true end of process */
248: /* DREQ Data request status */
249: /* DACK Data acknowledge status */
250:
251: #define CTEST3_SIZE 0x01
252: #define CTEST3 0x0000001B
253: #define CTEST3_INIT 0x04 /* Chip test three */
254: #define CTEST3_INIT_A 0x05 /* Chip test three for 'A' part */
255:
256: #define VERS 0xf0 /* V3-0 0 : Chip revision level */
257: #define FLF 0x08 /* FLF 0 : Flush DMA Fifo */
258: #define CLF 0x04 /* CLF 1 : Clear DMA FIFO */
259: #define FM 0x02 /* FM 0 : Fetch pin mode */
260: #define WRIE 0x01 /* WRIE 1 : Write and Invalidate Enable, for 825A only!!! */
261:
262: #define TEMP_SIZE 0x04
263: #define TEMP 0x0000001C
264: #define TEMP_INIT 0x00000000 /* Tempory stack */
265:
266: #define DFIFO_SIZE 0x01
267: #define DFIFO 0x00000020
268: #define DFIFO_INIT 0x00 /* DMA FIFO */
269: /* upper bit used for 825 'A' part when using large fifo */
270: /* BO6-0 0: Byte offset counter */
271:
272: #define CTEST4_SIZE 0x01
273: #define CTEST4 0x00000021 /* Chip test four */
274: // #define CTEST4_INIT 0x80 /* Chip test four DISABLE BURST!! */
275: #define CTEST4_INIT 0x00 /* Chip test four */
276: /* BDIS 0 : set for Burst Disable, reset allows burst on data moves */
277: /* ZMOD High impedance mode */
278: /* ZSD Scsi high impedance mode */
279: /* SRTM Shadow register test mode */
280: /* NOT for bandit!!!! yes for NEW rev of Dumbarton LATER on, not initial!!! */
281: /* MPEE 0 : Master Parity Error Enable Do we want this set???? rph */
282: /* FBL2-0 Fifo byte control */
283:
284: #define CTEST5_SIZE 0x01
285: #define CTEST5 0x00000022
286: #define CTEST5_INIT 0x00 /* Chip test five */
287: #define CTEST5_INIT_A 0x00 /* Chip test five 'A' part, upper burst OFF */
288: #define CTEST5_INIT_A_revB 0x24 /* Chip test five 'A' part, upper burst OFF
289: * also Enable 536 byte fifo */
290: #define ADCK 0x80 /* ADCK 0 : Clock address incrementor */
291: #define BBCK 0x40 /* BBCK 0 : Clock byte counter */
292: #define DFS 0x20 /* DFS 0 : fifo size - 0=88 1=536 bytes */
293: #define MASR 0x10 /* MASR 0 : Master control for set reset pulses */
294: #define DDIR 0x08 /* DDIR 0 : DMA direction */
295: #define BL2 0x04 /* BL2 0 : see DMODE bits 6,7 */
296: #define BO89 0x03 /* BO89 0 : upper bits of DFIFO count */
297:
298: #define CTEST6_SIZE 0x01
299: #define CTEST6 0x00000023
300: #define CTEST6_INIT 0x00 /* chip test six */
301: /* 7-0 0 : DMA Fifo */
302:
303: #define DBC_SIZE 0x04
304: #define DBC 0x00000024
305: #define DBC_INIT 0x000000 /* DMA Byte Counter */
306:
307: #define DCMD_SIZE 0x01
308: #define DCMD 0x00000027
309: #define DCMD_INIT 0x00 /* DMA command */
310:
311: #define DNAD_SIZE 0x04
312: #define DNAD 0x00000028
313: #define DNAD_INIT 0x00000000 /* DMA Next Data Address */
314:
315: #define DSP_SIZE 0x04
316: #define DSP 0x0000002C
317: #define DSP_INIT 0x00000000 /* DMA script pointer */
318:
319: #define DSPS_SIZE 0x04
320: #define DSPS 0x00000030
321: #define DSPS_INIT 0x00000000 /* DMA SCRIPTS Pointer Save */
322:
323: #define SCRATCHA_SIZE 0x04
324: #define SCRATCHA 0x00000034
325: #define SCRATCHA0 0x00000034
326: #define SCRATCHA1 0x00000035
327: #define SCRATCHA2 0x00000036
328: #define SCRATCHA3 0x00000037
329: #define SCRATCHA_INIT 0x04030201 /* general purpose register */
330:
331: #define DMODE_SIZE 0x01
332: #define DMODE 0x00000038
333: /* 825 bug!!!!! 8 is max!!!!!!! rph 8-23-94
334: */
335: #define DMODE_INIT 0x82 /* DMA mode 8 burst xfers + instruc fetch */
336: #define DMODE_INIT_A 0x0A /* DMA mode 32 burst xfers + instruc fetch */
337: /* BL1 1 : Burst length, burst size is '8' transfers (4 bytes per) */
338: /* BL0 0 : Burst length */
339: /* SIOM 0 : Source I/O-Memory Enable (Memory space is default) */
340: /* DIOM 0 : Destination I/O-Memory Enable (Memory space is default) */
341: /* ER 1 : Enable Read Line Command, set for 825'A' part */
342: /* ERM 0 : */
343: /* BOF 1 : Burst Op Code Fetch Enable, only for 825!!! rph */
344: /* MAN 0 : Manual start mode (leave 0 for auto-start with DSP write */
345:
346: #define DIEN_SIZE 0x01
347: #define DIEN 0x00000039
348: #define DIEN_INIT 0x7D /* No mask on DMA interrupt */
349: /* RES */
350: /* MDPE 1 : Master Data Parity Error */
351: /* BF 1 : Bus fault */
352: /* ABRT 1 : Aborted */
353: /* SSI 1 : Script step interrupt */
354: /* SIR 1 : Script interrupt instruction received */
355: /* RES */
356: /* IID 1 : Illegal instruction detected */
357:
358: #define DWT_SIZE 0x01
359: #define DWT 0x0000003A
360: #define DWT_INIT 0xD0 /* DMA watchdog timer to 0xD0*32*BCLK ns*/
361:
362: #define DCNTL_SIZE 0x01
363: #define DCNTL 0x0000003B
364: #define DCNTL_INIT 0x01 /* DMA Control register */
365: #define DCNTL_INIT_A 0xA1 /* DMA Control register, 'A' part */
366: /* CLE 7: Cache Line Size Enable for 'A' part */
367: /* PFF 6: pre-fetch flush bit for 'A' part */
368: /* PFEN 5: pre-fetch Enable bit for 'A' part */
369: /* RES */
370: /* RES */
371: #define SSM 0x10 /* 0 : Single step mode */
372: /* IRQM 0 : HW driver type for IRQ pin, default is open drain, ask HW rph*/
373: #define STD 0x04 /* 0 : start DMA operation */
374: /* IRQ 1: IRQ disable for 'A' part */
375: /* COM 1 : No Compatibility 700 */
376:
377: #define ADDER_SIZE 0x04
378: #define ADDER 0x0000003C /* Adder sum output Read only */
379:
380: #define SIEN_SIZE 0x02
381: #define SIEN 0x00000040
382: #define SIEN_INIT_RST_OFF 0x048D /* SCSI Interrupt enable SIEN0-1 rph */
383: #define SIEN_INIT 0x048F /* SCSI Interrupt enable SIEN0-1 rph */
384: /* SIEN0 */
385: /* M/A 1 : Scsi phase mismatch */
386: /* CMP 0 : Function complete */
387: /* SEL 0 : Selected */
388: /* RSL 0 : Reselected */
389: /* SGE 1 : Scsi Gross error */
390: /* UDC 1 : Unexpected disconnect */
391: /* RST 1 : Scsi Reset condition */
392: /* PAR 1 : Scsi Parity error */
393:
394: /* RES */
395: /* RES */
396: /* RES */
397: /* RES */
398: /* RES */
399: /* STO 1 : (Re)Selection timeout */
400: /* GEM 0 : General purpose timeout*/
401: /* HTH 0 : Handshake timeout */
402:
403: #define SIST_SIZE 0x02
404: #define SIST 0x00000042 /* Scsi interrupt status Read only */
405: /* idem SIEN reg */
406: #define STO 0x0400
407: #define GEN 0x0200
408: #define HTH 0x0100
409:
410: #define MA 0x0080
411: #define CMP 0x0040
412: #define SEL 0x0020
413: #define RSL 0x0010
414: #define SGE 0x0008
415: #define UDC 0x0004
416: #define RSTI 0x0002
417: #define PAR 0x0001
418:
419: #define SLPAR_SIZE 0x01
420: #define SLPAR 0x00000044
421: #define SLPAR_INIT 0x00 /* SCSI longitudinal parity */
422:
423: #define SWIDE_SIZE 0x01
424: #define SWIDE 0x00000045 /* Scsi wide residue data Read only */
425:
426: #define MACNTL_SIZE 0x01
427: #define MACNTL 0x00000046
428: #define MACNTL_INIT 0x00 /* memory access control */
429: /* TYP3-0 : Chip Type (read-only) */
430: /* DataWr 0 : Data write Far memory */
431: /* DataRd 0 : Data read far memory */
432: /* Pointer to script fetch 0 : far memory */
433: /* Script fetch 0 : far memory */
434:
435: #define GPCNTL_SIZE 0x01
436: #define GPCNTL 0x00000047
437: #define GPCNTL_INIT 0x0F /* General purpose control Cf appendum ?? */
438: // #define GPCNTL_INIT 0xCF /* General purpose control Cf appendum ?? */
439: /* ME : 0 Master Enable */
440: /* FE : 0 Fetch Enable */
441: /* RES */
442: /* GPI/O_en4 : 0 GPREG input or output */
443: /* GPI/O_en3 : 1 */
444: /* GPI/O_en2 : 1 */
445: /* GPI/O_en1 : 1 */
446: /* GPI/O_en0 : 1 */
447:
448: #define STIME0_SIZE 0x01
449: #define STIME0 0x00000048
450: #define STIME0_INIT 0x0C /* Scsi timer register 0 */
451: /* HTH3 */
452: /* HTH2 */
453: /* HTH1 0 */
454: /* HTH0 0 : Handshake timer period (disabled) */
455: /* SEL3 1 */
456: /* SEL2 1 */
457: /* SEL1 0 */
458: /* SEL0 0 : Selection timeout period (204.8ms) */
459:
460: #define STIME1_SIZE 0x01
461: #define STIME1 0x00000049
462: #define STIME1_INIT 0x00 /* Scsi timer register one */
463: /* RES */
464: /* RES */
465: /* RES */
466: /* RES */
467: /* GEN3 0 */
468: /* GEN2 0 */
469: /* GEN1 0 */
470: /* GEN0 0 : General purpose timer period (disabled) */
471:
472: #define RESPID0_SIZE 0x01
473: #define RESPID0 0x0000004A
474: #define RESPID0_INIT 0x00 /* Response Id zero */
475: /* ID7 - ID0 */
476:
477: #define RESPID1_SIZE 0x01
478: #define RESPID1 0x0000004B
479: #define RESPID1_INIT 0x00 /* Response ID one */
480: /* ID15 - ID8 */
481:
482: #define STEST0_SIZE 0x01
483: #define STEST0 0x0000004C /* Scsi test register zero Read only */
484: /* RES */
485: /* RES */
486: /* RES */
487: /* RES */
488: /* SLT Selection response Logic test */
489: /* ART Arbitration priority encoder test */
490: /* SOZ Scsi synchronous offset zero */
491: /* SOM Scsi synchronous offset maximum */
492:
493: #define STEST1_SIZE 0x01
494: #define STEST1 0x0000004D /* Scsi test register one Read/Write */
495: #define STEST1_INIT 0x00
496: #define SCLK 0x80 /* SCLK 0 : 1 = Use PCI Clock 0 = Use SCLK input */
497: #define SISIO 0x40 /* SISIO 0 : SCSI Isolation Mode */
498: /* 0 : */
499: /* 0 : */
500: #define DBLEN 0x08 /* DBLEN 0 : SCLK Doubler Enable */
501: #define DBLSEL 0x04 /* DBLSEL 0 : SCLK Doubler Select */
502: /* 0 : */
503: /* 0 : */
504:
505: #define STEST2_SIZE 0x01
506: #define STEST2 0x0000004E
507: #define STEST2_INIT 0x00 /* Scsi Test register two */
508: #define STEST2_DIFF_INIT 0x20 /* Scsi Test register two */
509: #define SCE 0x80 /* SCE 0 : Scsi control enable */
510: #define ROF 0x40 /* ROF 0 : Reset Scsi offset */
511: #define DIF 0x20 /* DIF 0/1 : SCSI differential mode, set if we detect differential card */
512: #define SLB 0x10 /* SLB 0 : Scsi loopback mode */
513: #define SZM 0x08 /* SZM 0 : SCSI high impedance mode */
514: #define AWS 0x04 /* AWS 0 : Always wide SCSI */
515: #define EXT 0x02 /* EXT 0 : Extend REQ/ACK filtering NEVER want SET for 'fast'!!! */
516: #define LOW 0x01 /* LOW 0 : Scsi low level mode */
517:
518: #define STEST3_SIZE 0x01
519: #define STEST3 0x0000004F
520: #define STEST3_INIT 0x92 /* Scsi test register 3 */
521: #define EAN 0x80 /* EAN 1 : Enable active negation */
522: #define STR 0x40 /* STR 0 : Scsi FIFO test read */
523: #define HSC 0x20 /* HSC 0 : Halt Scsi Clock */
524: #define DSI 0x10 /* DSI 1 : Disable single initiator response */
525: /* RES */
526: #define TTM 0x04 /* TTM 0 : Timer test mode */
527: #define CSF 0x02 /* CSF 1 : Clear SCSI FIFO */
528: #define STW 0x01 /* STW 0 : SCSI FIFO test write */
529:
530: #define SSIDL_SIZE 0x02
531: #define SSIDL 0x00000050 /* SCSI input data latch Read only */
532:
533: #define SODL_SIZE 0x02
534: #define SODL 0x00000054
535: #define SODL_INIT 0x0000 /* SCSI Output Data Latch */
536:
537: #define SBDL_SIZE 0x02
538: #define SBDL 0x00000058 /* SCSI bus data line Read only */
539:
540: #define SCRATCHB_SIZE 0x04
541: #define SCRATCHB 0x0000005C
542: #define SCRATCHB0 0x0000005C
543: #define SCRATCHB1 0x0000005D
544: #define SCRATCHB2 0x0000005E
545: #define SCRATCHB3 0x0000005F
546: #define SCRATCHB_INIT 0x00000000 /* general purpose register */
547:
548: /* ************************* */
549:
550: /* Miscellaneous defines */
551: #define CLK_40MHz 40
552: #define CLK_80MHz 80
553: #define kResetRecoveryTimeMS 5000
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