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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: File: OHCIUIM.h
27:
28: Contains: Header file for OHCIUIM.c
29:
30: Version: xxx put version here xxx
31:
32: Written by: Guillermo Gallegos
33:
34: Copyright: � 1997-1998 by Apple Computer, Inc., all rights reserved.
35:
36: File Ownership:
37:
38: DRI: xxx put dri here xxx
39:
40: Other Contact: xxx put other contact here xxx
41:
42: Technology: xxx put technology here xxx
43:
44: Writers:
45:
46: (TC) Tom Clark
47: (DRF) Dave Falkenburg
48: (BG) Bill Galcher
49: (DF) David Ferguson
50: (DKF) David Ferguson
51: (GG) Guillermo Gallegos
52: (CJK) Craig Keithley
53: (BT) Barry Twycross
54:
55: Change History (most recent first):
56:
57: <USB41> 9/9/98 BT Fix size of refcon in Isoc transfers
58: <USB40> 9/3/98 GG Add Isochronous Suppurt for Create, Abort, Delete endpoint and
59: create transfers.
60: <USB39> 8/12/98 BT Move root hub back into UIM again.
61: <USB38> 8/7/98 GG Fixed Opti data corruption problem.
62: <USB37> 7/10/98 TC Back out <USB35>
63: <USB36> 6/30/98 BT Tidy up
64: <USB35> 6/30/98 BT Move Root hub sim into UIM
65: <USB34> 6/14/98 DF Add more Volatile keywords to the globals
66: <USB33> 6/4/98 DRF In UIMInitialize & UIMFinalize, add a Ptr to facilitate
67: handing-off global state when performing replacement.
68: <USB32> 6/3/98 GG Added kOHCIFrameOverflowBit for frame overflows.
69: <USB31> 6/2/98 GG Add interfaces for UIMFrameCount, IsochEndpointCreate, and
70: IsochTransfer.
71: <USB30> 6/2/98 DRF Added params to UIMInitialize & UIMFinalize for replacement.
72: <USB29> 5/18/98 BG Remove comma from final entry in enums so that they compile with
73: no complaints from MrC.
74: <USB28> 5/15/98 DF keep last pointer to the various descriptor free lists
75: <USB27> 5/14/98 GG Added some constants to support Buffer Underrun Errata fix.
76: <USB26> 5/14/98 DF Add retryBufferUnderrun errata
77: <USB25> 5/12/98 BT fix spare comma
78: <USB24> 5/5/98 GG Change Buffersize from short to unsigned long in
79: uimBulkTransfer.
80: <USB23> 5/2/98 DF Add volatile keyboard for variables updated by the interrupt
81: handler, also added stuff for erratas
82: <USB22> 4/29/98 BT Move common errors to USBpriv
83: <USB21> 4/24/98 GG Added support for bulk transfers greater than 4k. Added fix to
84: support to clear an endpoint stall.
85: <USB20> 4/9/98 BT Use USB.h
86: <19> 4/8/98 GG Added Abort and Delete APIs.
87: <18> 4/7/98 GG Added Abort and delete apis.
88: <17> 3/19/98 BT Split UIM into UIM and root hub parts
89: <16> 3/18/98 BT Add reset enable change to root hub.
90: <15> 3/18/98 GG Added some constants
91: <14> 3/11/98 BT More int transaction simualtion
92: <13> 2/25/98 GG Added kOHCIUIMUiniqueNoDir.
93: <12> 2/23/98 GG Moved interrupt structure, changed OHCIData struct to hold array
94: of InterruptHeads.
95: <11> 2/20/98 GG Added Interrupt Transfer Support.
96: <10> 2/19/98 GG Added Endpoint Creation Functionality.
97: <USB9> 2/17/98 DKF Add HW Interrupt related definitions and globals
98: <8> 2/12/98 GG Added Rom in Ram Memory management support.
99: <7> 2/2/98 BT Add bulk stuff
100: <6> 1/26/98 BT Hack in clear enpoint stall
101: <5> 12/22/97 CJK Add include of UIMSupport.h
102: <4> 12/19/97 BT Temp hack, Make it a shared lib
103: <4> 30/11/97 BT Various mods to get USL preveiw running
104: <2*> 11/20/97 GG Add callback parameter to bulk and control creators.
105: <2> 11/20/97 GG Filled in contains field. Initial check in has minimal support
106: for Root Hub, Control and Bulk transfers.
107: <1> 11/20/97 GG first checked in
108:
109: */
110:
111: /* IMPORTANT NOTES:
112: The generic UIM structures and typedefs needed by the Family Expert
113: have been moved to the UIMSupport.h file in the Neptune:Interfaces
114: folder. Any UIM typedefs or structs that are not OHCI specific
115: should be kept there, so that the family expert, etc., can have
116: access to them without needing to be hardware saavy.
117:
118: While that's the goal, the current reality is that some roothub
119: support is performed in the USL, with special roothub dispatch
120: entries needed for root hub functions. So until the roothub
121: simulation is implement in the UIM, you will find a small amount
122: of USL & OHCI related items in UIMSupport. These non-generic
123: UIM thangs will need to be removed when roothub simulation
124: moves from the USL to the UIM.
125: */
126:
127: #ifndef __OHCIUIM__
128: #define __OHCIUIM__
129:
130: #ifndef __TYPES__
131: //#include "types.h"
132: #endif
133: #ifndef __INTERRUPTS__
134: //#include "interrupts.h"
135: #endif
136:
137: #include "USBpriv.h"
138:
139: #ifdef __cplusplus
140: extern "C" {
141: #endif
142:
143: #if PRAGMA_IMPORT_SUPPORTED
144: #pragma import on
145: #endif
146:
147: #if PRAGMA_ALIGN_SUPPORTED
148: #pragma options align=power
149: #endif
150:
151: /*zzz*/
152: /* Isn't this PCI standard stuff? Shouldn't it be in some regular include */
153: /* file like PCI.h? */
154: //#include <PCI.h>
155:
156: #define bit0 0x00000001
157: #define bit1 0x00000002
158: #define bit2 0x00000004
159: #define bit3 0x00000008
160: #define bit4 0x00000010
161: #define bit5 0x00000020
162: #define bit6 0x00000040
163: #define bit7 0x00000080
164: #define bit8 0x00000100
165: #define bit9 0x00000200
166: #define bit10 0x00000400
167: #define bit11 0x00000800
168: #define bit12 0x00001000
169: #define bit13 0x00002000
170: #define bit14 0x00004000
171: #define bit15 0x00008000
172: #define bit16 0x00010000
173: #define bit17 0x00020000
174: #define bit18 0x00040000
175: #define bit19 0x00080000
176: #define bit20 0x00100000
177: #define bit21 0x00200000
178: #define bit22 0x00400000
179: #define bit23 0x00800000
180: #define bit24 0x01000000
181: #define bit25 0x02000000
182: #define bit26 0x04000000
183: #define bit27 0x08000000
184: #define bit28 0x10000000
185: #define bit29 0x20000000
186: #define bit30 0x40000000
187: #define bit31 0x80000000
188:
189: /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
190: * * * * * *
191: * Configuration Registers
192: *
193: */
194: enum {
195: kConfigStart = 0x00,
196: cwVendorID = 0x00, /* 0x1000 */
197: cwDeviceID = 0x02, /* 0x0003 */
198: cwCommand = 0x04,
199: cwStatus = 0x06,
200: clClassCodeAndRevID = 0x08,
201: clHeaderAndLatency = 0x0C,
202: clBaseAddressZero = 0x10, /* I/O Base address */
203: clBaseAddressOne = 0x14, /* Memory Base address */
204: clExpansionRomAddr = 0x30,
205: clLatGntIntPinLine = 0x3C, /* Max_Lat, Max_Gnt, Int. Pin, Int. Line */
206: kConfigEnd = 0x40
207: };
208:
209: /*
210: * 0x04 cwCommand Command Register (read/write)
211: */
212: enum {
213: cwCommandSERREnable = bit8,
214: cwCommandEnableParityError = bit6,
215: cwCommandEnableBusMaster = bit2, /* Set this on initialization */
216: cwCommandEnableMemorySpace = bit1, /* Respond at Base Address One if set */
217: cwCommandEnableIOSpace = bit0 /* Respond at Base Address Zero if set */
218: };
219: /*
220: * 0x06 cwStatus Status Register (read/write)
221: */
222: enum {
223: cwStatusDetectedParityError = bit15, /* Detected from slave */
224: cwStatusSignaledSystemError = bit14, /* Device asserts SERR/ signal */
225: cwStatusMasterAbort = bit13, /* Master sets when transaction aborts */
226: cwStatusReceivedTargetAbort = bit12, /* Master sets when target-abort */
227: cwStatusDEVSELTimingMask = (bit10 | bit9), /* DEVSEL timing encoding R/O */
228: cwStatusDEVSELFastTiming = 0,
229: cwStatusDEVSELMediumTiming = bit9,
230: cwStatusDEVSELSlowTiming = bit10,
231: cwStatusDataParityReported = bit8
232: };
233:
234: /*zzz*/
235:
236:
237: ////////////////////////////////////////////////////////////////////////////////
238: //
239: // Useful macro defs.
240: //
241:
242: #define EndianSwapImm32Bit(data32) \
243: ( \
244: (((UInt32) data32) >> 24) | \
245: ((((UInt32) data32) >> 8) & 0xFF00) | \
246: ((((UInt32) data32) << 8) & 0xFF0000) | \
247: (((UInt32) data32) << 24) \
248: )
249:
250: ////////////////////////////////////////////////////////////////////////////////
251: //
252: // OHCI type defs.
253: //
254:
255: typedef volatile struct OHCIRegistersStruct
256: OHCIRegisters,
257: *OHCIRegistersPtr;
258:
259: typedef struct OHCIIntHeadStruct
260: OHCIIntHead,
261: *OHCIIntHeadPtr;
262:
263: typedef struct OHCIEndpointDescriptorStruct
264: OHCIEndpointDescriptor,
265: *OHCIEndpointDescriptorPtr;
266:
267: typedef struct OHCIGeneralTransferDescriptorStruct
268: OHCIGeneralTransferDescriptor,
269: *OHCIGeneralTransferDescriptorPtr;
270:
271: typedef struct OHCIIsochTransferDescriptorStruct
272: OHCIIsochTransferDescriptor,
273: *OHCIIsochTransferDescriptorPtr;
274:
275: typedef struct OHCIUIMDataStruct
276: OHCIUIMData, *OHCIUIMDataPtr;
277:
278: typedef struct OHCIPhysicalLogicalStruct
279: OHCIPhysicalLogical,
280: *OHCIPhysicalLogicalPtr;
281:
282: typedef struct ErrataListEntryStruct
283: ErrataListEntry,
284: *ErrataListEntryPtr;
285:
286: ////////////////////////////////////////////////////////////////////////////////
287: //
288: // OHCI type defs.
289: // (moved to UIMSupport.h so that the Expert can use them as well.)
290:
291: ////////////////////////////////////////////////////////////////////////////////
292: //
293: // OHCI register file.
294: //
295:
296: enum
297: {
298: kOHCIBit0 = (1 << 0),
299: kOHCIBit1 = (1 << 1),
300: kOHCIBit2 = (1 << 2),
301: kOHCIBit3 = (1 << 3),
302: kOHCIBit4 = (1 << 4),
303: kOHCIBit5 = (1 << 5),
304: kOHCIBit6 = (1 << 6),
305: kOHCIBit7 = (1 << 7),
306: kOHCIBit8 = (1 << 8),
307: kOHCIBit9 = (1 << 9),
308: kOHCIBit10 = (1 << 10),
309: kOHCIBit11 = (1 << 11),
310: kOHCIBit12 = (1 << 12),
311: kOHCIBit13 = (1 << 13),
312: kOHCIBit14 = (1 << 14),
313: kOHCIBit15 = (1 << 15),
314: kOHCIBit16 = (1 << 16),
315: kOHCIBit17 = (1 << 17),
316: kOHCIBit18 = (1 << 18),
317: kOHCIBit19 = (1 << 19),
318: kOHCIBit20 = (1 << 20),
319: kOHCIBit21 = (1 << 21),
320: kOHCIBit22 = (1 << 22),
321: kOHCIBit23 = (1 << 23),
322: kOHCIBit24 = (1 << 24),
323: kOHCIBit25 = (1 << 25),
324: kOHCIBit26 = (1 << 26),
325: kOHCIBit27 = (1 << 27),
326: kOHCIBit28 = (1 << 28),
327: kOHCIBit29 = (1 << 29),
328: kOHCIBit30 = (1 << 30),
329: kOHCIBit31 = (1 << 31)
330: };
331:
332: #define OHCIBitRange(start, end) \
333: ( \
334: ((((UInt32) 0xFFFFFFFF) << (31 - (end))) >> \
335: ((31 - (end)) + (start))) << \
336: (start) \
337: )
338:
339: #define OHCIBitRangePhase(start, end) \
340: (start)
341:
342:
343: // OHCI register file.
344:
345: struct OHCIRegistersStruct
346: {
347: // Control and status group.
348: volatile UInt32 hcRevision;
349: volatile UInt32 hcControl;
350: volatile UInt32 hcCommandStatus;
351: volatile UInt32 hcInterruptStatus;
352: volatile UInt32 hcInterruptEnable;
353: volatile UInt32 hcInterruptDisable;
354:
355: // Memory pointer group.
356: volatile UInt32 hcHCCA;
357: volatile UInt32 hcPeriodCurrentED;
358: volatile UInt32 hcControlHeadED;
359: volatile UInt32 hcControlCurrentED;
360: volatile UInt32 hcBulkHeadED;
361: volatile UInt32 hcBulkCurrentED;
362: volatile UInt32 hcDoneHead;
363:
364: // Frame counter group.
365: volatile UInt32 hcFmInterval;
366: volatile UInt32 hcFmRemaining;
367: volatile UInt32 hcFmNumber;
368: volatile UInt32 hcPeriodicStart;
369: volatile UInt32 hcLSThreshold;
370:
371: // Root hub group.
372: volatile UInt32 hcRhDescriptorA;
373: volatile UInt32 hcRhDescriptorB;
374: volatile UInt32 hcRhStatus;
375: volatile UInt32 hcRhPortStatus[1];
376: };
377:
378: // hcControl register defs.
379: enum
380: {
381: kOHCIHcControl_CBSR = OHCIBitRange (0, 1),
382: kOHCIHcControl_CBSRPhase = OHCIBitRangePhase (0, 1),
383: kOHCIHcControl_PLE = kOHCIBit2,
384: kOHCIHcControl_IE = kOHCIBit3,
385: kOHCIHcControl_CLE = kOHCIBit4,
386: kOHCIHcControl_BLE = kOHCIBit5,
387: kOHCIHcControl_HCFS = OHCIBitRange (6, 7),
388: kOHCIHcControl_HCFSPhase = OHCIBitRangePhase (6, 7),
389: kOHCIHcControl_IR = kOHCIBit8,
390: kOHCIHcControl_RWC = kOHCIBit9,
391: kOHCIHcControl_RWE = kOHCIBit10,
392:
393: kOHCIHcControl_Reserved = OHCIBitRange (11, 31),
394:
395: kOHCIFunctionalState_Reset = 0,
396: kOHCIFunctionalState_Resume = 1,
397: kOHCIFunctionalState_Operational = 2,
398: kOHCIFunctionalState_Suspend = 3
399: };
400:
401: // hcCommandStatus register defs.
402: enum
403: {
404: kOHCIHcCommandStatus_HCR = kOHCIBit0,
405: kOHCIHcCommandStatus_CLF = kOHCIBit1,
406: kOHCIHcCommandStatus_BLF = kOHCIBit2,
407: kOHCIHcCommandStatus_OCR = kOHCIBit3,
408: kOHCIHcCommandStatus_SOC = OHCIBitRange (16, 17),
409: kOHCIHcCommandStatus_SOCPhase = OHCIBitRangePhase (16, 17),
410:
411: kOHCIHcCommandStatus_Reserved = OHCIBitRange (4, 15) | OHCIBitRange (18, 31)
412: };
413:
414: // hcInterrupt register defs.
415: enum
416: {
417: kOHCIHcInterrupt_SO = kOHCIBit0,
418: kOHCIHcInterrupt_WDH = kOHCIBit1,
419: kOHCIHcInterrupt_SF = kOHCIBit2,
420: kOHCIHcInterrupt_RD = kOHCIBit3,
421: kOHCIHcInterrupt_UE = kOHCIBit4,
422: kOHCIHcInterrupt_FNO = kOHCIBit5,
423: kOHCIHcInterrupt_RHSC = kOHCIBit6,
424: kOHCIHcInterrupt_OC = kOHCIBit30,
425: kOHCIHcInterrupt_MIE = kOHCIBit31
426: };
427:
428: // this is what I would like it to be
429: //#define kOHCIDefaultInterrupts (kOHCIHcInterrupt_SO | kOHCIHcInterrupt_WDH | kOHCIHcInterrupt_UE | kOHCIHcInterrupt_FNO | kOHCIHcInterrupt_RHSC)
430: #define kOHCIDefaultInterrupts (kOHCIHcInterrupt_WDH | kOHCIHcInterrupt_UE | kOHCIHcInterrupt_FNO)
431:
432:
433: // hcFmInterval register defs.
434: enum
435: {
436: kOHCIHcFmInterval_FI = OHCIBitRange (0, 13),
437: kOHCIHcFmInterval_FIPhase = OHCIBitRangePhase (0, 13),
438: kOHCIHcFmInterval_FSMPS = OHCIBitRange (16, 30),
439: kOHCIHcFmInterval_FSMPSPhase = OHCIBitRangePhase (16, 30),
440: kOHCIHcFmInterval_FIT = kOHCIBit31,
441:
442: kOHCIHcFmInterval_Reserved = OHCIBitRange (14, 15)
443: };
444:
445: // hcRhDescriptorA register defs.
446: enum
447: {
448: kOHCIHcRhDescriptorA_NDP = OHCIBitRange (0, 7),
449: kOHCIHcRhDescriptorA_NDPPhase = OHCIBitRangePhase (0, 7),
450: kOHCIHcRhDescriptorA_PSM = kOHCIBit8,
451: kOHCIHcRhDescriptorA_NPS = kOHCIBit9,
452: kOHCIHcRhDescriptorA_DT = kOHCIBit10,
453: kOHCIHcRhDescriptorA_OCPM = kOHCIBit11,
454: kOHCIHcRhDescriptorA_NOCP = kOHCIBit12,
455: kOHCIHcRhDescriptorA_POTPGT = OHCIBitRange (24, 31),
456: kOHCIHcRhDescriptorA_POTPGTPhase = OHCIBitRangePhase (24, 31),
457:
458: kOHCIHcRhDescriptorA_Reserved = OHCIBitRange (13,23)
459: };
460:
461: // Root hub sttaus reg
462:
463: // Barry, not moved to OHCIRootHub.h
464:
465:
466: // Port status reg
467:
468: // Barry, not moved to OHCIRootHub.h
469:
470:
471:
472: // Config space defs.
473: enum
474: {
475: kOHCIConfigRegBaseAddressRegisterNumber = 0x10
476: };
477:
478:
479: enum
480: {
481: kOHCIEDControl_FA = OHCIBitRange (0, 6),
482: kOHCIEDControl_FAPhase = OHCIBitRangePhase (0, 6),
483: kOHCIEDControl_EN = OHCIBitRange (7, 10),
484: kOHCIEDControl_ENPhase = OHCIBitRangePhase (7, 10),
485: kOHCIEDControl_D = OHCIBitRange (11, 12),
486: kOHCIEDControl_DPhase = OHCIBitRangePhase (11, 12),
487: kOHCIEDControl_S = OHCIBitRange (13, 13),
488: kOHCIEDControl_SPhase = OHCIBitRangePhase (13, 13),
489: kOHCIEDControl_K = kOHCIBit14,
490: kOHCIEDControl_F = OHCIBitRange (15, 15),
491: kOHCIEDControl_FPhase = OHCIBitRangePhase (15, 15),
492: kOHCIEDControl_MPS = OHCIBitRange (16, 26),
493: kOHCIEDControl_MPSPhase = OHCIBitRangePhase (16, 26),
494:
495: kOHCITailPointer_tailP = OHCIBitRange (4, 31),
496: kOHCITailPointer_tailPPhase = OHCIBitRangePhase (4, 31),
497:
498: kOHCIHeadPointer_H = kOHCIBit0,
499: kOHCIHeadPointer_C = kOHCIBit1,
500: kOHCIHeadPointer_headP = OHCIBitRange (4, 31),
501: kOHCIHeadPointer_headPPhase = OHCIBitRangePhase (4, 31),
502:
503: kOHCINextEndpointDescriptor_nextED = OHCIBitRange (4, 31),
504: kOHCINextEndpointDescriptor_nextEDPhase = OHCIBitRangePhase (4, 31),
505:
506: kOHCIEDDirectionTD = 0,
507: kOHCIEDDirectionOut = 1,
508: kOHCIEDDirectionIn = 2,
509:
510: kOHCIEDSpeedFull = 0,
511: kOHCIEDSpeedLow = 1,
512:
513: kOHCIEDFormatGeneralTD = 0,
514: kOHCIEDFormatIsochronousTD = 1
515: };
516:
517: // General Transfer Descriptor
518: enum
519: {
520: kOHCIGTDControl_R = kOHCIBit18,
521: kOHCIGTDControl_DP = OHCIBitRange (19, 20),
522: kOHCIGTDControl_DPPhase = OHCIBitRangePhase (19, 20),
523: kOHCIGTDControl_DI = OHCIBitRange (21, 23),
524: kOHCIGTDControl_DIPhase = OHCIBitRangePhase (21, 23),
525: kOHCIGTDControl_T = OHCIBitRange (24, 25),
526: kOHCIGTDControl_TPhase = OHCIBitRangePhase (24, 25),
527: kOHCIGTDControl_EC = OHCIBitRange (26, 27),
528: kOHCIGTDControl_ECPhase = OHCIBitRangePhase (26, 27),
529: kOHCIGTDControl_CC = OHCIBitRange (28, 31),
530: kOHCIGTDControl_CCPhase = OHCIBitRangePhase (28, 31),
531:
532: kOHCIGTDPIDSetup = 0,
533: kOHCIGTDPIDOut = 1,
534: kOHCIGTDPIDIn = 2,
535:
536: kOHCIGTDNoInterrupt = 7,
537:
538: kOHCIGTDDataToggleCarry = 0,
539: kOHCIGTDDataToggle0 = 2,
540: kOHCIGTDDataToggle1 = 3,
541:
542: kOHCIGTDConditionNoError = 0,
543: kOHCIGTDConditionCRC = 1,
544: kOHCIGTDConditionBitStuffing = 2,
545: kOHCIGTDConditionDataToggleMismatch = 3,
546: kOHCIGTDConditionStall = 4,
547: kOHCIGTDConditionDeviceNotResponding = 5,
548: kOHCIGTDConditionPIDCheckFailure = 6,
549: kOHCIGTDConditionUnexpectedPID = 7,
550: kOHCIGTDConditionDataOverrun = 8,
551: kOHCIGTDConditionDataUnderrun = 9,
552: kOHCIGTDConditionBufferOverrun = 12,
553: kOHCIGTDConditionBufferUnderrun = 13,
554: kOHCIGTDConditionNotAccessed = 15
555: };
556:
557: // Isochronous Transfer Descriptor
558: enum
559: {
560: kOHCIITDControl_SF = OHCIBitRange (0,15),
561: kOHCIITDControl_SFPhase = OHCIBitRangePhase(0,15),
562: kOHCIITDControl_DI = OHCIBitRange (21,23),
563: kOHCIITDControl_DIPhase = OHCIBitRangePhase (21,23),
564: kOHCIITDControl_FC = OHCIBitRange (24,26),
565: kOHCIITDControl_FCPhase = OHCIBitRangePhase (24,26),
566: kOHCIITDControl_CC = OHCIBitRange (28,31),
567: kOHCIITDControl_CCPhase = OHCIBitRangePhase (28,31),
568: kOHCIITDPSW_Size = OHCIBitRange(0,10),
569: kOHCIITDPSW_SizePhase = OHCIBitRangePhase(0,10),
570: kOHCIITDPSW_CC = OHCIBitRange(12,15),
571: kOHCIITDPSW_CCPhase = OHCIBitRangePhase(12,15),
572: kOHCIITDPSW_CCNA = OHCIBitRange(13,15),
573: kOHCIITDPSW_CCNAPhase = OHCIBitRangePhase(13,15),
574: kOHCIITDOffset_Size = OHCIBitRange(0,10),
575: kOHCIITDOffset_SizePhase = OHCIBitRangePhase(0,10),
576: kOHCIITDOffset_PC = OHCIBitRange(12,12),
577: kOHCIITDOffset_PCPhase = OHCIBitRangePhase(12,12),
578: kOHCIITDOffset_CC = OHCIBitRange(13,15),
579: kOHCIITDOffset_CCPhase = OHCIBitRangePhase(13,15),
580: kOHCIITDConditionNoError = 0,
581: kOHCIITDConditionCRC = 1,
582: kOHCIITDConditionBitStuffing = 2,
583: kOHCIITDConditionDataToggleMismatch = 3,
584: kOHCIITDConditionStall = 4,
585: kOHCIITDConditionDeviceNotResponding = 5,
586: kOHCIITDConditionPIDCheckFailure = 6,
587: kOHCIITDConditionUnExpectedPID = 7,
588: kOHCIITDConditionDataOverrun = 8,
589: kOHCIITDConditionDataUnderrun = 9,
590: kOHCIITDConditionBufferOverrun = 12,
591: kOHCIITDConditionBufferUnderrun = 13,
592: kOHCIITDConditionNotAccessed = 7,
593: kOHCIITDConditionNotAccessedReturn = 15,
594: kOHCIITDConditionNotCrossPage = 0,
595: kOHCIITDConditionCrossPage = 1
596: };
597:
598:
599:
600: // misc definitions -- most of these need to be cleaned up/replaced with better terms defined previously
601:
602: enum
603: {
604: // Barry, note - Root hub defines moved to OHCIRootHub.h
605:
606: kOHCIEndpointNumberOffset = 7,
607: kOHCIEndpointDirectionOffset = 11,
608: kOHCIMaxPacketSizeOffset = 16,
609: kOHCISpeedOffset = 13,
610: kOHCIBufferRoundingOffset = 18,
611: kOHCIDirectionOffset = 19,
612: kENOffset = 7,
613:
614: kUniqueNumMask = OHCIBitRange (0, 12),
615: kUniqueNumNoDirMask = OHCIBitRange (0, 10),
616: kOHCIHeadPMask = OHCIBitRange (4, 31),
617: kOHCIInterruptSOFMask = kOHCIHcInterrupt_SF,
618: kOHCISkipped = kOHCIEDControl_K,
619: kOHCIDelayIntOffset = 21,
620: kOHCIMaxPages = 20, //arbitrary value for #of pages to use in prepare memory for io
621: kOHCIPageSize = 4096,
622: kOHCIEndpointDirectionMask = OHCIBitRange (11, 12),
623: kOHCIEDToggleBitMask = OHCIBitRange (1, 1),
624: kOHCIGTDClearErrorMask = OHCIBitRange (0, 25)
625: };
626:
627:
628: // errataBits contents
629: enum {
630: kErrataCMDDisableTestMode = kOHCIBit0, // turn off UHCI test mode
631: kErrataOnlySinglePageTransfers = kOHCIBit1, // Don't cross page boundaries in a single transfer
632: kErrataRetryBufferUnderruns = kOHCIBit2, // UIM will retry out transfers with buffer underrun errors
633: kErrataLSHSOpti = kOHCIBit3 // UIM will insert delay buffer between HS and LS transfers
634: };
635:
636: enum {
637: kOHCIBulkTransferOutType = 1,
638: kOHCIBulkTransferInType = 2,
639: kOHCIControlSetupType = 3,
640: kOHCIControlDataType = 4,
641: kOHCIControlStatusType = 5,
642: kOHCIInterruptInType = 6,
643: kOHCIInterruptOutType = 7,
644: kOHCIOptiLSBug = 8,
645: kOHCIIsochronousType = 9
646: };
647:
648: enum {
649: kOHCIFrameOffset = 16,
650: kOHCIFmNumberMask = OHCIBitRange (0, 15),
651: kOHCIFrameOverflowBit = kOHCIBit16,
652: kOHCIMaxRetrys = 20
653:
654: };
655:
656: ////////////////////////////////////////////////////////////////////////////////
657: //
658: // OHCI UIM data records.
659: //
660:
661: typedef short RootHubID;
662:
663: // Interrupt head struct
664: struct OHCIIntHeadStruct
665: {
666: OHCIEndpointDescriptorPtr pHead;
667: OHCIEndpointDescriptorPtr pTail;
668: UInt32 pHeadPhysical;
669: int nodeBandwidth;
670: };
671: //naga
672: typedef int ohciRegEntryID;
673: struct OHCIUIMDataStruct
674: {
675: RegEntryID ohciRegEntryID; // Name Registry entry of OHCI.
676: // UIMID uimID; // ID for OHCI UIM.
677: RootHubID rootHubID; // Status of root hub, if 0, not initialized otherwise has virtual ID number
678: UInt32 errataBits; // various bits for chip erratas
679:
680: OHCIRegistersPtr pOHCIRegisters; // Pointer to base address of OHCI registers.
681: Ptr pHCCA, // Pointer to HCCA.
682: pHCCAAllocation; // Pointer to memory allocated for HCCA.
683: OHCIIntHead pInterruptHead[63]; // ptr to private list of all interrupts heads
684: volatile UInt32 pIsochHead; // ptr to Isochtonous list
685: volatile UInt32 pIsochTail; // ptr to Isochtonous list
686: volatile UInt32 pBulkHead; // ptr to Bulk list
687: volatile UInt32 pControlHead; // ptr to Control list
688: volatile UInt32 pBulkTail; // ptr to Bulk list
689: volatile UInt32 pControlTail; // ptr to Control list
690: volatile OHCIPhysicalLogicalPtr pPhysicalLogical; // ptr to list of memory maps
691: volatile OHCIGeneralTransferDescriptorPtr pFreeTD; // list of availabble Trasfer Descriptors
692: volatile OHCIIsochTransferDescriptorPtr pFreeITD; // list of availabble Trasfer Descriptors
693: volatile OHCIEndpointDescriptorPtr pFreeED; // list of available Endpoint Descriptors
694: volatile OHCIGeneralTransferDescriptorPtr pLastFreeTD; // last of availabble Trasfer Descriptors
695: volatile OHCIIsochTransferDescriptorPtr pLastFreeITD; // last of availabble Trasfer Descriptors
696: volatile OHCIEndpointDescriptorPtr pLastFreeED; // last of available Endpoint Descriptors
697: volatile OHCIGeneralTransferDescriptorPtr pPendingTD; // list of non processed Trasfer Descriptors
698:
699: UInt32 pageSize; // OS Logical page size
700:
701: InterruptSetMember interruptSetMember;
702: void *oldInterruptRefCon;
703: InterruptHandler oldInterruptHandler;
704: InterruptEnabler interruptEnabler;
705: InterruptDisabler interruptDisabler;
706: struct {
707: volatile UInt32 scheduleOverrun; // updated by the interrupt handler
708: volatile UInt32 unrecoverableError; // updated by the interrupt handler
709: volatile UInt32 frameNumberOverflow; // updated by the interrupt handler
710: volatile UInt32 ownershipChange; // updated by the interrupt handler
711: } errors;
712: volatile UInt64 frameNumber;
713: UInt16 rootHubFuncAddress; // Funciotn Address for the root hub
714: int OptiOn;
715:
716: };
717:
718: struct OHCIEndpointDescriptorStruct
719: {
720: UInt32 dWord0; // control
721: UInt32 dWord1; // pointer to last TD
722: UInt32 dWord2; // pointer to first TD
723: UInt32 dWord3; // Pointer to next ED
724: UInt32 pVirtualNext;
725: UInt32 pPhysical;
726: UInt32 pVirtualTailP;
727: UInt32 pVirtualHeadP;
728: };
729: struct OHCIGeneralTransferDescriptorStruct
730: {
731: volatile UInt32 dWord0; // Data controlling transfer.
732: volatile UInt32 dWord1; // Current buffer pointer.
733: volatile UInt32 dWord2; // Pointer to next transfer descriptor.
734: UInt32 dWord3; // Pointer to end of buffer.
735: CallBackFuncPtr CallBack; // only used if last TD, other wise its nil
736: long refcon; //
737: UInt32 pPhysical;
738: UInt32 pVirtualNext;
739: UInt32 pType;
740: UInt32 pEndpoint; // pointer to TD's Endpoint
741: UInt32 bufferSize; // used only by control transfers to keep track of data buffers size leftover
742: IOPreparationID preparationID; // used for CheckpointIO
743: };
744:
745: struct OHCIIsochTransferDescriptorStruct
746: {
747: UInt32 dWord0; // Condition code/FrameCount/DelayInterrrupt/StartingFrame.
748: UInt32 dWord1; // Buffer Page 0.
749: UInt32 dWord2; // Pointer to next transfer descriptor.
750: UInt32 dWord3; // Pointer to end of buffer.
751: UInt16 offset[8];
752: /*
753: UInt32 dWord4; // offset1/PSW1 - offset0/PSW0
754: UInt32 dWord5; // offset3/PSW3 - offset2/PSW2
755: UInt32 dWord6; // offset5/PSW5 - offset4/PSW4
756: UInt32 dWord7; // offset7/PSW7 - offset6/PSW6
757: */
758: UInt32 pType; // type of descriptor, must always be in this position
759: IsocCallBackFuncPtr handler; // callback for Isoch transactions
760: UInt32 pPhysical; // physical address of ITD
761: UInt32 pVirtualNext; // virtual ptr to next ITD
762: UInt32 pIsocFrame; // ptr to USLs status and length array
763: UInt32 refcon; // callback reference
764: UInt32 frameNum; // index to pIsocFrame array
765: UInt32 reserve2; //
766: };
767:
768: struct OHCIPhysicalLogicalStruct
769: {
770: UInt32 LogicalStart;
771: UInt32 LogicalEnd;
772: UInt32 PhysicalStart;
773: UInt32 PhysicalEnd;
774: UInt32 type;
775: UInt32 pNext;
776:
777: };
778:
779: struct ErrataListEntryStruct {
780: UInt16 vendID;
781: UInt16 deviceID;
782: UInt16 revisionLo;
783: UInt16 revisionHi;
784: UInt32 errata;
785: };
786:
787:
788: //Globals -yuck (Barry, made more global to share with root hub)
789:
790:
791:
792:
793:
794: int OHCIUIMInitialize(unsigned long);
795:
796: OSStatus OHCIUIMFinalize(
797: Boolean beingReplaced,
798: Ptr * savedStatePtr);
799:
800: OSStatus OHCIUIMControlEDCreate(
801: UInt8 functionNumber,
802: UInt8 endpointNumber,
803: UInt16 maxPacketSize,
804: UInt8 speed);
805:
806: OSStatus OHCIUIMControlTransfer(
807: UInt32 refcon,
808: CallBackFuncPtr handler,
809: UInt32 CBP,
810: Boolean bufferRounding,
811: short functionNumber,
812: short endpointNumber,
813: short bufferSize,
814: short direction);
815:
816: OSStatus OHCIUIMControlEDDelete(
817: short functionNumber,
818: short endpointNumber);
819:
820: OSStatus OHCIUIMClearEndPointStall(
821: short functionNumber,
822: short endpointNumber,
823: short direction);
824:
825: OSStatus OHCIUIMBulkEDCreate(
826: UInt8 functionAddress,
827: UInt8 endpointNumber,
828: UInt8 maxPacketSize,
829: UInt8 speed);
830:
831: OSStatus OHCIUIMBulkTransfer(
832: UInt32 refcon,
833: CallBackFuncPtr handler,
834: UInt32 CBP,
835: Boolean bufferRounding,
836: short functionNumber,
837: short endpointNumber,
838: UInt32 bufferSize,
839: short direction);
840:
841: OSStatus OHCIUIMBulkEDDelete(
842: short functionNumber,
843: short endpointNumber,
844: short direction);
845:
846: OSStatus OHCIUIMInterruptEDCreate(
847: short functionNumber,
848: short endPointNumber,
849: short speed,
850: UInt16 maxPacketSize,
851: short pollingRate,
852: UInt32 reserveBandwidth);
853:
854: OSStatus OHCIUIMInterruptTransfer(
855: short functionNumber,
856: short endpointNumber,
857: UInt32 refcon,
858: CallBackFuncPtr handler,
859: UInt32 CBP,
860: Boolean bufferRounding,
861: short bufferSize);
862:
863: OSStatus OHCIProcessDoneQueue(void);
864:
865: OSStatus OHCIUIMAbortEndpoint(
866: short functionNumber,
867: short endpointNumber,
868: short direction);
869:
870: OSStatus OHCIUIMEndpointDelete(
871: short functionNumber,
872: short endpointNumber,
873: short direction);
874:
875: UInt64 OHCIUIMGetCurrentFrameNumber(void);
876:
877: OSStatus OHCIUIMIsochEDCreate(
878: short functionAddress,
879: short endpointNumber,
880: UInt32 maxPacketSize,
881: UInt8 direction);
882:
883: OSStatus OHCIUIMIsochTransfer(
884: short functionAddress,
885: short endpointNumber,
886: UInt32 refcon,
887: UInt8 direction,
888: IsocCallBackFuncPtr pIsochHandler,
889: UInt64 frameNumberStart,
890: UInt32 pBufferStart,
891: UInt32 frameCount,
892: USBIsocFrame *pFrames);
893:
894: // BT Root hub internal functions
895:
896: OSStatus RootHubFrame(void *p1, void *p2);
897: OSStatus RootHubStatusChange(void *p1, void *p2);
898:
899: Boolean OHCISetOurAddress(uslBusRef bus, UInt16 addr);
900:
901: void OHCISetFrameInterrupt(void);
902: OSStatus UIMSimulateRootHubStages(
903: UInt32 refcon,
904: CallBackFuncPtr handler,
905: UInt32 CBP,
906: Boolean bufferRounding,
907: short endpointNumber,
908: short bufferSize,
909: short direction);
910:
911: void SimulateRootHubInt(UInt8 endpoint, UInt8 *buf, UInt32 bufLen,
912: CallBackFuncPtr handler, UInt32 refCon);
913:
914: void OHCIPollRootHubSim(uslBusRef bus);
915:
916: void ResetRootHubSimulation(void);
917:
918: #if PRAGMA_ALIGN_SUPPORTED
919: #pragma options align=reset
920: #endif
921:
922: #if PRAGMA_IMPORT_SUPPORTED
923: #pragma import off
924: #endif
925:
926: #ifdef __cplusplus
927: }
928: #endif
929:
930: #endif /* __OHCIUIM__ */
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