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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: //#import <mach/std_types.h>
26: #import <kernserv/ns_timer.h>
27: #import <driverkit/IODirectDevice.h>
28: #import <driverkit/ppc/IOPCIDevice.h>
29: #import <driverkit/IOPower.h>
30: #import <machdep/ppc/proc_reg.h>
31: #define kSAFE_USB_KMEMSIZE 2 * 1024 //"safe" amount to kalloc() for USB
32: #define bit0 0x00000001
33: #define bit1 0x00000002
34: #define bit2 0x00000004
35: #define bit3 0x00000008
36: #define bit4 0x00000010
37: #define bit5 0x00000020
38: #define bit6 0x00000040
39: #define bit7 0x00000080
40: #define bit8 0x00000100
41: #define bit9 0x00000200
42: #define bit10 0x00000400
43: #define bit11 0x00000800
44: #define bit12 0x00001000
45: #define bit13 0x00002000
46: #define bit14 0x00004000
47: #define bit15 0x00008000
48: #define bit16 0x00010000
49: #define bit17 0x00020000
50: #define bit18 0x00040000
51: #define bit19 0x00080000
52: #define bit20 0x00100000
53: #define bit21 0x00200000
54: #define bit22 0x00400000
55: #define bit23 0x00800000
56: #define bit24 0x01000000
57: #define bit25 0x02000000
58: #define bit26 0x04000000
59: #define bit27 0x08000000
60: #define bit28 0x10000000
61: #define bit29 0x20000000
62: #define bit30 0x40000000
63: #define bit31 0x80000000
64:
65: ////////////////////////////////////////////////////////////////////////////////
66: //
67: // OHCI register file.
68: //
69:
70: enum
71: {
72: kOHCIBit0 = (1 << 0),
73: kOHCIBit1 = (1 << 1),
74: kOHCIBit2 = (1 << 2),
75: kOHCIBit3 = (1 << 3),
76: kOHCIBit4 = (1 << 4),
77: kOHCIBit5 = (1 << 5),
78: kOHCIBit6 = (1 << 6),
79: kOHCIBit7 = (1 << 7),
80: kOHCIBit8 = (1 << 8),
81: kOHCIBit9 = (1 << 9),
82: kOHCIBit10 = (1 << 10),
83: kOHCIBit11 = (1 << 11),
84: kOHCIBit12 = (1 << 12),
85: kOHCIBit13 = (1 << 13),
86: kOHCIBit14 = (1 << 14),
87: kOHCIBit15 = (1 << 15),
88: kOHCIBit16 = (1 << 16),
89: kOHCIBit17 = (1 << 17),
90: kOHCIBit18 = (1 << 18),
91: kOHCIBit19 = (1 << 19),
92: kOHCIBit20 = (1 << 20),
93: kOHCIBit21 = (1 << 21),
94: kOHCIBit22 = (1 << 22),
95: kOHCIBit23 = (1 << 23),
96: kOHCIBit24 = (1 << 24),
97: kOHCIBit25 = (1 << 25),
98: kOHCIBit26 = (1 << 26),
99: kOHCIBit27 = (1 << 27),
100: kOHCIBit28 = (1 << 28),
101: kOHCIBit29 = (1 << 29),
102: kOHCIBit30 = (1 << 30),
103: kOHCIBit31 = (1 << 31)
104: };
105:
106:
107: #ifdef OMIT
108: #ifndef __APPLE_TYPES_DEFINED__
109: #define __APPLE_TYPES_DEFINED__ 1
110:
111: typedef unsigned int UInt32; // A 32-bit unsigned integer
112: typedef unsigned char UInt8; // A "byte-sized" integer
113: typedef signed char SInt8;
114: typedef signed int SInt32; // A 32-bit signed integer
115: typedef boolean_t Boolean; // TRUE/FALSE value (YES/NO in NeXT)
116: typedef signed int OSErr;
117: typedef signed int OSStatus;
118:
119: #endif /* __APPLE_TYPES_DEFINED__ */
120: #endif
121:
122:
123: typedef long InterruptMemberNumber;
124: typedef Boolean InterruptSourceState;
125:
126: //typedef InterruptSourceState (*InterruptDisabler)(InterruptSetMember ISTmember, void *refCon);
127: typedef InterruptSourceState (*InterruptDisabler)(void *ISTmember, void *refCon);
128:
129: //typedef InterruptMemberNumber (*InterruptHandler)(InterruptSetMember ISTmember, void *refCon, UInt32 theIntCount);
130: typedef InterruptMemberNumber (*InterruptHandler)(void *ISTmember, void *refCon, UInt32 theIntCount);
131:
132: //typedef void (*InterruptEnabler)(InterruptSetMember ISTmember, void *refCon);
133: typedef void (*InterruptEnabler)(void *ISTmember, void *refCon); //fake it since I can't find InterruptSetMember
134:
135: /** Can't find OpaqueRef anywhere
136: typedef struct OpaqueRef *KernelID;
137: typedef KernelID InterruptSetID; //A.W. doesn't seem that useful in C code
138:
139: From Bill's DriverServices.h
140: struct InterruptSetMember {
141: InterruptSetID setID;
142: InterruptMemberNumber member;
143: };
144:
145: typedef struct InterruptSetMember InterruptSetMember;
146:
147: enum {
148: kISTChipInterruptSource = 0,
149: kISTOutputDMAInterruptSource = 1,
150: kISTInputDMAInterruptSource = 2,
151: kISTPropertyMemberCount = 3
152: };
153:
154:
155: typedef InterruptSetMember ISTProperty[3];
156: ****/
157:
158:
159:
160: #define OHCIBitRange(start, end) \
161: ( \
162: ((((UInt32) 0xFFFFFFFF) << (31 - (end))) >> \
163: ((31 - (end)) + (start))) << \
164: (start) \
165: )
166:
167: #define OHCIBitRangePhase(start, end) \
168: (start)
169:
170:
171:
172: #define EndianSwapImm32Bit(data32) \
173: ( \
174: (((UInt32) data32) >> 24) | \
175: ((((UInt32) data32) >> 8) & 0xFF00) | \
176: ((((UInt32) data32) << 8) & 0xFF0000) | \
177: (((UInt32) data32) << 24) \
178: )
179:
180: typedef struct OHCIRegistersStruct
181: OHCIRegisters,
182: *OHCIRegistersPtr;
183:
184: typedef struct OHCIEndpointDescriptorStruct
185: OHCIEndpointDescriptor,
186: *OHCIEndpointDescriptorPtr;
187:
188: typedef struct OHCIGeneralTransferDescriptorStruct
189: OHCIGeneralTransferDescriptor,
190: *OHCIGeneralTransferDescriptorPtr;
191:
192:
193: struct OHCIPhysicalLogicalStruct
194: {
195: UInt32 LogicalStart;
196: UInt32 LogicalEnd;
197: UInt32 PhysicalStart;
198: UInt32 PhysicalEnd;
199: UInt32 type;
200: UInt32 pNext;
201:
202: };
203:
204:
205:
206: typedef struct OHCIPhysicalLogicalStruct
207: OHCIPhysicalLogical,
208: *OHCIPhysicalLogicalPtr;
209:
210:
211:
212:
213: // OHCI register file.
214: // The following fields exactly match the OHCI hardware registers
215: // (page 5-1 of CMD specs)
216: struct OHCIRegistersStruct
217: {
218: // Control and status group.
219: volatile UInt32 hcRevision;
220: volatile UInt32 hcControl;
221: volatile UInt32 hcCommandStatus;
222: volatile UInt32 hcInterruptStatus;
223: volatile UInt32 hcInterruptEnable;
224: volatile UInt32 hcInterruptDisable;
225:
226: // Memory pointer group.
227: volatile UInt32 hcHCCA;
228: volatile UInt32 hcPeriodCurrentED;
229: volatile UInt32 hcControlHeadED;
230: volatile UInt32 hcControlCurrentED;
231: volatile UInt32 hcBulkHeadED;
232: volatile UInt32 hcBulkCurrentED;
233: volatile UInt32 hcDoneHead;
234:
235: // Frame counter group.
236: volatile UInt32 hcFmInterval;
237: volatile UInt32 hcFmRemaining;
238: volatile UInt32 hcFmNumber;
239: volatile UInt32 hcPeriodicStart;
240: volatile UInt32 hcLSThreshold;
241:
242: // Root hub group.
243: volatile UInt32 hcRhDescriptorA;
244: volatile UInt32 hcRhDescriptorB;
245: volatile UInt32 hcRhStatus;
246: volatile UInt32 hcRhPortStatus[2];
247: };
248:
249: // hcControl register defs.
250: enum
251: {
252: kOHCIHcControl_CBSR = OHCIBitRange (0, 1),
253: kOHCIHcControl_CBSRPhase = OHCIBitRangePhase (0, 1),
254: kOHCIHcControl_PLE = kOHCIBit2,
255: kOHCIHcControl_IE = kOHCIBit3,
256: kOHCIHcControl_CLE = kOHCIBit4,
257: kOHCIHcControl_BLE = kOHCIBit5,
258: kOHCIHcControl_HCFS = OHCIBitRange (6, 7),
259: kOHCIHcControl_HCFSPhase = OHCIBitRangePhase (6, 7),
260: kOHCIHcControl_IR = kOHCIBit8,
261: kOHCIHcControl_RWC = kOHCIBit9,
262: kOHCIHcControl_RWE = kOHCIBit10,
263:
264: kOHCIHcControl_Reserved = OHCIBitRange (11, 31),
265:
266: kOHCIFunctionalState_Reset = 0,
267: kOHCIFunctionalState_Resume = 1,
268: kOHCIFunctionalState_Operational = 2,
269: kOHCIFunctionalState_Suspend = 3
270: };
271:
272: // hcCommandStatus register defs.
273: enum
274: {
275: kOHCIHcCommandStatus_HCR = kOHCIBit0,
276: kOHCIHcCommandStatus_CLF = kOHCIBit1,
277: kOHCIHcCommandStatus_BLF = kOHCIBit2,
278: kOHCIHcCommandStatus_OCR = kOHCIBit3,
279: kOHCIHcCommandStatus_SOC = OHCIBitRange (16, 17),
280: kOHCIHcCommandStatus_SOCPhase = OHCIBitRangePhase (16, 17),
281:
282: kOHCIHcCommandStatus_Reserved = OHCIBitRange (4, 15) | OHCIBitRange (18, 31)
283: };
284:
285: // hcInterrupt register defs.
286: enum
287: {
288: kOHCIHcInterrupt_SO = kOHCIBit0,
289: kOHCIHcInterrupt_WDH = kOHCIBit1,
290: kOHCIHcInterrupt_SF = kOHCIBit2,
291: kOHCIHcInterrupt_RD = kOHCIBit3,
292: kOHCIHcInterrupt_UE = kOHCIBit4,
293: kOHCIHcInterrupt_FNO = kOHCIBit5,
294: kOHCIHcInterrupt_RHSC = kOHCIBit6,
295: kOHCIHcInterrupt_OC = kOHCIBit30,
296: kOHCIHcInterrupt_MIE = kOHCIBit31
297: };
298:
299: /* ******************************************************************************
300: **
301: ** RegEntryID : The Global x-Namespace Entry Identifier
302: //
303: */
304: /* These are borrowed from nameregistry.h */
305: /* Naga Longterm: Better merge this with nameregistry.h */
306: struct RegEntryID {
307: UInt8 opaque[16];
308: };
309: typedef struct RegEntryID RegEntryID, *RegEntryIDPtr;
310: typedef UInt32 RegPropertyValueSize;
311: typedef char RegPropertyName;
312:
313: ////////////////////////////////////////////////////////////////////////////////
314: //
315: // OHCI UIM data records.
316: //
317:
318: typedef short RootHubID;
319:
320: // Interrupt head struct
321: struct OHCIIntHeadStruct
322: {
323: OHCIEndpointDescriptorPtr pHead;
324: OHCIEndpointDescriptorPtr pTail;
325: UInt32 pHeadPhysical;
326: int nodeBandwidth;
327: };
328:
329: typedef struct OHCIIntHeadStruct
330: OHCIIntHead,
331: *OHCIIntHeadPtr;
332:
333:
334: struct OHCIUIMDataStruct
335: {
336: RegEntryID ohciRegEntryID; // Name Registry entry of OHCI.
337: // UIMID uimID; // ID for OHCI UIM.
338: RootHubID rootHubID; // Status of root hub, if 0, not enitialized otherwise has virtual ID number
339:
340: OHCIRegistersPtr pOHCIRegisters; // Pointer to base address of OHCI registers.
341: Ptr pHCCA, // Pointer to HCCA.
342: pHCCAAllocation; // Pointer to memory allocated for HCCA.
343: OHCIIntHead pInterruptHead[64]; // ptr to private list of all interrupts heads
344: UInt32 pIsochHead; // ptr to Isochtonous list
345: UInt32 pBulkHead; // ptr to Bulk list
346: UInt32 pControlHead; // ptr to Control list
347: OHCIPhysicalLogicalPtr pPhysicalLogical; // ptr to list of memory maps
348: OHCIGeneralTransferDescriptorPtr pFreeTD; // list of Availabble Trasfer Descriptors
349: OHCIEndpointDescriptorPtr pFreeED; // List of available Endpoint Descriptors
350: OHCIGeneralTransferDescriptorPtr pPendingTD; // list of non processed Trasfer Descriptors
351:
352: UInt32 pageSize;
353:
354: // can't find includes for opaque InterruptSetMember interruptSetMember;
355: void *oldInterruptRefCon;
356: InterruptHandler oldInterruptHandler;
357: InterruptEnabler interruptEnabler;
358: InterruptDisabler interruptDisabler;
359: struct {
360: UInt32 scheduleOverrun;
361: UInt32 unrecoverableError;
362: UInt32 frameNumberOverflow;
363: UInt32 ownershipChange;
364: } errors;
365:
366: };
367:
368:
369: typedef struct OHCIUIMDataStruct
370: OHCIUIMData,
371: *OHCIUIMDataPtr;
372:
373:
374: struct OHCIEndpointDescriptorStruct
375: {
376: UInt32 dWord0; // control
377: UInt32 dWord1; // pointer to last TD
378: UInt32 dWord2; // pointer to first TD
379: UInt32 dWord3; // Pointer to next ED
380: UInt32 pVirtualNext;
381: UInt32 pPhysical;
382: UInt32 pVirtualTailP;
383: UInt32 pVirtualHeadP;
384: };
385:
386: struct OHCIGeneralTransferDescriptorStruct
387: {
388: volatile UInt32 dWord0; // Data controlling transfer.
389: volatile UInt32 dWord1; // Current buffer pointer.
390: volatile UInt32 dWord2; // Pointer to next transfer descriptor.
391: UInt32 dWord3; // Pointer to end of buffer.
392: //WARNING... remove for now, can't find #include anywhere CallBackFuncPtr CallBack; // only used if last TD, other wise its nil
393: long refcon; //
394: UInt32 pPhysical;
395: UInt32 pVirtualNext;
396: UInt32 pIntBack;
397: UInt32 pEndpoint; // pointer to TD's Endpoint
398: UInt32 bufferSize; // used only by control transfers to keep track of data buffers size leftover
399: UInt32 reserved2; //
400: };
401:
402: @interface AppleUSBCMD:IODirectDevice
403: {
404:
405: unsigned long ioBase; // USB Host Controller registers base
406: port_t port; // our interrupt port
407: id theirId; // ADB client's id for input callback
408: unsigned int reg_HcFmInterval, reg_HcCommandStatus, reg_HcControl;
409: //Globals -yuck from MacOS OHCIUIM.c
410:
411:
412: }
413:
414:
415: + (Boolean)probe : (IOPCIDevice *) devDesc; // initialize the driver
416:
417: - initFromDeviceDescription : (IODeviceDescription *)deviceDescription;
418:
419: //- (Boolean)enableCMDChip;
420: //- (Boolean) SetupHCDLists;
421: - free;
422:
423: - (unsigned int) getADBKeyboardID;
424:
425: - (void)interruptOccurred;
426:
427: @end
428:
429:
430:
431:
432:
433:
434:
435:
436:
437:
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