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Annotation of kernel/machdep/i386/dma.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
        !             3:  *
        !             4:  * @APPLE_LICENSE_HEADER_START@
        !             5:  * 
        !             6:  * Portions Copyright (c) 1999 Apple Computer, Inc.  All Rights
        !             7:  * Reserved.  This file contains Original Code and/or Modifications of
        !             8:  * Original Code as defined in and that are subject to the Apple Public
        !             9:  * Source License Version 1.1 (the "License").  You may not use this file
        !            10:  * except in compliance with the License.  Please obtain a copy of the
        !            11:  * License at http://www.apple.com/publicsource and read it before using
        !            12:  * this file.
        !            13:  * 
        !            14:  * The Original Code and all software distributed under the License are
        !            15:  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
        !            16:  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
        !            17:  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
        !            18:  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
        !            19:  * License for the specific language governing rights and limitations
        !            20:  * under the License.
        !            21:  * 
        !            22:  * @APPLE_LICENSE_HEADER_END@
        !            23:  */
        !            24: 
        !            25: /*
        !            26:  * Copyright (c) 1992 NeXT Computer, Inc.
        !            27:  *
        !            28:  * 8237A DMA Controller definitions.
        !            29:  *
        !            30:  * HISTORY
        !            31:  *
        !            32:  * 30 May 1992 ? at NeXT
        !            33:  *     Created.
        !            34:  */
        !            35: 
        !            36: /*
        !            37:  * Command register.
        !            38:  */
        !            39: typedef struct {
        !            40:     unsigned char
        !            41:                                        :2,
        !            42:                        chip_disbl      :1,
        !            43:                                        :1,
        !            44:                        priority        :1,
        !            45: #define DMA_PRIO_FIXED         0
        !            46: #define DMA_PRIO_ROTATING      1
        !            47:                                        :1,
        !            48:                        dreq_sense      :1,
        !            49: #define DMA_DREQ_ACT_HIGH      0
        !            50: #define DMA_DREQ_ACT_LOW       1
        !            51:                        dack_sense      :1;
        !            52: #define DMA_DACK_ACT_LOW       0
        !            53: #define DMA_DACK_ACT_HIGH      1
        !            54: } dma_cmd_reg_t;
        !            55: 
        !            56: /*
        !            57:  * Mode register.
        !            58:  */
        !            59: typedef struct {
        !            60:     unsigned char
        !            61:                        chan_sel        :2,
        !            62: #define DMA_CHAN0_SEL          0
        !            63: #define DMA_CHAN1_SEL          1
        !            64: #define DMA_CHAN2_SEL          2
        !            65: #define DMA_CHAN3_SEL          3
        !            66:                        xfer_dir        :2,
        !            67: #define DMA_XFER_VERIFY                0
        !            68: #define DMA_XFER_WRITE         1
        !            69: #define DMA_XFER_READ          2
        !            70:                        autoinit        :1,
        !            71:                        adrs_dir        :1,
        !            72: #define DMA_ADRS_INCR          0
        !            73: #define DMA_ADRS_DECR          1
        !            74:                        xfer_mode       :2;
        !            75: #define DMA_MODE_DEMAND                0
        !            76: #define DMA_MODE_SINGLE                1
        !            77: #define DMA_MODE_BLOCK         2
        !            78: #define DMA_MODE_CASCADE       3
        !            79: } dma_mode_reg_t;
        !            80: 
        !            81: /*
        !            82:  * Request register.
        !            83:  */
        !            84: typedef struct {
        !            85:     unsigned char
        !            86:                        chan_sel        :2,
        !            87:                        req             :1,
        !            88: #define DMA_REQ_RESET          0
        !            89: #define DMA_REQ_SET            1
        !            90:                                        :5;
        !            91: } dma_req_reg_t;
        !            92: 
        !            93: /*
        !            94:  * Mask register.
        !            95:  */
        !            96: typedef struct {
        !            97:     unsigned char
        !            98:                        chan_sel        :2,
        !            99:                        mask            :1,
        !           100: #define DMA_MASK_CLEAR         0
        !           101: #define DMA_MASK_SET           1
        !           102:                                        :5;
        !           103: } dma_mask_reg_t;
        !           104: 
        !           105: /*
        !           106:  * Status register.
        !           107:  */
        !           108: typedef struct {
        !           109:     unsigned char
        !           110:                        chan0_done      :1,
        !           111:                        chan1_done      :1,
        !           112:                        chan2_done      :1,
        !           113:                        chan3_done      :1,
        !           114:                        chan0_req       :1,
        !           115:                        chan1_req       :1,
        !           116:                        chan2_req       :1,
        !           117:                        chan3_req       :1;
        !           118: } dma_status_reg_t;
        !           119: 
        !           120: /*
        !           121:  * Extended mode register (EISA only).
        !           122:  */
        !           123: typedef struct {
        !           124:     unsigned char
        !           125:                                chan_sel        :2,
        !           126:                                xfer_width      :2,
        !           127: #define DMA_XFR_8_BIT          0
        !           128: #define DMA_XFR_16_BIT_WORD    1
        !           129: #define DMA_XFR_32_BIT         2
        !           130: #define DMA_XFR_16_BIT_BYTE    3
        !           131:        
        !           132:                                dma_timing      :2,
        !           133: #define DMA_TIMING_COMPAT      0
        !           134: #define DMA_TIMING_A           1
        !           135: #define DMA_TIMING_B           2
        !           136: #define DMA_TIMING_BURST       3
        !           137: 
        !           138:                                eop_io          :1,
        !           139: #define        DMA_EOP_OUT             0
        !           140: #define        DMA_EOP_IN              1
        !           141:                                stop_enable     :1;
        !           142: #define DMA_STOP_DISABLE       0
        !           143: #define DMA_STOP_ENABLE                1
        !           144: 
        !           145: } dma_extend_mode_reg_t;
        !           146: 
        !           147: /*
        !           148:  * DMA I/O Ports.
        !           149:  */
        !           150: 
        !           151: /*
        !           152:  * Master device.
        !           153:  */
        !           154: #define DMA_CHAN0_ADDR_PORT    0x0000
        !           155: #define DMA_CHAN0_COUNT_PORT   0x0001
        !           156: #define DMA_CHAN1_ADDR_PORT    0x0002
        !           157: #define DMA_CHAN1_COUNT_PORT   0x0003
        !           158: #define DMA_CHAN2_ADDR_PORT    0x0004
        !           159: #define DMA_CHAN2_COUNT_PORT   0x0005
        !           160: #define DMA_CHAN3_ADDR_PORT    0x0006
        !           161: #define DMA_CHAN3_COUNT_PORT   0x0007
        !           162: 
        !           163: #define DMA_CHAN0_PAGE_PORT    0x0087
        !           164: #define DMA_CHAN1_PAGE_PORT    0x0083
        !           165: #define DMA_CHAN2_PAGE_PORT    0x0081
        !           166: #define DMA_CHAN3_PAGE_PORT    0x0082
        !           167: 
        !           168: // HICOUNT (bits 23:16): EISA Only
        !           169: #define DMA_CHAN0_HICOUNT_PORT 0x0401
        !           170: #define DMA_CHAN1_HICOUNT_PORT 0x0403
        !           171: #define DMA_CHAN2_HICOUNT_PORT 0x0405
        !           172: #define DMA_CHAN3_HICOUNT_PORT 0x0407
        !           173: 
        !           174: // HIPAGE (bits 31:24): EISA Only
        !           175: #define DMA_CHAN0_HIPAGE_PORT  0x0487
        !           176: #define DMA_CHAN1_HIPAGE_PORT  0x0483
        !           177: #define DMA_CHAN2_HIPAGE_PORT  0x0481
        !           178: #define DMA_CHAN3_HIPAGE_PORT  0x0482
        !           179: 
        !           180: #define DMA_CMD_STATUS_PORT    0x0008
        !           181: #define DMA_REQ_PORT           0x0009
        !           182: #define DMA_MASK_PORT          0x000A
        !           183: #define DMA_MODE_PORT          0x000B
        !           184: #define DMA_CLEAR_FF_PORT      0x000C
        !           185: #define DMA_MASTER_RESET_PORT  0x000D
        !           186: #define DMA_EXTEND_MODE_PORT   0x040B
        !           187: 
        !           188: /*
        !           189:  * Slave device.
        !           190:  */
        !           191: #define DMA2_CHAN0_ADDR_PORT   0x00C0
        !           192: #define DMA2_CHAN0_COUNT_PORT  0x00C2
        !           193: #define DMA2_CHAN1_ADDR_PORT   0x00C4
        !           194: #define DMA2_CHAN1_COUNT_PORT  0x00C6
        !           195: #define DMA2_CHAN2_ADDR_PORT   0x00C8
        !           196: #define DMA2_CHAN2_COUNT_PORT  0x00CA
        !           197: #define DMA2_CHAN3_ADDR_PORT   0x00CC
        !           198: #define DMA2_CHAN3_COUNT_PORT  0x00CE
        !           199: 
        !           200: #define DMA2_CHAN1_PAGE_PORT   0x008B
        !           201: #define DMA2_CHAN2_PAGE_PORT   0x0089
        !           202: #define DMA2_CHAN3_PAGE_PORT   0x008A
        !           203: 
        !           204: // HICOUNT (bits 23:16): EISA Only
        !           205: #define DMA2_CHAN1_HICOUNT_PORT        0x04C6
        !           206: #define DMA2_CHAN2_HICOUNT_PORT        0x04CA
        !           207: #define DMA2_CHAN3_HICOUNT_PORT        0x04CE
        !           208: 
        !           209: // HIPAGE (bits 31:24): EISA Only
        !           210: #define DMA2_CHAN1_HIPAGE_PORT 0x048B
        !           211: #define DMA2_CHAN2_HIPAGE_PORT 0x0489
        !           212: #define DMA2_CHAN3_HIPAGE_PORT 0x048A
        !           213: 
        !           214: #define DMA2_CMD_STATUS_PORT   0x00D0
        !           215: #define DMA2_REQ_PORT          0x00D2
        !           216: #define DMA2_MASK_PORT         0x00D4
        !           217: #define DMA2_MODE_PORT         0x00D6
        !           218: #define DMA2_CLEAR_FF_PORT     0x00D8
        !           219: #define DMA2_MASTER_RESET_PORT 0x00DA
        !           220: #define DMA2_EXTEND_MODE_PORT  0x04D6

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