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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Copyright (c) 1992 NeXT Computer, Inc.
27: *
28: * 8259A (PIC) Interrupt Controller definitions.
29: *
30: * HISTORY
31: *
32: * 31 May 1992 ? at NeXT
33: * Created.
34: */
35:
36: /*
37: * Operation Command Words.
38: */
39:
40: /*
41: * OCW1 - interrupt mask.
42: */
43: typedef struct {
44: unsigned char
45: mask :8;
46: } intr_ocw1_t;
47:
48: /*
49: * OCW2 - EOI support.
50: */
51: typedef struct {
52: unsigned char
53: level :3,
54: set_to_zero :2,
55: eoi :1,
56: specific :1,
57: rotation :1;
58: } intr_ocw2_t;
59:
60: /*
61: * OCW3 - register access, poll, smm commands.
62: */
63: typedef struct {
64: unsigned char
65: read_reg :2,
66: #define INTR_OCW3_READ_IRR 2
67: #define INTR_OCW3_READ_ISR 3
68: poll :1,
69: set_to_one :2,
70: smm :2,
71: #define INTR_OCW3_RESET_SMM 2
72: #define INTR_OCW3_SET_SMM 3
73: :1;
74: } intr_ocw3_t;
75:
76: /*
77: * Initialization Command Words.
78: */
79:
80: /*
81: * ICW1 - mode initialization.
82: */
83: typedef struct {
84: unsigned char
85: ic4 :1,
86: no_slaves :1,
87: vectsz :1,
88: #define INTR_ICW1_VECTSZ_8 0
89: #define INTR_ICW1_VECTSZ_4 1
90: trig_mode :1,
91: #define INTR_ICW1_EDGE_TRIG 0
92: #define INTR_ICW1_LEVEL_TRIG 1
93: set_to_one :1,
94: :3;
95: } intr_icw1_t;
96:
97: /*
98: * ICW2 - interrupt vector.
99: */
100: typedef struct {
101: unsigned char
102: vectoff :8;
103: } intr_icw2_t;
104:
105: /*
106: * ICW3 for master - slave inputs.
107: */
108: typedef struct {
109: unsigned char
110: slave_ir :8;
111: } intr_icw3m_t;
112:
113: /*
114: * ICW3 for slave - slave priority.
115: */
116: typedef struct {
117: unsigned char
118: slave_id :3,
119: :5;
120: } intr_icw3s_t;
121:
122: /*
123: * ICW4 - misc mode initialization.
124: */
125: typedef struct {
126: unsigned char
127: pmode :1,
128: #define INTR_ICW4_8080_MODE 0
129: #define INTR_ICW4_8086_MODE 1
130: auto_eoi :1,
131: bufmode :2,
132: #define INTR_ICW4_NONBUF 0
133: #define INTR_ICW4_BUF_SLAVE 2
134: #define INTR_ICW4_BUF_MASTER 3
135: sfnmode :1,
136: :3;
137: } intr_icw4_t;
138:
139: /*
140: * ELCR - EISA Edge/Level Triggered
141: * Control Register.
142: */
143: typedef struct {
144: unsigned char
145: mask :8;
146: } intr_elcr_t;
147:
148: /*
149: * PIC I/O Ports.
150: */
151:
152: /*
153: * Master device.
154: */
155: #define INTR_PRIMARY_PORT 0x0020
156: #define INTR_SECONDARY_PORT 0x0021
157: #define INTR_ELCR_PORT 0x04D0
158:
159: /*
160: * Slave device.
161: */
162: #define INTR2_PRIMARY_PORT 0x00A0
163: #define INTR2_SECONDARY_PORT 0x00A1
164: #define INTR2_ELCR_PORT 0x04D1
165:
166: /*
167: * IRQs returned for missed interrupts.
168: */
169: #define INTR_MASTER_PHANTOM_IRQ 7
170: #define INTR_SLAVE_PHANTOM_IRQ 15
171: #define INTR_PHANTOM_IRQ_MASK (1 << 7)
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