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1.1 ! root 1: /* ! 2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved. ! 3: * ! 4: * @APPLE_LICENSE_HEADER_START@ ! 5: * ! 6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights ! 7: * Reserved. This file contains Original Code and/or Modifications of ! 8: * Original Code as defined in and that are subject to the Apple Public ! 9: * Source License Version 1.1 (the "License"). You may not use this file ! 10: * except in compliance with the License. Please obtain a copy of the ! 11: * License at http://www.apple.com/publicsource and read it before using ! 12: * this file. ! 13: * ! 14: * The Original Code and all software distributed under the License are ! 15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER ! 16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, ! 17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, ! 18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the ! 19: * License for the specific language governing rights and limitations ! 20: * under the License. ! 21: * ! 22: * @APPLE_LICENSE_HEADER_END@ ! 23: */ ! 24: ! 25: /* Copyright (c) 1992 NeXT Computer, Inc. All rights reserved. ! 26: * ! 27: * vgapriv.h - Private definitions used by vga ps driver implementation. ! 28: * ! 29: * ! 30: * HISTORY ! 31: * 28 Sep 92 Gary Crum ! 32: * Created. ! 33: */ ! 34: ! 35: // TO DO: Color palette setting will be moved into kernel driver ! 36: // and change along with Mike Paquette's work. ! 37: ! 38: // These values were computed given a gamma of 1.5. ! 39: // For most CRT displays, gamma should be 2.2, but this driver is ! 40: // used for flat panel LCD displays, so this 1.5 setting is a compromise. ! 41: #define WHITE_PALETTE_VALUE 63 ! 42: #define LIGHT_GRAY_PALETTE_VALUE 48 ! 43: #define DARK_GRAY_PALETTE_VALUE 30 ! 44: #define BLACK_PALETTE_VALUE 0 ! 45: ! 46: #define INB(addr) { inb(addr); } ! 47: #define INDB(addr,data) { data=inb(addr); } ! 48: #define OUTB(addr,data) { outb(addr,data); } ! 49: ! 50: #define zvga_reg_out(reg,indx,data) \ ! 51: { \ ! 52: OUTB(WRIT_##reg##_ADDR, indx) \ ! 53: OUTB(WRIT_##reg##_DATA, data) \ ! 54: } ! 55: ! 56: #define zvga_reg__in(reg,indx,data) \ ! 57: { \ ! 58: OUTB(WRIT_##reg##_ADDR, indx) \ ! 59: INDB(READ_##reg##_DATA, data) \ ! 60: } ! 61: ! 62: ! 63: /* ! 64: *********************************************************************************************** ! 65: ** VGA :- General registers ** ! 66: *********************************************************************************************** ! 67: */ ! 68: #define WRIT_MONO_GEN_MISC_OP 0x03C2 ! 69: #define WRIT_COLR_GEN_MISC_OP 0x03C2 ! 70: #define WRIT_EIDR_GEN_MISC_OP 0x03C2 ! 71: ! 72: #define READ_MONO_GEN_MISC_OP 0x03CC ! 73: #define READ_COLR_GEN_MISC_OP 0x03CC ! 74: #define READ_EIDR_GEN_MISC_OP 0x03CC ! 75: ! 76: #define READ_MONO_GEN_IN_ST_0 0x03C2 ! 77: #define READ_COLR_GEN_IN_ST_0 0x03C2 ! 78: #define READ_EIDR_GEN_IN_ST_0 0x03C2 ! 79: ! 80: #define READ_MONO_GEN_IN_ST_1 0x03BA ! 81: #define READ_COLR_GEN_IN_ST_1 0x03DA ! 82: ! 83: #define WRIT_MONO_GEN_FEAT_CT 0x03BA ! 84: #define WRIT_COLR_GEN_FEAT_CT 0x03DA ! 85: ! 86: #define READ_MONO_GEN_FEAT_CT 0x03CA ! 87: #define READ_COLR_GEN_FEAT_CT 0x03CA ! 88: ! 89: /* ! 90: ** Index mask - not necessary here ! 91: */ ! 92: #define MONO_GEN_MSK 0x00 ! 93: #define COLR_GEN_MSK 0x00 ! 94: #define EIDR_GEN_MSK 0x00 ! 95: ! 96: /* ! 97: ** List of index registers ! 98: */ ! 99: ! 100: /* ! 101: ** Bitfields for misc op reg. ! 102: */ ! 103: #define GEN_AT_VSP 0x80 ! 104: #define GEN_AT_HSP 0x40 ! 105: #define GEN_AT__PB 0x00 ! 106: #define GEN_AT_DVD 0x10 ! 107: #define GEN_AT__CS 0x0C ! 108: #define GEN_AT__ER 0x02 ! 109: #define GEN_AT_IOA 0x01 ! 110: ! 111: /* ! 112: ** Bitfields for feature control reg. ! 113: */ ! 114: #define GEN_AT_VSS 0x08 ! 115: ! 116: /* ! 117: ** Bitfields for Input Status #0 register ! 118: */ ! 119: #define GEN_AT__SS 0x10 ! 120: ! 121: /* ! 122: ** Bitfields for Input Status #1 register ! 123: */ ! 124: #define GEN_AT__VR 0x08 ! 125: #define GEN_AT__DE 0x01 ! 126: ! 127: /* ! 128: *********************************************************************************************** ! 129: ** VGA :- Sequencer registers ** ! 130: *********************************************************************************************** ! 131: */ ! 132: #define READ_MONO_SEQ_ADDR 0x03C4 ! 133: #define READ_COLR_SEQ_ADDR 0x03C4 ! 134: #define READ_EIDR_SEQ_ADDR 0x03C4 ! 135: ! 136: #define WRIT_MONO_SEQ_ADDR 0x03C4 ! 137: #define WRIT_COLR_SEQ_ADDR 0x03C4 ! 138: #define WRIT_EIDR_SEQ_ADDR 0x03C4 ! 139: ! 140: #define READ_MONO_SEQ_DATA 0x03C5 ! 141: #define READ_COLR_SEQ_DATA 0x03C5 ! 142: #define READ_EIDR_SEQ_DATA 0x03C5 ! 143: ! 144: #define WRIT_MONO_SEQ_DATA 0x03C5 ! 145: #define WRIT_COLR_SEQ_DATA 0x03C5 ! 146: #define WRIT_EIDR_SEQ_DATA 0x03C5 ! 147: ! 148: /* ! 149: ** Index mask ! 150: */ ! 151: #define MONO_SEQ_MSK 0x07 ! 152: #define COLR_SEQ_MSK 0x07 ! 153: #define EIDR_SEQ_MSK 0x07 ! 154: ! 155: /* ! 156: ** List of index registers ! 157: */ ! 158: #define SEQ_AT_RST 0x00 ! 159: #define SEQ_AT_CLO 0x01 ! 160: #define SEQ_AT_MPK 0x02 ! 161: #define SEQ_AT_CRS 0x03 ! 162: #define SEQ_AT_MMD 0x04 ! 163: ! 164: /* ! 165: ** Bitfield - Sequencer registers - Reset ! 166: */ ! 167: #define SEQ_AT__SR 0x02 ! 168: #define SEQ_AT__AR 0x00 ! 169: ! 170: /* ! 171: ** Bitfields - Sequencer registers - Clocking Mode Register ! 172: */ ! 173: #define SEQ_AT__SO 0x20 ! 174: #define SEQ_AT__S4 0x10 ! 175: #define SEQ_AT__DC 0x08 ! 176: #define SEQ_AT__SL 0x04 ! 177: #define SEQ_AT__89 0x01 ! 178: ! 179: /* ! 180: ** Bitfields - Sequencer registers - Map Mask Register ! 181: */ ! 182: #define SEQ_AT_EM3 0x08 ! 183: #define SEQ_AT_EM2 0x04 ! 184: #define SEQ_AT_EM1 0x02 ! 185: #define SEQ_AT_EM0 0x01 ! 186: ! 187: /* ! 188: ** Bitfields - Sequencer registers - Character Map Select Registers ! 189: */ ! 190: #define SEQ_AT_SAH 0x20 ! 191: #define SEQ_AT_SBH 0x10 ! 192: #define SEQ_AT__SA 0x0C ! 193: #define SEQ_AT__SB 0x03 ! 194: ! 195: /* ! 196: ** Bitfields - Sequencer registers - Memory Mode Register ! 197: */ ! 198: #define SEQ_AT__C4 0x08 ! 199: #define SEQ_AT__OE 0x04 ! 200: #define SEQ_AT__EM 0x02 ! 201: ! 202: /* ! 203: *********************************************************************************************** ! 204: ** VGA :- CRT Controller Registers ** ! 205: *********************************************************************************************** ! 206: */ ! 207: #define WRIT_MONO_CRT_ADDR 0x03B4 ! 208: #define READ_MONO_CRT_ADDR 0x03B4 ! 209: ! 210: #define WRIT_MONO_CRT_DATA 0x03B5 ! 211: #define READ_MONO_CRT_DATA 0x03D5 ! 212: ! 213: #define WRIT_COLR_CRT_ADDR 0x03D4 ! 214: #define READ_COLR_CRT_ADDR 0x03D4 ! 215: ! 216: #define WRIT_COLR_CRT_DATA 0x03D5 ! 217: #define READ_COLR_CRT_DATA 0x03D5 ! 218: ! 219: /* ! 220: ** Index mask ! 221: */ ! 222: #define MONO_CRT_MSK 0x3F ! 223: #define COLR_CRT_MSK 0x3F ! 224: ! 225: /* ! 226: ** List of index registers ! 227: */ ! 228: #define CRT_AT_HORZ_TOT 0x00 ! 229: #define CRT_AT_HORZ_DND 0x01 ! 230: #define CRT_AT_HORZ_BST 0x02 ! 231: #define CRT_AT_HORZ_BND 0x03 ! 232: #define CRT_AT_HORZ_RST 0x04 ! 233: #define CRT_AT_HORZ_RND 0x05 ! 234: #define CRT_AT_VERT_TOT 0x06 ! 235: #define CRT_AT_OVERFLOW 0x07 ! 236: #define CRT_AT_PRE_ROWS 0x08 ! 237: #define CRT_AT_MAX_SCAN 0x09 ! 238: #define CRT_AT_CURSR_ST 0x0A ! 239: #define CRT_AT_CURSR_ND 0x0B ! 240: #define CRT_AT_ST_ADRHI 0x0C ! 241: #define CRT_AT_ST_ADRLO 0x0D ! 242: #define CRT_AT_CR_LOCHI 0x0E ! 243: #define CRT_AT_CR_LOCLO 0x0F ! 244: #define CRT_AT_VRT_RTST 0x10 ! 245: #define CRT_AT_VRT_RTLO 0x11 ! 246: #define CRT_AT_VRT_DSND 0x12 ! 247: #define CRT_AT___OFFSET 0x13 ! 248: #define CRT_AT_UNDR_LOC 0x14 ! 249: #define CRT_AT_VBLNK_ST 0x15 ! 250: #define CRT_AT_VBLNK_ND 0x16 ! 251: #define CRT_AT_MOD_CTRL 0x17 ! 252: #define CRT_AT_LINE_CMP 0x18 ! 253: ! 254: /* ! 255: ** Bitfields - CRT Controller registers - Horizontal total Register ! 256: */ ! 257: #define CRT_AT__HT 0xFF ! 258: ! 259: /* ! 260: ** Bitfields - CRT Controller registers - Horizontal Display End Register ! 261: */ ! 262: #define CRT_AT_HDE 0xFF ! 263: ! 264: /* ! 265: ** Bitfields - CRT Controller registers - Start Horizontal Blanking register ! 266: */ ! 267: #define CRT_AT_SHB 0xFF ! 268: ! 269: /* ! 270: ** Bitfields - CRT Controller registers - End Horizontal Blanking Register ! 271: */ ! 272: #define CRT_AT__CR 0x80 ! 273: #define CRT_AT_DES 0x60 ! 274: #define CRT_AT_EHB 0x1F ! 275: ! 276: /* ! 277: ** Bitfields - CRT Controller registers - Start Horizontal Retrace Register ! 278: */ ! 279: #define CRT_AT_SHR 0xFF ! 280: ! 281: /* ! 282: ** Bitfields - CRT Controller registers - End Horizontal Retrace Register ! 283: */ ! 284: #define CRT_AT_EHB_6 0x80 ! 285: #define EGA_AT_CRT 0x80 ! 286: #define CRT_AT_HRD 0x60 ! 287: #define CRT_AT_EHR 0x1F ! 288: ! 289: /* ! 290: ** Bitfields - CRT Controller registers - Vertical Total Register ! 291: */ ! 292: #define CRT_AT_VT 0xFF ! 293: ! 294: /* ! 295: ** Bitfields - CRT Controller registers - Overflow Register ! 296: */ ! 297: #define CRT_AT_VRS_9 0x80 ! 298: #define CRT_AT_VDE_9 0x40 ! 299: #define EGA_AT_CRT_8 0x20 ! 300: #define CRT_AT_VT1_8 0x20 ! 301: #define CRT_AT__LC_8 0x10 ! 302: #define CRT_AT_VBS_8 0x08 ! 303: #define CRT_AT_VRS_8 0x04 ! 304: #define CRT_AT_VDE_8 0x02 ! 305: #define CRT_AT__VT_8 0x01 ! 306: ! 307: /* ! 308: ** Bitfields - CRT Controller registers - Preset Row Scan Register ! 309: */ ! 310: #define CRT_AT__BP 0x60 ! 311: #define CRT_AT_PRS 0x1F ! 312: ! 313: /* ! 314: ** Bitfields - CRT Controller registers - Maximum Scan Line Register ! 315: */ ! 316: #define CRT_AT_2T4 0x80 ! 317: #define CRT_AT__LC 0x40 ! 318: #define CRT_AT_VBS_9 0x20 ! 319: #define CRT_AT_MSL 0x1F ! 320: ! 321: /* ! 322: ** Bitfields - CRT Controller registers - Cursor Start Register ! 323: */ ! 324: #define CRT_AT_COO 0x20 ! 325: #define CRT_AT__CS 0x1F ! 326: ! 327: /* ! 328: ** Bitfields - CRT Controller registers - Cursor End Register ! 329: */ ! 330: #define CRT_AT_CSK 0x60 ! 331: #define CRT_AT__CE 0x1F ! 332: ! 333: /* ! 334: ** Bitfields - CRT Controller registers - Start Address High Register ! 335: */ ! 336: #define CRT_AT_SAH 0xFF ! 337: ! 338: /* ! 339: ** Bitfields - CRT Controller registers - Start Address Low Register ! 340: */ ! 341: #define CRT_AT_SAL 0xFF ! 342: ! 343: /* ! 344: ** Bitfields - CRT Controller registers - Cursor Location High Register ! 345: */ ! 346: #define CRT_AT_CLH 0xFF ! 347: ! 348: /* ! 349: ** Bitfields - CRT Controller registers - Cursor Location Low Register ! 350: */ ! 351: #define CRT_AT_CLL 0xFF ! 352: ! 353: /* ! 354: ** Bitfields - CRT Controller registers - Vertical Retrace Start Register ! 355: */ ! 356: #define CRT_AT_VRS 0xFF ! 357: ! 358: /* ! 359: ** Bitfields - CRT Controller registers - Vertical Retrace End Register ! 360: */ ! 361: #define CRT_AT__PR 0x80 ! 362: #define CRT_AT__BW 0x40 ! 363: #define CRT_AT_DVI 0x20 ! 364: #define CRT_AT_CVI 0x10 ! 365: #define CRT_AT_EVR 0x0F ! 366: ! 367: /* ! 368: ** Bitfields - CRT Controller registers - Light Pen High Register ! 369: */ ! 370: #define CRT_AT_LPH 0xFF ! 371: ! 372: /* ! 373: ** Bitfields - CRT Controller registers - Light Pen Low Register ! 374: */ ! 375: #define CRT_AT_LPL 0xFF ! 376: ! 377: /* ! 378: ** Bitfields - CRT Controller registers - Vertical Display End Register ! 379: */ ! 380: #define CRT_AT_VDE 0xFF ! 381: ! 382: /* ! 383: ** Bitfields - CRT Controller registers - Offset Register ! 384: */ ! 385: #define CRT_AT_OFF 0xFF ! 386: ! 387: /* ! 388: ** Bitfields - CRT Controller registers - Underline Location Register ! 389: */ ! 390: #define CRT_AT__DW 0x40 ! 391: #define CRT_AT_CB4 0x20 ! 392: #define CRT_AT__UL 0x1F ! 393: ! 394: /* ! 395: ** Bitfields - CRT Controller registers - Start vertical Blank register ! 396: */ ! 397: #define CRT_AT_VBS 0xFF ! 398: ! 399: /* ! 400: ** Bitfields - CRT Controller registers - End Vertical Blank register ! 401: */ ! 402: #define CRT_AT_VBE_H 0x60 ! 403: #define CRT_AT_VBE_L 0x1F ! 404: ! 405: /* ! 406: ** Bitfields - CRT Controller registers - Mode Control Register ! 407: */ ! 408: #define CRT_AT__HR 0x80 ! 409: #define CRT_AT__WB 0x40 ! 410: #define CRT_AT__AW 0x20 ! 411: #define CRT_AT__OC 0x10 ! 412: #define CRT_AT_CBT 0x08 ! 413: #define CRT_AT_HRS 0x04 ! 414: #define CRT_AT_SRS 0x02 ! 415: #define CRT_AT_CMS 0x01 ! 416: ! 417: /* ! 418: ** Bitfields - CRT Controller registers - Line Compare Register ! 419: */ ! 420: #define CRT_AT_LNC 0xFF ! 421: ! 422: /* ! 423: *********************************************************************************************** ! 424: ** VGA :- GCR Controller Registers ** ! 425: *********************************************************************************************** ! 426: */ ! 427: #define READ_MONO_GCR_ADDR 0x03CE ! 428: #define READ_COLR_GCR_ADDR 0x03CE ! 429: #define READ_EIDR_GCR_ADDR 0x03CE ! 430: ! 431: #define WRIT_MONO_GCR_ADDR 0x03CE ! 432: #define WRIT_COLR_GCR_ADDR 0x03CE ! 433: #define WRIT_EIDR_GCR_ADDR 0x03CE ! 434: ! 435: #define READ_MONO_GCR_DATA 0x03CF ! 436: #define READ_COLR_GCR_DATA 0x03CF ! 437: #define READ_EIDR_GCR_DATA 0x03CF ! 438: ! 439: #define WRIT_MONO_GCR_DATA 0x03CF ! 440: #define WRIT_COLR_GCR_DATA 0x03CF ! 441: #define WRIT_EIDR_GCR_DATA 0x03CF ! 442: ! 443: /* ! 444: ** Index mask ! 445: */ ! 446: #define MONO_GCR_MSK 0x0F ! 447: #define COLR_GCR_MSK 0x0F ! 448: #define EIDR_GCR_MSK 0x0F ! 449: ! 450: /* ! 451: ** List of index registers ! 452: */ ! 453: #define GCR_AT_SET_RESET 0x00 ! 454: #define GCR_AT_ENA_S_RST 0x01 ! 455: #define GCR_AT_COLR_COMP 0x02 ! 456: #define GCR_AT_DATA_ROTR 0x03 ! 457: #define GCR_AT_READ_MAPS 0x04 ! 458: #define GCR_AT_GCR__MODE 0x05 ! 459: #define GCR_AT_GCR__MISC 0x06 ! 460: #define GCR_AT_CLR_NOCAR 0x07 ! 461: #define GCR_AT_BIT__MASK 0x08 ! 462: ! 463: /* ! 464: ** Bitfields - Graphics Controller Registers - Graphics#1 Position Register ! 465: */ ! 466: #define GCR_AT_GP1 0x03 ! 467: ! 468: /* ! 469: ** Bitfields - Graphics Controller Registers - Graphics#2 Position Register ! 470: */ ! 471: #define GCR_AT_GP2 0x03 ! 472: ! 473: /* ! 474: ** Bitfields - Graphics Controller Registers - Set/Reset Register ! 475: */ ! 476: #define GCR_AT_S_R 0x0F ! 477: ! 478: /* ! 479: ** Bitfields - Graphics Controller Registers - Enable Set/Reset Register ! 480: */ ! 481: #define GCR_AT_ESR 0x0F ! 482: ! 483: /* ! 484: ** Bitfields - Graphics Controller Registers - Color Compare Register ! 485: */ ! 486: #define GCR_AT__CC 0x0F ! 487: ! 488: /* ! 489: ** Bitfields - Graphics Controller Registers - Data Rotate register ! 490: */ ! 491: #define GCR_AT__FS 0x30 ! 492: #define GCR_AT__RC 0x0F ! 493: ! 494: /* ! 495: ** Bitfields - Graphics Controller Registers - Read Map Select Register ! 496: */ ! 497: #define GCR_AT_RMS 0x03 ! 498: ! 499: /* ! 500: ** Bitfields - Graphics Controller Registers - Mode Register ! 501: */ ! 502: #define GCR_AT__SR 0x60 ! 503: #define GCR_AT__OE 0x10 ! 504: #define GCR_AT__RM 0x08 ! 505: #define GCR_AT__TC 0x04 ! 506: #define GCR_AT__WM 0x03 ! 507: ! 508: /* ! 509: ** Bitfields - Graphics Controller Registers - Miscellaneous register ! 510: */ ! 511: #define GCR_AT__MM 0x0C ! 512: #define GCR_AT_COE 0x02 ! 513: #define GCR_AT__GA 0x01 ! 514: ! 515: /* ! 516: ** Bitfields - Graphics Controller Registers - Color Dont Care register ! 517: */ ! 518: #define GCR_AT_CDC 0x0F ! 519: ! 520: /* ! 521: ** Bitfields - Graphics Controller Registers - Bit Mask ! 522: */ ! 523: #define GCR_AT__BM 0xFF ! 524: ! 525: /* ! 526: *********************************************************************************************** ! 527: ** VGA :- ACR Controller Registers ** ! 528: *********************************************************************************************** ! 529: */ ! 530: ! 531: #define WRIT_TOGL_ACR_ADDR 0x03C0 ! 532: #define READ_TOGL_ACR_ADDR 0x03C0 ! 533: ! 534: #define WRIT_TOGL_ACR_DATA 0x03C0 ! 535: #define READ_TOGL_ACR_DATA 0x03C1 ! 536: ! 537: /* ! 538: ** Index mask ! 539: */ ! 540: #define ACR_MSK 0x1F ! 541: ! 542: /* ! 543: ** List of index registers ! 544: */ ! 545: #define ACR_AT_PALETTE_0 0x00 ! 546: #define ACR_AT_PALETTE_1 0x01 ! 547: #define ACR_AT_PALETTE_2 0x02 ! 548: #define ACR_AT_PALETTE_3 0x03 ! 549: #define ACR_AT_PALETTE_4 0x04 ! 550: #define ACR_AT_PALETTE_5 0x05 ! 551: #define ACR_AT_PALETTE_6 0x06 ! 552: #define ACR_AT_PALETTE_7 0x07 ! 553: #define ACR_AT_PALETTE_8 0x08 ! 554: #define ACR_AT_PALETTE_9 0x09 ! 555: #define ACR_AT_PALETTE_A 0x0A ! 556: #define ACR_AT_PALETTE_B 0x0B ! 557: #define ACR_AT_PALETTE_C 0x0C ! 558: #define ACR_AT_PALETTE_D 0x0D ! 559: #define ACR_AT_PALETTE_E 0x0E ! 560: #define ACR_AT_PALETTE_F 0x0F ! 561: #define ACR_AT_MODE_CNTL 0x10 ! 562: #define ACR_AT_OVERSCN_C 0x11 ! 563: #define ACR_AT_CLR_PL_EN 0x12 ! 564: #define ACR_AT_HORZ_PXPN 0x13 ! 565: #define ACR_AT_COLOR_SEL 0x14 ! 566: ! 567: /* ! 568: ** Bitfields - Attribute Controller registers - pallette registers ! 569: */ ! 570: #define ACR_AT__SR 0x20 ! 571: #define ACR_AT__SG 0x10 ! 572: #define ACR_AT__SB 0x08 ! 573: #define ACR_AT_REG 0x04 ! 574: #define ACR_AT_GRN 0x02 ! 575: #define ACR_AT_BLU 0x01 ! 576: ! 577: /* ! 578: ** Bitfields - Attribute Controller registers - Mode Control register ! 579: */ ! 580: #define ACR_AT_IPS 0x80 ! 581: #define ACR_AT_PCS 0x40 ! 582: #define ACR_AT_PPC 0x20 ! 583: #define ACR_AT__BI 0x08 ! 584: #define ACR_AT_ELG 0x04 ! 585: #define ACR_AT__DT 0x02 ! 586: #define ACR_AT__GA 0x01 ! 587: ! 588: /* ! 589: ** Bitfields - Attribute Controller registers - Overscan Color Register ! 590: */ ! 591: ! 592: #define ACR_AT_OSR 0x20 ! 593: #define ACR_AT_OSG 0x10 ! 594: #define ACR_AT_OSB 0x08 ! 595: #define ACR_AT_ORD 0x04 ! 596: #define ACR_AT_OGR 0x02 ! 597: #define ACR_AT_OBL 0x01 ! 598: /* ! 599: ** Bitfields - Attribute Controller registers - Color Plane Enable Register ! 600: */ ! 601: ! 602: #define ACR_AT_VSM 0x30 ! 603: #define ACR_AT_CPE 0x0F ! 604: /* ! 605: ** Bitfields - Attribute Controller registers - Horizontal Pixel Panning Reg ! 606: */ ! 607: #define ACR_AT_HPP 0x0F ! 608: ! 609: /* ! 610: ** Bitfields - Attribute Controller registers - Color Select Register ! 611: */ ! 612: #define ACR_AT_C67 0x0C ! 613: #define ACR_AT_C45 0x03 ! 614: ! 615: /* ! 616: *********************************************************************************************** ! 617: ** VGA :- PEL Controller Registers ** ! 618: *********************************************************************************************** ! 619: */ ! 620: #define WRIT_MONO_PEL_AWMR 0x03C8 ! 621: #define WRIT_COLR_PEL_AWMR 0x03C8 ! 622: #define READ_MONO_PEL_AWMR 0x03C8 ! 623: #define READ_COLR_PEL_AWMR 0x03C8 ! 624: ! 625: #define WRIT_MONO_PEL_ARMR 0x03C7 ! 626: #define WRIT_COLR_PEL_ARMR 0x03C7 ! 627: ! 628: #define WRIT_MONO_PEL_DATA 0x03C9 ! 629: #define WRIT_COLR_PEL_DATA 0x03C9 ! 630: #define READ_MONO_PEL_DATA 0x03C9 ! 631: #define READ_COLR_PEL_DATA 0x03C9 ! 632: ! 633: #define READ_MONO_PEL_DACS 0x03C7 ! 634: #define READ_COLR_PEL_DACS 0x03C7 ! 635: ! 636: #define WRIT_MONO_PEL_MASK 0x03C6 ! 637: #define WRIT_COLR_PEL_MASK 0x03C6 ! 638: #define READ_MONO_PEL_MASK 0x03C6 ! 639: #define READ_COLR_PEL_MASK 0x03C6 ! 640: ! 641: /* ! 642: *********************************************************************************************** ! 643: ** VGA :- External Palette RAM ! 644: *********************************************************************************************** ! 645: */ ! 646: #define READ_MONO_PEL_MASK 0x03C6 ! 647: #define READ_COLR_PEL_MASK 0x03C6 ! 648: #define READ_EIDR_PEL_MASK 0x03C6 ! 649: ! 650: #define WRIT_MONO_PEL_MASK 0x03C6 ! 651: #define WRIT_COLR_PEL_MASK 0x03C6 ! 652: #define WRIT_EIDR_PEL_MASK 0x03C6 ! 653: ! 654: #define READ_MONO_PEL_WADR 0x03C8 ! 655: #define READ_COLR_PEL_WADR 0x03C8 ! 656: #define READ_EIDR_PEL_WADR 0x03C8 ! 657: ! 658: #define WRIT_MONO_PEL_WADR 0x03C8 ! 659: #define WRIT_COLR_PEL_WADR 0x03C8 ! 660: #define WRIT_EIDR_PEL_WADR 0x03C8 ! 661: ! 662: #define READ_MONO_PEL_DATA 0x03C9 ! 663: #define READ_COLR_PEL_DATA 0x03C9 ! 664: #define READ_EIDR_PEL_DATA 0x03C9 ! 665: ! 666: #define WRIT_MONO_PEL_DATA 0x03C9 ! 667: #define WRIT_COLR_PEL_DATA 0x03C9 ! 668: #define WRIT_EIDR_PEL_DATA 0x03C9 ! 669: ! 670: #define WRIT_MONO_PEL_RADR 0x03C7 ! 671: #define WRIT_COLR_PEL_RADR 0x03C7 ! 672: #define WRIT_EIDR_PEL_RADR 0x03C7 ! 673: ! 674: #define WRIT_MONO_PEL_DACS 0x03C7 ! 675: #define WRIT_COLR_PEL_DACS 0x03C7 ! 676: #define WRIT_EIDR_PEL_DACS 0x03C7 ! 677: ! 678: /* ! 679: *********************************************************************************************** ! 680: ** VGA :- MODES ** ! 681: *********************************************************************************************** ! 682: */ ! 683: #define MAX_GEN_INDEX 0x01 ! 684: #define MAX_SEQ_INDEX SEQ_AT_MMD ! 685: #define MAX_CRT_INDEX CRT_LINE_CMP ! 686: #define MAX_GCR_INDEX GCR_BIT__MASK ! 687: #define MAX_ACR_INDEX ACR_COLOUR_SEL ! 688: ! 689: /* ! 690: ** There now follows a symbolic list of modes, these will be used as indeces into tables of ! 691: ** initial values to be put into the various registers for a given mode. ! 692: */ ! 693: ! 694: #define MODE_VGA_AT_00 0x00 ! 695: #define MODE_VGA_AT_01 0x01 ! 696: #define MODE_VGA_AT_02 0x02 ! 697: #define MODE_VGA_AT_03 0x03 ! 698: #define MODE_VGA_AT_04 0x04 ! 699: #define MODE_VGA_AT_05 0x05 ! 700: #define MODE_VGA_AT_06 0x06 ! 701: #define MODE_VGA_AT_07 0x07 ! 702: #define MODE_VGA_AT_00_X 0x08 ! 703: #define MODE_VGA_AT_01_X 0x09 ! 704: #define MODE_VGA_AT_02_X 0x0A ! 705: #define MODE_VGA_AT_03_X 0x0B ! 706: #define MODE_VGA_AT_07_X 0x0C ! 707: #define MODE_VGA_AT_0D 0x0D ! 708: #define MODE_VGA_AT_0E 0x0E ! 709: #define MODE_VGA_AT_0F 0x0F ! 710: #define MODE_VGA_AT_10 0x10 ! 711: #define MODE_VGA_AT_11 0x11 ! 712: #define MODE_VGA_AT_12 0x12 ! 713: #define MODE_VGA_AT_13 0x13 ! 714: ! 715: #define MIN_VGA_AT_MODE MODE_VGA_AT_00 ! 716: #define MAX_VGA_AT_MODE MODE_VGA_AT_13 ! 717: #define NUM_VGA_AT_MODE MAX_VGA_AT_MODE-MIN_VGA_AT_MODE ! 718: ! 719: #define IS_REG_MODE(a) ((a) <= MAX_VGA_AT_MODE) ! 720: ! 721: struct mode_params { ! 722: char *m_str; ! 723: int p_type; ! 724: int p_bpp; ! 725: int p_start; ! 726: int p_pages; ! 727: int p_alfa_w; ! 728: int p_alfa_h; ! 729: int p_char_w; ! 730: int p_char_h; ! 731: int p_disp_w; ! 732: int p_disp_h; ! 733: int p_font; ! 734: }; ! 735: ! 736: /* ! 737: ** Defines for the type of a particular mode ie - is it alphanummeric(A) or graphical(G), ! 738: ** color(C) or mono(M), ! 739: */ ! 740: ! 741: #define MODE_A_M 0x00 ! 742: #define MODE_A_C 0x01 ! 743: #define MODE_G_M 0x10 ! 744: #define MODE_G_C 0x11 ! 745: ! 746: /* ! 747: *********************************************************************************************** ! 748: ** VGA :- FONTS ** ! 749: *********************************************************************************************** ! 750: */ ! 751: ! 752: #define FONT_09_BY_16 0x00 ! 753: #define FONT_09_BY_15 0x01 ! 754: #define FONT_09_BY_14 0x02 ! 755: #define FONT_09_BY_13 0x03 ! 756: #define FONT_08_BY_16 0x04 ! 757: #define FONT_08_BY_15 0x05 ! 758: #define FONT_08_BY_14 0x06 ! 759: #define FONT_08_BY_08 0x07 ! 760: ! 761: ! 762: #define VGA_AT_MAX_PLANES 0x04 ! 763: ! 764: ! 765: // Start of defines from prototype vga_ts_defs.h file. ! 766: ! 767: /* ! 768: *********************************************************************************************** ! 769: ** VGA :- General registers ** ! 770: *********************************************************************************************** ! 771: */ ! 772: #define WRIT_MONO_MODE_CT 0x03B8 ! 773: #define WRIT_COLR_MODE_CT 0x03D8 ! 774: #define WRIT_EIDR_MODE_CT 0x03D8 ! 775: ! 776: #define WRIT_MONO_GEN_VID_EN 0x46E8 ! 777: #define WRIT_COLR_GEN_VID_EN 0x46E8 ! 778: #define WRIT_EIDR_GEN_VID_EN 0x46E8 ! 779: ! 780: #define READ_MONO_GEN_VID_EN 0x03C3 ! 781: #define READ_COLR_GEN_VID_EN 0x03C3 ! 782: #define READ_EIDR_GEN_VID_EN 0x03C3 ! 783: ! 784: #define WRIT_MONO_ALT_VID_EN 0x46E8 ! 785: #define WRIT_COLR_ALT_VID_EN 0x46E8 ! 786: #define WRIT_EIDR_ALT_VID_EN 0x46E8 ! 787: ! 788: #define READ_MONO_ALT_VID_EN 0x46E8 ! 789: #define READ_COLR_ALT_VID_EN 0x46E8 ! 790: #define READ_EIDR_ALT_VID_EN 0x46E8 ! 791: ! 792: /* ! 793: ** Bitfields for Hercules compatibility register ! 794: */ ! 795: #define GEN_TS_HER 0xFD ! 796: #define GEN_TS_ESP 0x02 ! 797: ! 798: /* ! 799: ** Bitfields for Video Subsystem Register ! 800: */ ! 801: #define GEN_TS_WRI 0x01 ! 802: #define GEN_TS_REA 0x08 ! 803: #define GEN_TS_VSR 0xF6 ! 804: ! 805: /* ! 806: *********************************************************************************************** ! 807: ** VGA :- 6845 Compatibility registers ** ! 808: *********************************************************************************************** ! 809: */ ! 810: #define WRIT_MONO_6845_CTL_REG 0x03B4 ! 811: #define WRIT_COLR_6845_CTL_REG 0x03D4 ! 812: #define READ_MONO_6845_CTL_REG 0x03B4 ! 813: #define READ_COLR_6845_CTL_REG 0x03D4 ! 814: ! 815: #define WRIT_MONO_6845_DTA_REG 0x03B5 ! 816: #define WRIT_COLR_6845_DTA_REG 0x03D5 ! 817: #define READ_MONO_6845_DTA_REG 0x03B5 ! 818: #define READ_COLR_6845_DTA_REG 0x03D5 ! 819: ! 820: #define WRIT_MONO_6845_DMC_REG 0x03B8 ! 821: #define WRIT_COLR_6845_DMC_REG 0x03D8 ! 822: #define READ_MONO_6845_DMC_REG 0x03B8 ! 823: #define READ_COLR_6845_DMC_REG 0x03D8 ! 824: ! 825: #define WRIT_6845_DCC_REG 0x03D9 ! 826: ! 827: #define WRIT_MONO_6845_DSC_REG 0x03BA ! 828: #define WRIT_COLR_6845_DSC_REG 0x03DA ! 829: #define READ_MONO_6845_DSC_REG 0x03BA ! 830: #define READ_COLR_6845_DSC_REG 0x03DA ! 831: ! 832: #define WRIT_6845_ATT_REG 0x03DE ! 833: #define WRIT_HERCULES_REG 0x03BF ! 834: ! 835: /* ! 836: *********************************************************************************************** ! 837: ** VGA :- Sequencer registers ** ! 838: *********************************************************************************************** ! 839: */ ! 840: ! 841: /* ! 842: ** New Registers ! 843: */ ! 844: ! 845: /* ! 846: ** List of index registers ! 847: */ ! 848: #define SEQ_TS_TSS 0x06 ! 849: #define SEQ_TS_TAM 0x07 ! 850: ! 851: /* ! 852: ** Bitfields - Sequencer Registers - TS state control Tseng Labs ! 853: */ ! 854: #define SEQ_TS_TSS 0x06 ! 855: ! 856: /* ! 857: ** Bitfields - Sequencer Registers - TS Auxiliary mode Tseng Labs ! 858: */ ! 859: #define SEQ_TS_VGM 0x80 ! 860: #define SEQ_TS_MC2 0x40 ! 861: #define SEQ_TS_RO2 0x20 ! 862: #define SEQ_TS_RO1 0x08 ! 863: #define SEQ_TS_SC2 0x02 ! 864: #define SEQ_TS_MC4 0x01 ! 865: #define SEQ_TS_MSK 0x14 ! 866: ! 867: /* ! 868: *********************************************************************************************** ! 869: ** VGA :- CRT Controller Registers ** ! 870: *********************************************************************************************** ! 871: */ ! 872: ! 873: /* ! 874: ** New Registers ! 875: */ ! 876: ! 877: /* ! 878: ** List of index registers ! 879: */ ! 880: #define CRT_TS_RAS 0x32 ! 881: #define CRT_TS_ESA 0x33 ! 882: #define CRT_TS_CTL 0x34 ! 883: #define CRT_TS_OVH 0x35 ! 884: #define CRT_TS_VS1 0x36 ! 885: #define CRT_TS_VS2 0x37 ! 886: ! 887: /* ! 888: ** Bitfields - CRT Controller registers - RAS/CAS Configuration Reggister Tseng Labs ! 889: */ ! 890: #define CRT_TS_SCM 0x80 ! 891: #define CRT_TS_RAL 0x40 ! 892: #define CRT_TS_RCD 0x20 ! 893: #define CRT_TS_RSP 0x18 ! 894: #define CRT_TS_CSP 0x04 ! 895: #define CRT_TS_CSW 0x03 ! 896: ! 897: /* ! 898: ** Bitfields - CRT Controller registers - Extended Start Register Tseng Labs ! 899: */ ! 900: #define CRT_TS_CSA 0x0C ! 901: #define CRT_TS_LSA 0x03 ! 902: ! 903: /* ! 904: ** Bitfields - CRT Controller registers - 6845 Compatibility Control Register Tseng Labs ! 905: */ ! 906: #define CRT_TS_CMP 0x80 ! 907: #define CRT_TS_EBA 0x40 ! 908: #define CRT_TS_EXL 0x20 ! 909: #define CRT_TS_EXR 0x10 ! 910: #define CRT_TS_EVS 0x08 ! 911: #define CRT_TS_TRI 0x04 ! 912: #define CRT_TS_MCK 0x02 ! 913: #define CRT_TS_EMK 0x01 ! 914: ! 915: /* ! 916: ** Bitfields - CRT Controller registers - Overflow High Tseng Labs ! 917: */ ! 918: #define CRT_TS_VIM 0x80 ! 919: #define CRT_TS_ARW 0x40 ! 920: #define CRT_TS_ESR 0x20 ! 921: #define CRT_TS_LCA 0x10 ! 922: #define CRT_TS_VSA 0x08 ! 923: #define CRT_TS_VDA 0x04 ! 924: #define CRT_TS_VTA 0x02 ! 925: #define CRT_TS_VBA 0x01 ! 926: ! 927: /* ! 928: ** Bitfields - CRT Controller registers - Video System Configuration 1 Tseng Labs ! 929: */ ! 930: #define CRT_TS_RWF 0x80 ! 931: #define CRT_TS_DMF 0x40 ! 932: #define CRT_TS_AMD 0x20 ! 933: #define CRT_TS_SGL 0x10 ! 934: #define CRT_TS_FWF 0x08 ! 935: #define CRT_TS_REF 0x07 ! 936: ! 937: /* ! 938: ** Bitfields - CRT Controller registers - Video System Configuration 2 Tseng Labs ! 939: */ ! 940: #define CRT_TS_DRM 0x80 ! 941: #define CRT_TS_TST 0x40 ! 942: #define CRT_TS_PTC 0x20 ! 943: #define CRT_TS_RM8 0x10 ! 944: #define CRT_TS_DMD 0x0C ! 945: #define CRT_TS_DBW 0x03 ! 946: ! 947: /* ! 948: *********************************************************************************************** ! 949: ** VGA :- GCR Controller Registers ** ! 950: *********************************************************************************************** ! 951: */ ! 952: ! 953: /* ! 954: ** New Registers ! 955: */ ! 956: #define READ_MONO_GCR_SEGS 0x03CD ! 957: #define READ_COLR_GCR_SEGS 0x03CD ! 958: #define READ_EIDR_GCR_SEGS 0x03CD ! 959: ! 960: #define WRIT_MONO_GCR_SEGS 0x03CD ! 961: #define WRIT_COLR_GCR_SEGS 0x03CD ! 962: #define WRIT_EIDR_GCR_SEGS 0x03CD ! 963: ! 964: /* ! 965: ** List of index registers ! 966: */ ! 967: ! 968: /* ! 969: ** Bitfields - GCR Controller registers - Segment Select Register Tseng Labs ! 970: */ ! 971: #define GCR_TS_GRD 0xF0 ! 972: #define GCR_TS_GWR 0x0F ! 973: ! 974: /* ! 975: *********************************************************************************************** ! 976: ** VGA :- ACR Controller Registers ** ! 977: *********************************************************************************************** ! 978: */ ! 979: ! 980: /* ! 981: ** New Registers ! 982: */ ! 983: ! 984: /* ! 985: ** List of index registers ! 986: */ ! 987: #define ACR_TS_MSC 0x16 ! 988: ! 989: /* ! 990: ** Bitfields - Attribute Controller Registers - Miscellaneous Tseng Labs ! 991: */ ! 992: #define ACR_TS_BYP 0x80 ! 993: #define ACR_TS_2BC 0x40 ! 994: #define ACR_TS_SHR 0x30 ! 995: #define ACR_TS_RES 0x0F ! 996: ! 997: /* ! 998: *********************************************************************************************** ! 999: ** VGA :- MODES ** ! 1000: *********************************************************************************************** ! 1001: */ ! 1002: #define MAX_TS_GEN_INDEX 0x01 ! 1003: #define MAX_TS_SEQ_INDEX SEQ_TS_TAM ! 1004: #define MAX_TS_CRT_INDEX CRT_TS_VS2 ! 1005: #define MAX_TS_GCR_INDEX GCR_AT_BIT__MASK ! 1006: #define MAX_TS_ACR_INDEX ACR_TS_MISC ! 1007: ! 1008: /* ! 1009: ** There now follows a symbolic list of modes, these will be used as indeces into tables of ! 1010: ** initial values to be put into the various registers for a given mode. ! 1011: */ ! 1012: ! 1013: #define MODE_VGA_TS_18 (MAX_VGA_AT_MODE + 0x01) ! 1014: #define MODE_VGA_TS_19 (MAX_VGA_AT_MODE + 0x02) ! 1015: #define MODE_VGA_TS_1A (MAX_VGA_AT_MODE + 0x03) ! 1016: #define MODE_VGA_TS_22 (MAX_VGA_AT_MODE + 0x04) ! 1017: #define MODE_VGA_TS_23 (MAX_VGA_AT_MODE + 0x05) ! 1018: #define MODE_VGA_TS_24 (MAX_VGA_AT_MODE + 0x06) ! 1019: #define MODE_VGA_TS_25 (MAX_VGA_AT_MODE + 0x07) ! 1020: #define MODE_VGA_TS_26 (MAX_VGA_AT_MODE + 0x08) ! 1021: #define MODE_VGA_TS_29 (MAX_VGA_AT_MODE + 0x09) ! 1022: #define MODE_VGA_TS_2A (MAX_VGA_AT_MODE + 0x0A) ! 1023: #define MODE_VGA_TS_2D (MAX_VGA_AT_MODE + 0x0B) ! 1024: #define MODE_VGA_TS_2E (MAX_VGA_AT_MODE + 0x0C) ! 1025: #define MODE_VGA_TS_30 (MAX_VGA_AT_MODE + 0x0D) ! 1026: #define MODE_VGA_TS_37i (MAX_VGA_AT_MODE + 0x0E) ! 1027: #define MODE_VGA_TS_37n (MAX_VGA_AT_MODE + 0x0F) ! 1028: #define MODE_VGA_TS_2F (MAX_VGA_AT_MODE + 0x10) ! 1029: #define MODE_VGA_TS_38i (MAX_VGA_AT_MODE + 0x11) ! 1030: #define MODE_VGA_TS_38n (MAX_VGA_AT_MODE + 0x12) ! 1031: ! 1032: #define MAX_VGA_TS_MODE MODE_VGA_TS_38n ! 1033: #define MIN_VGA_TS_MODE MODE_VGA_TS_18 ! 1034: #define NUM_VGA_TS_MODE (MAX_VGA_TS_MODE-MIN_VGA_TS_MODE) ! 1035: ! 1036: /* ! 1037: *********************************************************************************************** ! 1038: ** Tseng Labs Specific ** ! 1039: *********************************************************************************************** ! 1040: */ ! 1041: ! 1042: #define CHIP_IS_ET3000 0x10 ! 1043: #define CHIP_IS_ET4000 0x11 ! 1044: ! 1045: #define VGA_TS_MAX_SIZE 0x10000 ! 1046: ! 1047: ! 1048: extern void vga_read_bpp4planar_to_bpp2packed32(unsigned short *fb, unsigned int *dst); ! 1049: extern void vga_write_bpp2packed32_to_bpp4planar(unsigned int *dst, unsigned short *fb); ! 1050: ! 1051: // Global variables ! 1052: // TODO: Eliminate the need for these. ! 1053: extern unsigned int vgapriv_bpl; ! 1054: extern unsigned int vgapriv_vgamode; ! 1055: extern unsigned int *vgapriv_vgaAddr; ! 1056: extern unsigned int *vgapriv_vgaVirtAddr; ! 1057: extern int colr_mode; ! 1058: ! 1059: ! 1060: // Alternate VGA routines ! 1061: ! 1062: // Modes that we are interested in... ! 1063: // WG_foo are Wingine modes ! 1064: // VGA_foo are standard VGA modes. ! 1065: ! 1066: #define WG_MODE_40 0 // 640x480, 555 Non-interlaced, 50MHz dot clock ! 1067: #define WG_MODE_42 1 // 800x600, 555 Non-interlaced, 75MHz dot clock ! 1068: #define WG_MODE_50 2 // 640x480, 888 Non-interlaced, 75MHz dot clock ! 1069: #define WG_MODE_51 3 // 1Kx768, 555 Non-interlaced, 75MHz dot clock ! 1070: #define VGA_MODE_3 4 // 80x25 Alphanumeric mode ! 1071: #define VGA_MODE_12 5 // 640x480x4 VGA mode ! 1072: #define N_MODES 6 // Total number of modes ! 1073: ! 1074: /* ! 1075: * VGASetStdRegs() sets the standard VGA registers based on the supplied mode. ! 1076: * The modes are chosen from the above list. New modes can be added by adding ! 1077: * to the tables in vga_modes.c. This routine is usually only a subset of what ! 1078: * needs to be done for enhanced modes. ! 1079: */ ! 1080: extern int VGASetStdRegs(int mode); ! 1081: ! 1082: extern void fill_64K_plane(short colr); ! 1083: extern void save_colr_data(); ! 1084: extern void save_font_data(); ! 1085: extern void set_linr_mono(char max); ! 1086: extern void get_addr_range(short **segment_st, short **segment_nd); ! 1087: extern void select_write_segment(char num); ! 1088: extern void select_read_segment(char num); ! 1089:
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