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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Mach Operating System
27: * Copyright (c) 1991,1990 Carnegie Mellon University
28: * All Rights Reserved.
29: *
30: * Permission to use, copy, modify and distribute this software and its
31: * documentation is hereby granted, provided that both the copyright
32: * notice and this permission notice appear in all copies of the
33: * software, derivative works or modified versions, and any portions
34: * thereof, and that both notices appear in supporting documentation.
35: *
36: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39: *
40: * Carnegie Mellon requests users of this software to return to
41: *
42: * Software Distribution Coordinator or [email protected]
43: * School of Computer Science
44: * Carnegie Mellon University
45: * Pittsburgh PA 15213-3890
46: *
47: * any improvements or extensions that they make and grant Carnegie Mellon
48: * the rights to redistribute these changes.
49: */
50:
51: #ifndef _MACHINE_MACHSPL_H_
52: #define _MACHINE_MACHSPL_H_ 1
53:
54:
55: /*
56: * This file defines the interrupt priority levels used by
57: * machine-dependent code.
58: *
59: * The powerpc has only primitive interrupt masking (all/none),
60: * spl behaviour is done in software
61: */
62:
63: /*
64: * These are the bits in the eirr register that are assigned for various
65: * devices
66: */
67:
68: #define SPL_CLOCK_BIT 0
69: #define SPL_POWER_BIT 1
70: #define SPL_VM_BIT 4
71: #define SPL_CIO_BIT 8
72: #define SPL_HPIB_BIT 9
73: #define SPL_BIO_BIT 9
74: #define SPL_IMP_BIT 9
75: #define SPL_TTY_BIT 16
76: #define SPL_NET_BIT 24
77:
78: /*
79: * The powerpc only has a single level of hardware interrupt. There is
80: * no processor support for disabling certain interrupts whilst allowing
81: * others - this must be done in software.
82: *
83: * The mechanism chosen is fairly standard - a primary interrupt fielder
84: * is used which detects the source of the incoming interrupt and thus its
85: * priority. This routine will either allow the interrupt to pass to
86: * its handler if it is above the current priority, or queue it if it is
87: * not. A word of 32 bits is used for queue flags, thus determining the
88: * number of interrupt levels available.
89: */
90:
91:
92: /*
93: * Convert interrupt levels into machine-independent SPLs as follows:
94: *
95: * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
96: * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
97: * +-+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
98: * |c|p| | |v| | | |b i| | | | | | | |t| | | | | | | |n| | |s| | | | |
99: * |l|w| | |m| | | |i m| | | | | | | |t| | | | | | | |e| | |c| | | | |
100: * |k|r| | | | | | |o p| | | | | | | |y| | | | | | | |t| | |l| | | | |
101: * | | | | | | | | | | | | | | | | | | | | | | | | | | | |k| | | | |
102: * +-+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
103: *
104: * Notes:
105: * - software prohibits more than one machine-dependent SPL per bit on
106: * a given architecture (e.g. ppc). In cases where there
107: * are multiple equivalent devices which interrupt at the same level
108: * (e.g. ASP RS232 #1 and #2), the interrupt table insertion routine
109: * will always add in the unit number (arg0) to offset the entry.
110: * - hard clock must be the first bit (i.e. 0x80000000).
111: * - SPL7 is any non-zero value (since the PSW I-bit is off).
112: * - SPLIMP serves two purposes: blocks network interfaces and blocks
113: * memory allocation via malloc. In theory, SPLLAN would be high
114: *TODONMGS enough. However, on the hp700, the SCSI driver uses malloc at
115: *TODONMGS interrupt time requiring SPLIMP >= SPLBIO. On the 800, we are
116: * still using HP-UX drivers which make the assumption that
117: * SPLIMP >= SPLCIO. New drivers would address both problems.
118: */
119: /* Note also : if any new SPL's are introduced, please add to debugging list*/
120: #define SPLOFF (32 - 0) /* all interrupts disabled TODO NMGS */
121: #define SPLHIGH (32 - 2) /* TODO NMGS any non-zero, non-INTPRI value */
122: #define SPLSCHED SPLHIGH
123: #define SPLCLOCK (32 - 0) /* hard clock */
124: #define SPLPOWER (32 - 1) /* power failure (unused) */
125: #define SPLVM (32 - 4) /* TLB shootdown (unused) */
126: #define SPLBIO (32 - 8) /* block I/O */
127: #define SPLIMP (32 - 8) /* network & malloc */
128: #define SPLTTY (32 - 16) /* TTY */
129: #define SPLNET (32 - 24) /* soft net */
130: #define SPLSCLK (32 - 27) /* soft clock */
131: #define SPLLO (32 - 32) /* no interrupts masked */
132:
133: #define SPL_CMP_GT(a, b) ((unsigned)(a) > (unsigned)(b))
134: #define SPL_CMP_LT(a, b) ((unsigned)(a) < (unsigned)(b))
135: #define SPL_CMP_GE(a, b) ((unsigned)(a) >= (unsigned)(b))
136: #define SPL_CMP_LE(a, b) ((unsigned)(a) <= (unsigned)(b))
137:
138: #define IPLHIGH SPLHIGH
139: #define IPLSCHED SPLSCHED
140: #define IPLDEVICE SPLBIO
141:
142:
143: #ifndef __ASSEMBLER__
144:
145: typedef unsigned spl_t;
146:
147: /*
148: * This is a generic interrupt switch table. It may be used by various
149: * interrupt systems. For each interrupt, it holds a handler and an
150: * TODO NMGS interrupt mask (selected from SPL* or, more generally, INTPRI*).
151: *
152: * So that these tables can be easily found, please prefix them with
153: * the label "itab_" (e.g. "itab_proc").
154: */
155:
156: #if defined(KERNEL_BUILD)
157: #include <mach_debug.h>
158: #endif /* KERNEL_BUILD */
159:
160: struct intrtab {
161: void (*handler)(int); /* ptr to routine to call */
162: unsigned int intpri; /* INTPRI (SPL) with which to call it */
163: int arg; /* 1 arguments to handler: arg0 is unit */
164: };
165:
166: #endif /* __ASSEMBLER__ */
167:
168: #endif /* _MACHINE_MACHSPL_H_ */
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