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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * Portions Copyright (c) 1999 Apple Computer, Inc. All Rights
7: * Reserved. This file contains Original Code and/or Modifications of
8: * Original Code as defined in and that are subject to the Apple Public
9: * Source License Version 1.1 (the "License"). You may not use this file
10: * except in compliance with the License. Please obtain a copy of the
11: * License at http://www.apple.com/publicsource and read it before using
12: * this file.
13: *
14: * The Original Code and all software distributed under the License are
15: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
16: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
17: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
19: * License for the specific language governing rights and limitations
20: * under the License.
21: *
22: * @APPLE_LICENSE_HEADER_END@
23: */
24:
25: /*
26: * Mach Operating System
27: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
28: * All Rights Reserved.
29: *
30: * Permission to use, copy, modify and distribute this software and its
31: * documentation is hereby granted, provided that both the copyright
32: * notice and this permission notice appear in all copies of the
33: * software, derivative works or modified versions, and any portions
34: * thereof, and that both notices appear in supporting documentation.
35: *
36: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39: *
40: * Carnegie Mellon requests users of this software to return to
41: *
42: * Software Distribution Coordinator or [email protected]
43: * School of Computer Science
44: * Carnegie Mellon University
45: * Pittsburgh PA 15213-3890
46: *
47: * any improvements or extensions that they make and grant Carnegie Mellon
48: * the rights to redistribute these changes.
49: */
50: /*
51: */
52: /*
53: * File: scc_8530.h
54: * Author: Alessandro Forin, Carnegie Mellon University
55: * Date: 6/91
56: *
57: * Definitions for the Zilog Z8530 SCC serial line chip
58: */
59:
60: #ifndef _SCC_8530_H_
61: #define _SCC_8530_H_
62:
63: /*
64: * Register map, needs definition of the alignment
65: * used on the specific machine.
66: * #define the 'scc_register_t' data type before
67: * including this header file. For restrictions on
68: * access modes define the set/get_datum macros.
69: * We provide defaults ifnot.
70: */
71:
72:
73: #define SCC_CHANNEL_A 1
74: #define SCC_CHANNEL_B 0
75:
76: #define SCC_MODEM SCC_CHANNEL_A
77: #define SCC_PRINTER SCC_CHANNEL_B
78:
79: #define SCC_DATA_OFFSET 4
80:
81: typedef unsigned char *scc_regmap_t;
82:
83: extern void powermac_scc_set_datum(scc_regmap_t regs, unsigned int offset, unsigned char value);
84: extern unsigned char powermac_scc_get_datum(scc_regmap_t regs, unsigned int offset);
85:
86: #define scc_set_datum(regs, d, v) powermac_scc_set_datum(regs, (d), (v))
87: #define scc_get_datum(regs, d,v) (v) = powermac_scc_get_datum(regs, (d));
88:
89: #define scc_init_reg(regs,chan) { \
90: char tmp; \
91: scc_get_datum(regs, ((chan)<<1),tmp); \
92: scc_get_datum(regs, ((chan)<<1),tmp); \
93: }
94:
95: #define scc_read_reg(regs,chan,reg,val) { \
96: scc_set_datum(regs, ((chan)<<1),reg); \
97: scc_get_datum(regs, ((chan)<<1),val); \
98: }
99:
100: #define scc_read_reg_zero(regs,chan,val) { \
101: scc_get_datum(regs, ((chan)<<1),val); \
102: }
103:
104: #define scc_write_reg(regs,chan,reg,val) { \
105: scc_set_datum(regs, ((chan)<<1),reg); \
106: scc_set_datum(regs, ((chan)<<1),val); \
107: }
108:
109: #define scc_write_reg_zero(regs,chan,val) { \
110: scc_set_datum(regs, ((chan)<<1),val); \
111: }
112:
113: #define scc_read_data(regs,chan,val) { \
114: scc_get_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
115: }
116:
117: #define scc_write_data(regs,chan,val) { \
118: scc_set_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
119: }
120:
121:
122: /*
123: * Addressable registers
124: */
125:
126: #define SCC_RR0 0 /* status register */
127: #define SCC_RR1 1 /* special receive conditions */
128: #define SCC_RR2 2 /* (modified) interrupt vector */
129: #define SCC_RR3 3 /* interrupts pending (cha A only) */
130: #define SCC_RR8 8 /* recv buffer (alias for data) */
131: #define SCC_RR10 10 /* sdlc status */
132: #define SCC_RR12 12 /* BRG constant, low part */
133: #define SCC_RR13 13 /* BRG constant, high part */
134: #define SCC_RR15 15 /* interrupts currently enabled */
135:
136: #define SCC_WR0 0 /* reg select, and commands */
137: #define SCC_WR1 1 /* interrupt and DMA enables */
138: #define SCC_WR2 2 /* interrupt vector */
139: #define SCC_WR3 3 /* receiver params and enables */
140: #define SCC_WR4 4 /* clock/char/parity params */
141: #define SCC_WR5 5 /* xmit params and enables */
142: #define SCC_WR6 6 /* synchr SYNCH/address */
143: #define SCC_WR7 7 /* synchr SYNCH/flag */
144: #define SCC_WR8 8 /* xmit buffer (alias for data) */
145: #define SCC_WR9 9 /* vectoring and resets */
146: #define SCC_WR10 10 /* synchr params */
147: #define SCC_WR11 11 /* clocking definitions */
148: #define SCC_WR12 12 /* BRG constant, low part */
149: #define SCC_WR13 13 /* BRG constant, high part */
150: #define SCC_WR14 14 /* BRG enables and commands */
151: #define SCC_WR15 15 /* interrupt enables */
152:
153: /*
154: * Read registers defines
155: */
156:
157: #define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
158: #define SCC_RR0_ABORT 0x80 /* abort (synchr) */
159: #define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
160: #define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
161: only on intr and after RESI cmd */
162: #define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
163: #define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
164: #define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
165: #define SCC_RR0_ZERO_COUNT 0x02 /* ? */
166: #define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
167:
168: #define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
169: #define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
170: #define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
171: #define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
172: #define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
173: #define SCC_RR1_RESIDUE0 0x08
174: #define SCC_RR1_RESIDUE1 0x04
175: #define SCC_RR1_RESIDUE2 0x02
176: #define SCC_RR1_ALL_SENT 0x01
177:
178: /* RR2 contains the interrupt vector unmodified (channel A) or
179: modified as follows (channel B, if vector-include-status) */
180:
181: #define SCC_RR2_STATUS(val) ((val)&0xe) /* 11/7/95 used to be 0xf */
182:
183: #define SCC_RR2_B_XMIT_DONE 0x0
184: #define SCC_RR2_B_EXT_STATUS 0x2
185: #define SCC_RR2_B_RECV_DONE 0x4
186: #define SCC_RR2_B_RECV_SPECIAL 0x6
187: #define SCC_RR2_A_XMIT_DONE 0x8
188: #define SCC_RR2_A_EXT_STATUS 0xa
189: #define SCC_RR2_A_RECV_DONE 0xc
190: #define SCC_RR2_A_RECV_SPECIAL 0xe
191:
192: /* Interrupts pending, to be read from channel A only (B raz) */
193: #define SCC_RR3_zero 0xc0
194: #define SCC_RR3_RX_IP_A 0x20
195: #define SCC_RR3_TX_IP_A 0x10
196: #define SCC_RR3_EXT_IP_A 0x08
197: #define SCC_RR3_RX_IP_B 0x04
198: #define SCC_RR3_TX_IP_B 0x02
199: #define SCC_RR3_EXT_IP_B 0x01
200:
201: /* RR8 is the receive data buffer, a 3 deep FIFO */
202: #define SCC_RECV_BUFFER SCC_RR8
203: #define SCC_RECV_FIFO_DEEP 3
204:
205: #define SCC_RR10_1CLKS 0x80
206: #define SCC_RR10_2CLKS 0x40
207: #define SCC_RR10_zero 0x2d
208: #define SCC_RR10_LOOP_SND 0x10
209: #define SCC_RR10_ON_LOOP 0x02
210:
211: /* RR12/RR13 hold the timing base, upper byte in RR13 */
212:
213: #define scc_get_timing_base(scc,chan,val) { \
214: register char tmp; \
215: scc_read_reg(scc,chan,SCC_RR12,val);\
216: scc_read_reg(scc,chan,SCC_RR13,tmp);\
217: (val) = ((val)<<8)|(tmp&0xff);\
218: }
219:
220: #define SCC_RR15_BREAK_IE 0x80
221: #define SCC_RR15_TX_UNDERRUN_IE 0x40
222: #define SCC_RR15_CTS_IE 0x20
223: #define SCC_RR15_SYNCH_IE 0x10
224: #define SCC_RR15_DCD_IE 0x08
225: #define SCC_RR15_zero 0x05
226: #define SCC_RR15_ZERO_COUNT_IE 0x02
227:
228:
229: /*
230: * Write registers defines
231: */
232:
233: /* WR0 is used for commands too */
234: #define SCC_RESET_TXURUN_LATCH 0xc0
235: #define SCC_RESET_TX_CRC 0x80
236: #define SCC_RESET_RX_CRC 0x40
237: #define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
238: #define SCC_RESET_ERROR 0x30
239: #define SCC_RESET_TX_IP 0x28
240: #define SCC_IE_NEXT_CHAR 0x20
241: #define SCC_SEND_SDLC_ABORT 0x18
242: #define SCC_RESET_EXT_IP 0x10
243:
244: #define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
245: #define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
246: #define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
247: /* interrupt enable/conditions */
248: #define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
249: #define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
250: #define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
251: #define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
252: #define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
253: #define SCC_WR1_TX_IE 0x02
254: #define SCC_WR1_EXT_IE 0x01
255:
256: /* WR2 is common and contains the interrupt vector (high nibble) */
257:
258: #define SCC_WR3_RX_8_BITS 0xc0
259: #define SCC_WR3_RX_6_BITS 0x80
260: #define SCC_WR3_RX_7_BITS 0x40
261: #define SCC_WR3_RX_5_BITS 0x00
262: #define SCC_WR3_AUTO_ENABLE 0x20
263: #define SCC_WR3_HUNT_MODE 0x10
264: #define SCC_WR3_RX_CRC_ENABLE 0x08
265: #define SCC_WR3_SDLC_SRCH 0x04
266: #define SCC_WR3_INHIBIT_SYNCH 0x02
267: #define SCC_WR3_RX_ENABLE 0x01
268:
269: /* Should be re-written after reset */
270: #define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
271: #define SCC_WR4_CLK_x32 0x80
272: #define SCC_WR4_CLK_x16 0x40
273: #define SCC_WR4_CLK_x1 0x00
274: #define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
275: #define SCC_WR4_SDLC_MODE 0x20
276: #define SCC_WR4_16BIT_SYNCH 0x10
277: #define SCC_WR4_8BIT_SYNCH 0x00
278: #define SCC_WR4_2_STOP 0x0c /* asynch modes */
279: #define SCC_WR4_1_5_STOP 0x08
280: #define SCC_WR4_1_STOP 0x04
281: #define SCC_WR4_SYNCH_MODE 0x00
282: #define SCC_WR4_EVEN_PARITY 0x02
283: #define SCC_WR4_PARITY_ENABLE 0x01
284:
285: #define SCC_WR5_DTR 0x80 /* drive DTR pin */
286: #define SCC_WR5_TX_8_BITS 0x60
287: #define SCC_WR5_TX_6_BITS 0x40
288: #define SCC_WR5_TX_7_BITS 0x20
289: #define SCC_WR5_TX_5_BITS 0x00
290: #define SCC_WR5_SEND_BREAK 0x10
291: #define SCC_WR5_TX_ENABLE 0x08
292: #define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
293: #define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
294: #define SCC_WR5_RTS 0x02 /* drive RTS pin */
295: #define SCC_WR5_TX_CRC_ENABLE 0x01
296:
297: /* Registers WR6 and WR7 are for synch modes data, with among other things: */
298:
299: #define SCC_WR6_BISYNCH_12 0x0f
300: #define SCC_WR6_SDLC_RANGE_MASK 0x0f
301: #define SCC_WR7_SDLC_FLAG 0x7e
302:
303: /* WR8 is the transmit data buffer (no FIFO) */
304: #define SCC_XMT_BUFFER SCC_WR8
305:
306: #define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
307: #define SCC_WR9_RESET_CHA_A 0x80
308: #define SCC_WR9_RESET_CHA_B 0x40
309: #define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
310: #define SCC_WR9_STATUS_HIGH 0x10
311: #define SCC_WR9_MASTER_IE 0x08
312: #define SCC_WR9_DLC 0x04 /* disable-lower-chain */
313: #define SCC_WR9_NV 0x02 /* no vector */
314: #define SCC_WR9_VIS 0x01 /* vector-includes-status */
315:
316: #define SCC_WR10_CRC_PRESET 0x80
317: #define SCC_WR10_FM0 0x60
318: #define SCC_WR10_FM1 0x40
319: #define SCC_WR10_NRZI 0x20
320: #define SCC_WR10_NRZ 0x00
321: #define SCC_WR10_ACTIVE_ON_POLL 0x10
322: #define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
323: #define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
324: #define SCC_WR10_LOOP_MODE 0x02
325: #define SCC_WR10_6BIT_SYNCH 0x01
326: #define SCC_WR10_8BIT_SYNCH 0x00
327:
328: #define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
329: #define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
330: #define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
331: #define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
332: #define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
333: #define SCC_WR11_XTLK_DPLL 0x18
334: #define SCC_WR11_XTLK_BAUDR 0x10
335: #define SCC_WR11_XTLK_TRc_PIN 0x08
336: #define SCC_WR11_XTLK_RTc_PIN 0x00
337: #define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
338: #define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
339: #define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
340: #define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
341: #define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
342:
343: /* WR12/WR13 are for timing base preset */
344: #define scc_set_timing_base(scc,chan,val) { \
345: scc_write_reg(scc,chan,SCC_RR12,val);\
346: scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
347: }
348:
349: /* More commands in this register */
350: #define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
351: #define SCC_WR14_FM_MODE 0xc0
352: #define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
353: #define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
354: #define SCC_WR14_DISABLE_DPLL 0x60
355: #define SCC_WR14_RESET_CLKMISS 0x40
356: #define SCC_WR14_SEARCH_MODE 0x20
357: /* ..and more bitsy */
358: #define SCC_WR14_LOCAL_LOOPB 0x10
359: #define SCC_WR14_AUTO_ECHO 0x08
360: #define SCC_WR14_DTR_REQUEST 0x04
361: #define SCC_WR14_BAUDR_SRC 0x02
362: #define SCC_WR14_BAUDR_ENABLE 0x01
363:
364: #define SCC_WR15_BREAK_IE 0x80
365: #define SCC_WR15_TX_UNDERRUN_IE 0x40
366: #define SCC_WR15_CTS_IE 0x20
367: #define SCC_WR15_SYNCHUNT_IE 0x10
368: #define SCC_WR15_DCD_IE 0x08
369: #define SCC_WR15_zero 0x05
370: #define SCC_WR15_ZERO_COUNT_IE 0x02
371:
372: #define NSCC_LINE 2 /* How many lines are support per 8530 */
373: /*
374: * Driver status
375: */
376:
377: struct scc_dma_ops {
378: void (*scc_dma_init)(int chan);
379: void (*scc_dma_setup_8530)(int chan);
380: void (*scc_dma_start_rx)(int chan);
381: void (*scc_dma_reset_rx)(int chan);
382: void (*scc_dma_start_tx)(int chan, struct tty *tp);
383: void (*scc_dma_pause_tx)(int chan);
384: void (*scc_dma_continue_tx)(int chan);
385: };
386:
387: #define SCC_FLAGS_DMA_PAUSED 0x00001 /* DMA has been paused because of XON/XOFF */
388: #define SCC_FLAGS_DMA_TX_BUSY 0x00002 /* On going DMA operation.. */
389:
390: struct scc_softreg {
391: unsigned char wr1;
392: unsigned char wr4;
393: unsigned char wr5;
394: unsigned char wr14;
395:
396: unsigned long speed;
397: unsigned long flags;
398: unsigned long dma_flags;
399: };
400:
401:
402: struct scc_softc {
403: scc_regmap_t regs;
404: struct scc_dma_ops *dma_ops;
405:
406: /* software copy of some write regs, for reg |= */
407: struct scc_softreg softr[NSCC_LINE];
408:
409: int flags;
410: int modem[NSCC_LINE]; /* Mach modem bits (TM_DTR etc). */
411: int dma_initted;
412:
413: char polling_mode;
414: char probed_once;
415:
416: boolean_t full_modem;
417: };
418:
419: typedef struct scc_softc *scc_softc_t;
420: extern struct scc_softc scc_softc[];
421:
422: #endif /*_SCC_8530_H_*/
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