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1.1 root 1: /* wereg.h */
2: /*
3: Copyright (C) 1992 Ross Biro
4:
5: This program is free software; you can redistribute it and/or modify
6: it under the terms of the GNU General Public License as published by
7: the Free Software Foundation; either version 1, or (at your option)
8: any later version.
9:
10: This program is distributed in the hope that it will be useful,
11: but WITHOUT ANY WARRANTY; without even the implied warranty of
12: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13: GNU General Public License for more details.
14:
15: You should have received a copy of the GNU General Public License
16: along with this program; if not, write to the Free Software
17: Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18:
19: The Author may be reached as [email protected] or
20: C/O Department of Mathematics; Stanford University; Stanford, CA 94305
21: */
22: /* This is based on if_wereg.h from bsd386 */
23:
24: /* Uncomment the next line if you are having troubles with your
25: 8 bit card being recognized as 16 bit. */
26: /* #define FORCE_8BIT */
27:
28: struct wd_ring
29: {
30: unsigned char status; /* status */
31: /* format of status
32: bit
33: 0 packet ok
34: 1 crc error
35: 2 frame alignment error
36: 3 fifo overrun
37: */
38: #define STRECVD 0xf1
39: unsigned char next; /* pointer to next packet. */
40: unsigned short count; /*packet lenght in bytes + 4 */
41: };
42:
43: /* Format of command register.
44: bits
45: 0 stop
46: 1 start
47: 2 transmit packet
48: 3-5 Remote DMA command
49: 6-7 Page Select */
50:
51: #define CSTOP 0x1
52: #define CSTART 0x2
53: #define CTRANS 0x4
54: #define CRDMA 0x38
55: #define CRDMA_SHIFT 3
56: #define CPAGE 0xc0
57: #define CPAGE_SHIFT 6
58:
59: #define CPAGE1 0x40
60:
61:
62: #define CPAGE1 0x40
63:
64: /* interrupt status defenitions
65: bits
66: 0 Recv.
67: 1 Transmit
68: 2 RcvErr
69: 3 Transmit Err
70: 4 Overwrite warning
71: 5 Counter overflow
72: 6 Remote DMA complete
73: 7 Reset Status */
74:
75: #define IRCV 0x1
76: #define ITRS 0x2
77: #define IRCE 0x4
78: #define ITRE 0x8
79: #define IOVER 0x10
80: #define ICOUNTERS 0x20
81: #define IDMA 0x40
82: #define IRESET 0x80
83: #define IOVER 0x10
84: #define ICOUNTERS 0x20
85: #define IDMA 0x40
86: #define IRESET 0x80
87:
88: /* transmit status format
89: bits
90: 0 Packet transmitted ok.
91: 1 Non Deferred transmition
92: 2 Transmit collied
93: 3 Transmit aborted
94: 4 Carrier Sense Lost
95: 5 Fifo Underrun
96: 6 CD Heartbeat
97: 7 Out of Window Collision */
98:
99: #define TROK 0x1
100: #define TRAB 0x4
101:
102: /* Some ID stuff */
103: #define WD_ID1 0x03
104: #define WD_ID2 0x05
105: #define WD_CHECK 0xff
106: #define WD_PAGE 256 /* page size in bytes. */
107: #define WD_TXBS 6 /* size of transmit buffer in pages. */
108: #define WD_MAX_PAGES 32 /* Number of pages off ram on card (8k) */
109: #define WD_NIC 16 /* i/o base offset to NIC */
110:
111: /* Some configuration stuff. */
112: /* where the memory is mapped in. */
113: #define WD_MEM (dev->mem_start)
114: #define WD_BUFFEND (dev->mem_end)
115: #define WD_MEMSIZE (WD_BUFFEND-WD_MEM)
116: #define WD_BASE (dev->base_addr)
117:
118: #define TRANS_MASK 0xa
119: #define RECV_MASK 0x5
120: #define WD_DCONFIG 0x48
121: #define WD_RCONFIG 0x4
122: #define WD_MCONFIG 0x20
123: #define WD_TCONFIG 0x0
124: #define WD_IMEM (((WD_MEM>>13) & 0x3f)|0x40)
125:
126: /* WD registers. */
127: #define WD_ROM (WD_BASE+8)
128: #define WD_CTL (WD_BASE+0)
129:
130: /* WD NIC register offsets */
131: #define WD_COMM (WD_BASE+WD_NIC+0x00) /* command register */
132: #define WD_PSTRT (WD_BASE+WD_NIC+0x01) /* page start register */
133: #define WD_PSTOP (WD_BASE+WD_NIC+0x02) /* page stop register */
134: #define WD_BNDR (WD_BASE+WD_NIC+0x03) /* Boundary Pointer */
135: #define WD_TRST (WD_BASE+WD_NIC+0x04) /* Transmit Status */
136: #define WD_TRPG (WD_BASE+WD_NIC+0x04) /* Transmit Page */
137: #define WD_TB0 (WD_BASE+WD_NIC+0x05) /* Transmit byte count, low */
138: #define WD_TB1 (WD_BASE+WD_NIC+0x06) /* Transmit byte count, high */
139: #define WD_ISR (WD_BASE+WD_NIC+0x07) /* Interrupt status register */
140: #define WD_RBY0 (WD_BASE+WD_NIC+0x0a) /* remote byte count low. */
141: #define WD_RBY1 (WD_BASE+WD_NIC+0x0b) /* remote byte count high. */
142: #define WD_RCC (WD_BASE+WD_NIC+0x0c) /* receive configuration */
143: #define WD_TRC (WD_BASE+WD_NIC+0x0d) /* transmit configuration */
144: #define WD_DCR (WD_BASE+WD_NIC+0x0e) /* data configuration */
145: #define WD_IMR (WD_BASE+WD_NIC+0x0f) /* Interrupt Mask register. */
146: #define WD_PAR0 (WD_BASE+WD_NIC+0x01)
147: #define WD_CUR (WD_BASE+WD_NIC+0x07)
148: #define WD_MAR0 (WD_BASE+WD_NIC+0x08)
149:
150: /* rth additions */
151:
152: #define EN_CMD (WD_BASE+0)
153: #define EN_REG1 (WD_BASE+1)
154: #define EN_REG5 (WD_BASE+5)
155: #define EN_SAPROM (WD_BASE+8)
156: #define EN_REGE (WD_BASE+0x0e)
157: #define EN_OFFSET 16
158:
159: /* WD Commands for EN_CMD */
160: #define EN_RESET
161: #define EN_MEMEN 0x40
162: #define EN_MEM_MASK 0x3f
163:
164: /* WD Bus Register bits */
165: #define BUS16 1
166:
167: /* WD REG5 Commands */
168: #define MEM16ENABLE 0x80
169: #define LAN16ENABLE 0x40
170: #define MEMMASK 0x1f
171: #define BIT19 0x1
172:
173: /* Memory test pattern to use */
174: #define TESTPATTERN 0x5a
175:
176: /* Western Digital Additional Registers */
177:
178: /* National Semiconductor Definitions */
179:
180: /* Page 0 */
181: #define CR (WD_BASE+WD_NIC+0) /* RW - Command */
182: #define CLDA0 (WD_BASE+WD_NIC+1) /* R - Current Local DMA Address 0 */
183: #define PSTART (WD_BASE+WD_NIC+1) /* W - Page Start Register */
184: #define CLDA1 (WD_BASE+WD_NIC+2) /* R - Current Local DMA Address 1 */
185: #define PSTOP (WD_BASE+WD_NIC+2) /* W - Page Stop Register */
186: #define BNRY (WD_BASE+WD_NIC+3) /* RW - Boundry Pointer */
187: #define TSR (WD_BASE+WD_NIC+4) /* R - Transmit Status Register */
188: #define TPSR (WD_BASE+WD_NIC+4) /* W - Transmit Page Start */
189: #define NCR (WD_BASE+WD_NIC+5) /* R - Number of Collisions */
190: #define TBCR0 (WD_BASE+WD_NIC+5) /* W - Transmit Byte Count 0 */
191: #define FIFO (WD_BASE+WD_NIC+6) /* R - FIFO */
192: #define TBCR1 (WD_BASE+WD_NIC+6) /* W - Transmit Byte Count 1 */
193: #define ISR (WD_BASE+WD_NIC+7) /* RW - Interrupt Status Register */
194: #define CRDA0 (WD_BASE+WD_NIC+8) /* R - Current Remote DMA Address 0 */
195: #define RSAR0 (WD_BASE+WD_NIC+8) /* W - Remote Start Address 0 */
196: #define CRDA1 (WD_BASE+WD_NIC+9) /* R - Current Remote DMA Address 1 */
197: #define RSAR1 (WD_BASE+WD_NIC+9) /* W - Remote Start Address 1 */
198: /* R - Reserved */
199: #define RBCR0 (WD_BASE+WD_NIC+0x0a) /* W - Remote Byte Count 0 */
200: /* R - Reserved */
201: #define RBCR1 (WD_BASE+WD_NIC+0x0b) /* W - Remote Byte Count 1 */
202: #define RSR (WD_BASE+WD_NIC+0x0c) /* R - Receive Status Register */
203: #define RCR (WD_BASE+WD_NIC+0x0c) /* W - Receive Configuration */
204: #define CNTR0 (WD_BASE+WD_NIC+0x0d) /* R - Frame Alignment Errors 0 */
205: #define TCR (WD_BASE+WD_NIC+0x0d) /* W - Transmit Configuration */
206: #define CNTR1 (WD_BASE+WD_NIC+0x0e) /* R - Frame Alignment Errors 1 */
207: #define DCR (WD_BASE+WD_NIC+0x0e) /* W - Data Configuration */
208: #define CNTR2 (WD_BASE+WD_NIC+0x0f) /* R - Missed Packet Errors */
209: #define IMR (WD_BASE+WD_NIC+0x0f) /* W - Interrupt Mask Register */
210:
211: /* Page 1 */
212: /* RW - Command */
213: #define PAR0 (WD_BASE+WD_NIC+0x01) /* RW - Physical Address 0 */
214: #define PAR1 (WD_BASE+WD_NIC+0x02) /* RW - Physical Address 1 */
215: #define PAR2 (WD_BASE+WD_NIC+0x03) /* RW - Physical Address 2 */
216: #define PAR3 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 3 */
217: #define PAR4 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 4 */
218: #define PAR5 (WD_BASE+WD_NIC+0x05) /* RW - Physical Address 5 */
219: #define PAR6 (WD_BASE+WD_NIC+0x06) /* RW - Physical Address 6 */
220: #define CURR (WD_BASE+WD_NIC+0x07) /* RW - Current Page */
221: #define MAR0 (WD_BASE+WD_NIC+0x08) /* RW - Multicast Address 0 */
222: #define MAR1 (WD_BASE+WD_NIC+0x09) /* RW - Multicast Address 1 */
223: #define MAR2 (WD_BASE+WD_NIC+0x0a) /* RW - Multicast Address 2 */
224: #define MAR3 (WD_BASE+WD_NIC+0x0b) /* RW - Multicast Address 3 */
225: #define MAR4 (WD_BASE+WD_NIC+0x0c) /* RW - Multicast Address 4 */
226: #define MAR5 (WD_BASE+WD_NIC+0x0d) /* RW - Multicast Address 5 */
227: #define MAR6 (WD_BASE+WD_NIC+0x0e) /* RW - Multicast Address 6 */
228: #define MAR7 (WD_BASE+WD_NIC+0x0f) /* RW - Multicast Address 7 */
229:
230: /* Page 2 */
231: /* Page 2 Registers are RW opposite Page 0 */
232: /* and should be used for diagnostic purposes only */
233:
234: /* Command Register bits */
235: #define STOP 1 /* In progress jobs finished, software reset */
236: #define STA 2 /* Activate the NIC */
237: #define TXP 4 /* Initiate TX packet */
238: #define RD0 8 /* Remote DMA commands */
239: #define RD1 0x10
240: #define RD2 0x20
241: #define PS0 0x40 /* Page Select */
242: #define PS1 0x80 /* 00 = 0, 01 = 1, 10 = 2, 11 = reserved */
243:
244: #define PAGE0 ~(PS0|PS1) /* Remember to AND this */
245: #define PAGE1 PS0 /* these can be OR'd */
246: #define PAGE2 PS1
247: #define NO_DMA RD2
248:
249: /* Interrupt Status Register bits */
250: #define PRX 1 /* Packet received with no errors */
251: #define PTX 2 /* Packet transmitted with no errors */
252: #define RXE 4 /* Packet received with errors */
253: #define TXE 8 /* Transmit aborted with errors */
254: #define OVW 0x10 /* Overwrite warning */
255: #define CNT 0x20 /* Counter overflow warning */
256: #define RDC 0x40 /* Remote DMA complete */
257: #define RST 0x80 /* Reset status - does not cause interrupts */
258:
259: /* Interrupt Mask Register - 1 = enabled */
260: #define PRXE 1 /* Packet received */
261: #define PTXE 2 /* Packet transmitted */
262: #define RXEE 4 /* Receive error */
263: #define TXEE 8 /* Transmit error */
264: #define OVWE 0x10 /* Overwrite error */
265: #define CNTE 0x20 /* Counter overflow */
266: #define RDCE 0x40 /* Remote DMA complete */
267:
268: /* Data Configuration Register */
269: #define WTS 1 /* Word Transfer 0 = byte, 1 = word */
270: #define BOS 2 /* Byte Order 0 = 8086, 1 = 68000 */
271: #define LAS 4 /* Long Address 0 = 16bit, 1 = 32 bit DMA */
272: #define LS 8 /* Loopback = 0, 1 = Normal */
273: #define AR 0x10 /* Autoinitialize = 1 DMA, 0 = software */
274: #define FT0 0x20 /* FIFO Threshold (word mode /2 ) */
275: #define FT1 0x40 /* 00 = 2, 01 = 4, 10 = 8, 11 = 12 bytes */
276:
277: /* Transmit Configuration Register */
278: #define CRCI 1 /* CRC inhibit = 1, append = 0 */
279: #define LB0 2 /* Loopback control 00 = normal loopback */
280: #define LB1 4 /* 01 = internal, 10 = external1, 11 = external2 */
281: #define ATD 8 /* Auto Transmit Enable = 1 tx inhibit enabled */
282: #define OFST 0x10 /* Collision offset 1 = modify to low priority mode */
283:
284: /* Transmitter Status Register */
285: #define PTXOK 1 /* Packet transmitted without error */
286: /* reserved */
287: #define COL 4 /* Transmit collided, check NCR for count */
288: #define ABT 8 /* Transmit aborted - 16 tries */
289: #define CRS 0x10 /* Carrier Sense lost */
290: #define FU 0x20 /* FIFO underrun */
291: #define CDH 0x40 /* CD Heartbeat failed */
292: #define OWC 0x80 /* Out of window collision */
293:
294: /* Receive configuration Register */
295: #define SEP 1 /* Save error packets = 1 */
296: #define ARUNT 2 /* Accept RUNT packets < 64 bytes */
297: #define AB 4 /* Accept Broadcast packets */
298: #define AM 8 /* Accept Multicast packets */
299: #define PRO 0x10 /* Promiscuous mode */
300: #define MON 0x20 /* Monitor mode */
301:
302: /* Receive Status Register */
303: #define PRX 1 /* Packet received without error */
304: #define CRC 2 /* CRC error */
305: #define FAE 4 /* Frame Alignment error */
306: #define FO 8 /* FIFO overrun error */
307: #define MPA 0x10 /* Missed packet */
308: #define PHY 0x20 /* Physical = 0, Multicast/Broadcast = 1 */
309: #define DIS 0x40 /* Receiver disabled (monitor mode) */
310: #define DFR 0x80 /* Deferring - jabber on line */
311:
312:
313: /* rth additions */
314:
315: #define EN_CMD (WD_BASE+0)
316: #define EN_REG1 (WD_BASE+1)
317: #define EN_REG5 (WD_BASE+5)
318: #define EN_SAPROM (WD_BASE+8)
319: #define EN_REGE (WD_BASE+0x0e)
320: #define EN_OFFSET 16
321:
322: /* WD Commands for EN_CMD */
323: #define EN_RESET
324: #define EN_MEMEN 0x40
325: #define EN_MEM_MASK 0x3f
326:
327: /* WD Bus Register bits */
328: #define BUS16 1
329:
330: /* WD REG5 Commands */
331: #define MEM16ENABLE 0x80
332: #define LAN16ENABLE 0x40
333: #define MEMMASK 0x1f
334: #define BIT19 0x1
335:
336: /* Memory test pattern to use */
337: #define TESTPATTERN 0x5a
338:
339: /* Western Digital Additional Registers */
340:
341: /* National Semiconductor Definitions */
342:
343: /* Page 0 */
344: #define CR (WD_BASE+WD_NIC+0) /* RW - Command */
345: #define CLDA0 (WD_BASE+WD_NIC+1) /* R - Current Local DMA Address 0 */
346: #define PSTART (WD_BASE+WD_NIC+1) /* W - Page Start Register */
347: #define CLDA1 (WD_BASE+WD_NIC+2) /* R - Current Local DMA Address 1 */
348: #define PSTOP (WD_BASE+WD_NIC+2) /* W - Page Stop Register */
349: #define BNRY (WD_BASE+WD_NIC+3) /* RW - Boundry Pointer */
350: #define TSR (WD_BASE+WD_NIC+4) /* R - Transmit Status Register */
351: #define TPSR (WD_BASE+WD_NIC+4) /* W - Transmit Page Start */
352: #define NCR (WD_BASE+WD_NIC+5) /* R - Number of Collisions */
353: #define TBCR0 (WD_BASE+WD_NIC+5) /* W - Transmit Byte Count 0 */
354: #define FIFO (WD_BASE+WD_NIC+6) /* R - FIFO */
355: #define TBCR1 (WD_BASE+WD_NIC+6) /* W - Transmit Byte Count 1 */
356: #define ISR (WD_BASE+WD_NIC+7) /* RW - Interrupt Status Register */
357: #define CRDA0 (WD_BASE+WD_NIC+8) /* R - Current Remote DMA Address 0 */
358: #define RSAR0 (WD_BASE+WD_NIC+8) /* W - Remote Start Address 0 */
359: #define CRDA1 (WD_BASE+WD_NIC+9) /* R - Current Remote DMA Address 1 */
360: #define RSAR1 (WD_BASE+WD_NIC+9) /* W - Remote Start Address 1 */
361: /* R - Reserved */
362: #define RBCR0 (WD_BASE+WD_NIC+0x0a) /* W - Remote Byte Count 0 */
363: /* R - Reserved */
364: #define RBCR1 (WD_BASE+WD_NIC+0x0b) /* W - Remote Byte Count 1 */
365: #define RSR (WD_BASE+WD_NIC+0x0c) /* R - Receive Status Register */
366: #define RCR (WD_BASE+WD_NIC+0x0c) /* W - Receive Configuration */
367: #define CNTR0 (WD_BASE+WD_NIC+0x0d) /* R - Frame Alignment Errors 0 */
368: #define TCR (WD_BASE+WD_NIC+0x0d) /* W - Transmit Configuration */
369: #define CNTR1 (WD_BASE+WD_NIC+0x0e) /* R - Frame Alignment Errors 1 */
370: #define DCR (WD_BASE+WD_NIC+0x0e) /* W - Data Configuration */
371: #define CNTR2 (WD_BASE+WD_NIC+0x0f) /* R - Missed Packet Errors */
372: #define IMR (WD_BASE+WD_NIC+0x0f) /* W - Interrupt Mask Register */
373:
374: /* Page 1 */
375: /* RW - Command */
376: #define PAR0 (WD_BASE+WD_NIC+0x01) /* RW - Physical Address 0 */
377: #define PAR1 (WD_BASE+WD_NIC+0x02) /* RW - Physical Address 1 */
378: #define PAR2 (WD_BASE+WD_NIC+0x03) /* RW - Physical Address 2 */
379: #define PAR3 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 3 */
380: #define PAR4 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 4 */
381: #define PAR5 (WD_BASE+WD_NIC+0x05) /* RW - Physical Address 5 */
382: #define PAR6 (WD_BASE+WD_NIC+0x06) /* RW - Physical Address 6 */
383: #define CURR (WD_BASE+WD_NIC+0x07) /* RW - Current Page */
384: #define MAR0 (WD_BASE+WD_NIC+0x08) /* RW - Multicast Address 0 */
385: #define MAR1 (WD_BASE+WD_NIC+0x09) /* RW - Multicast Address 1 */
386: #define MAR2 (WD_BASE+WD_NIC+0x0a) /* RW - Multicast Address 2 */
387: #define MAR3 (WD_BASE+WD_NIC+0x0b) /* RW - Multicast Address 3 */
388: #define MAR4 (WD_BASE+WD_NIC+0x0c) /* RW - Multicast Address 4 */
389: #define MAR5 (WD_BASE+WD_NIC+0x0d) /* RW - Multicast Address 5 */
390: #define MAR6 (WD_BASE+WD_NIC+0x0e) /* RW - Multicast Address 6 */
391: #define MAR7 (WD_BASE+WD_NIC+0x0f) /* RW - Multicast Address 7 */
392:
393: /* Page 2 */
394: /* Page 2 Registers are RW opposite Page 0 */
395: /* and should be used for diagnostic purposes only */
396:
397: /* Command Register bits */
398: #define STOP 1 /* In progress jobs finished, software reset */
399: #define STA 2 /* Activate the NIC */
400: #define TXP 4 /* Initiate TX packet */
401: #define RD0 8 /* Remote DMA commands */
402: #define RD1 0x10
403: #define RD2 0x20
404: #define PS0 0x40 /* Page Select */
405: #define PS1 0x80 /* 00 = 0, 01 = 1, 10 = 2, 11 = reserved */
406:
407: #define PAGE0 ~(PS0|PS1) /* Remember to AND this */
408: #define PAGE1 PS0 /* these can be OR'd */
409: #define PAGE2 PS1
410: #define NO_DMA RD2
411:
412: /* Interrupt Status Register bits */
413: #define PRX 1 /* Packet received with no errors */
414: #define PTX 2 /* Packet transmitted with no errors */
415: #define RXE 4 /* Packet received with errors */
416: #define TXE 8 /* Transmit aborted with errors */
417: #define OVW 0x10 /* Overwrite warning */
418: #define CNT 0x20 /* Counter overflow warning */
419: #define RDC 0x40 /* Remote DMA complete */
420: #define RST 0x80 /* Reset status - does not cause interrupts */
421:
422: /* Interrupt Mask Register - 1 = enabled */
423: #define PRXE 1 /* Packet received */
424: #define PTXE 2 /* Packet transmitted */
425: #define RXEE 4 /* Receive error */
426: #define TXEE 8 /* Transmit error */
427: #define OVWE 0x10 /* Overwrite error */
428: #define CNTE 0x20 /* Counter overflow */
429: #define RDCE 0x40 /* Remote DMA complete */
430:
431: /* Data Configuration Register */
432: #define WTS 1 /* Word Transfer 0 = byte, 1 = word */
433: #define BOS 2 /* Byte Order 0 = 8086, 1 = 68000 */
434: #define LAS 4 /* Long Address 0 = 16bit, 1 = 32 bit DMA */
435: #define LS 8 /* Loopback = 0, 1 = Normal */
436: #define AR 0x10 /* Autoinitialize = 1 DMA, 0 = software */
437: #define FT0 0x20 /* FIFO Threshold (word mode /2 ) */
438: #define FT1 0x40 /* 00 = 2, 01 = 4, 10 = 8, 11 = 12 bytes */
439:
440: /* Transmit Configuration Register */
441: #define CRCI 1 /* CRC inhibit = 1, append = 0 */
442: #define LB0 2 /* Loopback control 00 = normal loopback */
443: #define LB1 4 /* 01 = internal, 10 = external1, 11 = external2 */
444: #define ATD 8 /* Auto Transmit Enable = 1 tx inhibit enabled */
445: #define OFST 0x10 /* Collision offset 1 = modify to low priority mode */
446:
447: /* Transmitter Status Register */
448: #define PTXOK 1 /* Packet transmitted without error */
449: /* reserved */
450: #define COL 4 /* Transmit collided, check NCR for count */
451: #define ABT 8 /* Transmit aborted - 16 tries */
452: #define CRS 0x10 /* Carrier Sense lost */
453: #define FU 0x20 /* FIFO underrun */
454: #define CDH 0x40 /* CD Heartbeat failed */
455: #define OWC 0x80 /* Out of window collision */
456:
457: /* Receive configuration Register */
458: #define SEP 1 /* Save error packets = 1 */
459: #define ARUNT 2 /* Accept RUNT packets < 64 bytes */
460: #define AB 4 /* Accept Broadcast packets */
461: #define AM 8 /* Accept Multicast packets */
462: #define PRO 0x10 /* Promiscuous mode */
463: #define MON 0x20 /* Monitor mode */
464:
465: /* Receive Status Register */
466: #define PRX 1 /* Packet received without error */
467: #define CRC 2 /* CRC error */
468: #define FAE 4 /* Frame Alignment error */
469: #define FO 8 /* FIFO overrun error */
470: #define MPA 0x10 /* Missed packet */
471: #define PHY 0x20 /* Physical = 0, Multicast/Broadcast = 1 */
472: #define DIS 0x40 /* Receiver disabled (monitor mode) */
473: #define DFR 0x80 /* Deferring - jabber on line */
474:
475:
476:
477:
478:
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