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1.1 root 1: #include "u.h"
2: #include "../port/lib.h"
3: #include "mem.h"
4: #include "dat.h"
5: #include "fns.h"
6: #include "../port/error.h"
7: #include "io.h"
8: #include "devtab.h"
9:
10: #include "ether.h"
11:
12: /*
13: * National Semiconductor DP83905 AT/LANTIC.
14: *
15: * It doesn't seem possible to tell which mode (NE2000 or WD8003)
16: * the chip is configured in without a lot of work. For now we'll
17: * just assume WD8003 mode.
18: * Driver written for the Dauphin DTR-1.
19: */
20: enum { /* Shared Memory Compatible Mode */
21: Control1 = 0x00, /* (WO) */
22: ATDetect = 0x01, /* (RO) */
23: Control2 = 0x05, /* (WO) */
24: Lar = 0x08, /* LAN Address Registers */
25: };
26:
27: enum { /* Control1 */
28: Rst = 0x80, /* software reset */
29: Meme = 0x40, /* memory enable */
30: };
31:
32: enum { /* ATDetect */
33: ATdet = 0x01, /* 8 or 16-bit slot */
34: };
35:
36: enum { /* Control2 */
37: Memw = 0x40, /* */
38: M16 = 0x80, /* */
39: };
40:
41: static void*
42: read(Ctlr *ctlr, void *to, ulong from, ulong len)
43: {
44: /*
45: * In this case, 'from' is an index into the shared memory.
46: */
47: memmove(to, (void*)(ctlr->card.mem+from), len);
48: return to;
49: }
50:
51: static void*
52: write(Ctlr *ctlr, ulong to, void *from, ulong len)
53: {
54: /*
55: * In this case, 'to' is an index into the shared memory.
56: */
57: memmove((void*)(ctlr->card.mem+to), from, len);
58: return (void*)to;
59: }
60:
61: /*
62: * Get configuration parameters, enable memory.
63: * There are opportunities here for buckets of code.
64: * We'll try to resist.
65: */
66: static int
67: reset(Ctlr *ctlr)
68: {
69: int i;
70: uchar control1, control2;
71: ulong port;
72:
73: /*
74: * Set up the software configuration.
75: * Use defaults for port, irq, mem and size if not specified.
76: * Defaults are set for the dumb 8003E which can't be
77: * autoconfigured.
78: */
79: if(ctlr->card.port == 0)
80: ctlr->card.port = 0x280;
81: if(ctlr->card.irq == 0)
82: ctlr->card.irq = 3;
83: if(ctlr->card.mem == 0)
84: ctlr->card.mem = 0xD0000;
85: if(ctlr->card.size == 0)
86: ctlr->card.size = 8*1024;
87:
88: ctlr->card.reset = reset;
89: ctlr->card.attach = dp8390attach;
90: ctlr->card.mode = dp8390mode;
91: ctlr->card.read = read;
92: ctlr->card.write = write;
93: ctlr->card.receive = dp8390receive;
94: ctlr->card.transmit = dp8390transmit;
95: ctlr->card.intr = dp8390intr;
96: ctlr->card.watch = 0;
97: ctlr->card.ram = 1;
98:
99: port = ctlr->card.port;
100: for(i = 0; i < sizeof(ctlr->ea); i++)
101: ctlr->ea[i] = inb(port+Lar+i);
102:
103: control1 = Meme|((ctlr->card.mem>>13) & 0x3F);
104: control2 = (ctlr->card.mem>>19) & 0x1F;
105: if(ctlr->card.bit16 = (inb(port+ATDetect) & ATdet))
106: control2 |= M16|Memw;
107: ctlr->card.mem |= KZERO;
108:
109: /*
110: * Set the DP8390 ring addresses.
111: */
112: ctlr->card.dp8390 = port+0x10;
113: ctlr->card.tstart = 0;
114: ctlr->card.pstart = HOWMANY(sizeof(Etherpkt), Dp8390BufSz);
115: ctlr->card.pstop = HOWMANY(ctlr->card.size, Dp8390BufSz);
116:
117: /*
118: * Enable interface RAM, set interface width.
119: */
120: outb(port+Control1, control1);
121: outb(port+Control2, control2);
122:
123: /*
124: * Finally, init the 8390 and set the
125: * ethernet address.
126: */
127: dp8390reset(ctlr);
128: dp8390setea(ctlr);
129:
130: return 0;
131: }
132:
133: void
134: ether83905link(void)
135: {
136: addethercard("DP83905", reset);
137: }
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