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1.1 root 1: /*++ BUILD Version: 0003 // Increment this if a change has global effects
2: */
3: //*++
4: //
5: // Copyright (c) 1990-1993 Microsoft Corporation
6: //
7: // Module Name:
8: //
9: // kxmips.h
10: //
11: // Abstract:
12: //
13: // This module contains the nongenerated part of the MIPS assembler
14: // header file. In general, it contains processor architecture constant
15: // information, however some assembler macros are also included.
16: //
17: // Author:
18: //
19: // David N. Cutler (davec) 23-Mar-1990
20: //
21: // Revision History:
22: //
23: //--*/
24:
25: //
26: // Define load linked and store conditional opcodes if system is not an r4000
27: //
28:
29: #if defined(R3000)
30:
31: #define ll lw
32: #define sc sw
33:
34: #endif
35:
36: #ifdef SABLE
37:
38: #define bal jal
39:
40: #endif
41:
42: //
43: // Define soft reset vector address for nonhandled cache parity errors.
44: //
45:
46: #if defined(R4000)
47:
48: #define SOFT_RESET_VECTOR 0xbfc00300 // default parity error routine address
49:
50: #endif
51:
52: //
53: // Define low memory transfer vector address and TB index address (temporary).
54: //
55:
56: #define TRANSFER_VECTOR (KSEG1_BASE + 0x400) // exception handler address
57:
58: //
59: // Define standard integer registers.
60: //
61:
62: #define zero $0 // read zero, writes ignored
63: #define AT $1 // assembler temporary
64: #define v0 $2 // return value
65: #define v1 $3 //
66: #define a0 $4 // argument registers
67: #define a1 $5 //
68: #define a2 $6 //
69: #define a3 $7 //
70: #define t0 $8 // caller saved registers
71: #define t1 $9 //
72: #define t2 $10 //
73: #define t3 $11 //
74: #define t4 $12 //
75: #define t5 $13 //
76: #define t6 $14 //
77: #define t7 $15 //
78: #define s0 $16 // callee saved registers
79: #define s1 $17 //
80: #define s2 $18 //
81: #define s3 $19 //
82: #define s4 $20 //
83: #define s5 $21 //
84: #define s6 $22 //
85: #define s7 $23 //
86: #define t8 $24 // caller saved registers
87: #define t9 $25 //
88: #define k0 $26 // kernel reserved registers
89: #define k1 $27 //
90: #define gp $28 // global pointer
91: #define sp $29 // stack pointer
92: #define s8 $30 // callee saved register
93: #define ra $31 // return address register
94:
95: //
96: // Define standard floating point registers.
97: //
98:
99: #define f0 $f0 // caller saved registers
100: #define f1 $f1 //
101: #define f2 $f2 //
102: #define f3 $f3 //
103: #define f4 $f4 //
104: #define f5 $f5 //
105: #define f6 $f6 //
106: #define f7 $f7 //
107: #define f8 $f8 //
108: #define f9 $f9 //
109: #define f10 $f10 //
110: #define f11 $f11 //
111: #define f12 $f12 //
112: #define f13 $f13 //
113: #define f14 $f14 //
114: #define f15 $f15 //
115: #define f16 $f16 //
116: #define f17 $f17 //
117: #define f18 $f18 //
118: #define f19 $f19 //
119: #define f20 $f20 // callee saved registers
120: #define f21 $f21 //
121: #define f22 $f22 //
122: #define f23 $f23 //
123: #define f24 $f24 //
124: #define f25 $f25 //
125: #define f26 $f26 //
126: #define f27 $f27 //
127: #define f28 $f28 //
128: #define f29 $f29 //
129: #define f30 $f30 //
130: #define f31 $f31 //
131:
132: //
133: // Define R3000 system coprocessor registers.
134: //
135:
136: #if defined(R3000)
137:
138: #define index $0 // TB index register
139: #define random $1 // TB random register
140: #define entrylo $2 // TB entry low register
141: #define context $4 // TB context register
142: #define badvaddr $8 // TB bad virtual address register
143: #define entryhi $10 // TB entry high register
144: #define psr $12 // processor status register
145: #define cause $13 // exception cause register
146: #define epc $14 // exception PC register
147: #define prid $15 // processor id register
148:
149: //
150: // Define R3000 system coprocessor register bit field offsets.
151: //
152:
153: #define INDEX_INDEX 0x8 // TLB specified index <13:8>
154: #define INDEX_PROBE 0x1f // TLB probe failure <31>
155:
156: #define RANDOM_INDEX 0x8 // TLB random index <13:8>
157:
158: #define ENTRYLO_G 0x8 // Global <8>
159: #define ENTRYLO_V 0x9 // Valid <9>
160: #define ENTRYLO_D 0xa // Dirty <10>
161: #define ENTRYLO_N 0xb // Nocache <11>
162: #define ENTRYLO_PFN 0xc // Page Frame <31:12>
163:
164: #define ENTRYHI_PID 0x6 // Process id <11:6>
165: #define ENTRYHI_VPN 0xc // Virtual page <31:12>
166:
167: #define PSR_IEC 0x0 // Current interrupt enable <0>
168: #define PSR_KUC 0x1 // Current kernel/user <1>
169: #define PSR_IEP 0x2 // Previous interrupt enable <2>
170: #define PSR_KUP 0x3 // Previous kernel/user <3>
171: #define PSR_PMODE PSR_KUP // Previous mode bit <3>
172: #define PSR_IEO 0x4 // Old interrupt enable <4>
173: #define PSR_KUO 0x5 // Old kernel/user <5>
174: #define PSR_INTMASK 0x8 // Interrupt mask <15:8>
175: #define PSR_ISC 0x10 // Isolate d-cache <16>
176: #define PSR_SWC 0x11 // Swap caches <17>
177: #define PSR_PZ 0x12 // Parity zero <18>
178: #define PSR_CM 0x13 // Cache miss <19>
179: #define PSR_PE 0x14 // Parity error <20>
180: #define PSR_TS 0x15 // TLB shutdown <21>
181: #define PSR_BEV 0x16 // Bootstrap exception vector <22>
182: #define PSR_CU0 0x1c // Coprocessor 0 enabled <28>
183: #define PSR_CU1 0x1d // Coprocessor 1 enabled <29>
184: #define PSR_CU2 0x1e // Coprocessor 2 enabled <30>
185: #define PSR_CU3 0x1f // Coprocessor 3 enabled <31>
186:
187: #endif
188:
189: //
190: // Define R4000 system coprocessor registers.
191: //
192:
193: #if defined(R4000)
194:
195: #define index $0 // TB index register
196: #define random $1 // TB random register
197: #define entrylo0 $2 // TB entry low 0 register
198: #define entrylo1 $3 // TB entry low 1 register
199: #define context $4 // TB context register
200: #define pagemask $5 // Page mask register
201: #define wired $6 // Wired TB entries register
202: #define badvaddr $8 // TB bad virtual address register
203: #define count $9 // Timer count register
204: #define entryhi $10 // TB entry high register
205: #define compare $11 // Timer compare register
206: #define psr $12 // Processor status register
207: #define cause $13 // Exception cause register
208: #define epc $14 // Exception PC register
209: #define prid $15 // Processor id register
210: #define config $16 // Configuration register
211: #define lladdr $17 // Load linked address register
212: #define watchlo $18 // Watch low address register
213: #define watchhi $19 // Watch high address register
214: #define ecc $26 // S-cache ECC and primary parity register
215: #define cacheerr $27 // Cache error and status register
216: #define taglo $28 // Cache tag low register
217: #define taghi $29 // Cache tag high register
218: #define errorepc $30 // Error exception PC register
219:
220: //
221: // Define R4000 system coprocessor register bit field offsets.
222: //
223:
224: #define INDEX_INDEX 0x0 // TLB specified index <5:0>
225: #define INDEX_PROBE 0x1f // TLB probe failure <31>
226:
227: #define RANDOM_INDEX 0x0 // TLB random index <5:0>
228:
229: #define ENTRYLO_G 0x0 // Global <0>
230: #define ENTRYLO_V 0x1 // Valid <1>
231: #define ENTRYLO_D 0x2 // Dirty <2>
232: #define ENTRYLO_C 0x3 // Cache control <5:3>
233: #define ENTRYLO_PFN 0x6 // Page Frame <29:6>
234:
235: #define PAGEMASK_PAGEMASK 0xd // Page mask <24:13>
236:
237: #define WIRED_NUMBER 0x0 // Wired entries <5:0>
238:
239: #define ENTRYHI_PID 0x0 // Process id <7:0>
240: #define ENTRYHI_VPN2 0xd // Virtual page <31:13>
241:
242: #define PID_MASK 0xfff // allow for ample expansion
243:
244: #define PSR_IE 0x0 // Interrupt enable <0>
245: #define PSR_EXL 0x1 // Exception level <1>
246: #define PSR_ERL 0x2 // Error level <2>
247: #define PSR_KSU 0x3 // Kernel/supervisor/user <4:3>
248: #define PSR_PMODE (PSR_KSU + 1) // Previous mode bit <4>
249: #define PSR_UX 0x5 // User extended <5>
250: #define PSR_SX 0x6 // Supervior extended <6>
251: #define PSR_KX 0x7 // Kernel extended <7>
252: #define PSR_INTMASK 0x8 // Interrupt mask <15:8>
253: #define PSR_DE 0x10 // Disable cache parity and ECC <16>
254: #define PSR_CE 0x11 // Check enable <17>
255: #define PSR_CH 0x12 // Cache hit <18>
256: #define PSR_SR 0x14 // Soft reset <20>
257: #define PSR_TS 0x15 // TLB shutdown <21>
258: #define PSR_BEV 0x16 // Bootstrap exception vector <22>
259: #define PSR_CU0 0x1c // Coprocessor 0 enabled <28>
260: #define PSR_CU1 0x1d // Coprocessor 1 enabled <29>
261: #define PSR_CU2 0x1e // Coprocessor 2 enabled <30>
262: #define PSR_CU3 0x1f // Coprocessor 3 enabled <31>
263:
264: #define CONFIG_K0 0x0 // Kseg0 cache algorithm <2:0>
265: #define CONFIG_CU 0x3 // Update on store conditional <3>
266: #define CONFIG_DB 0x4 // Data cache block size <4>
267: #define CONFIG_IB 0x5 // Instruction cache block size <5>
268: #define CONFIG_DC 0x6 // Data cache size <8:6>
269: #define CONFIG_IC 0x9 // Instruction cache size <11:9>
270: #define CONFIG_EB 0xd // Block ordering <13>
271: #define CONFIG_EM 0xe // ECC mode enable <14>
272: #define CONFIG_BE 0xf // Big endian memory <15>
273: #define CONFIG_SM 0x10 // Use dirty shared state <16>
274: #define CONFIG_SC 0x11 // Secondary cache present <17>
275: #define CONFIG_EW 0x12 // System address port width <19:18>
276: #define CONFIG_SW 0x14 // Secondary cache port width <20>
277: #define CONFIG_SS 0x15 // Split secondary cache mode <21>
278: #define CONFIG_SB 0x16 // Secondary cache block size <23:22>
279: #define CONFIG_EP 0x18 // Pattern for write back data <27:24>
280: #define CONFIG_EC 0x1c // System address port clock ratio <30:28>
281: #define CONFIG_CM 0x1f // Master checker mode <31>
282:
283: #define ECC_ECC 0x0 // Secondary cache ECC <7:0>
284:
285: #define CACHEERR_PIDX 0x0 // Primary cache index <2:0>
286: #define CACHEERR_SIDX 0x3 // Secondary cache index <21:3>
287: #define CACHEERR_EI 0x18 // ECC error on pimary store miss <24>
288: #define CACHEERR_EB 0x19 // Data error on instrruction error <25>
289: #define CACHEERR_EE 0x1a // Error on system address bus <26>
290: #define CACHEERR_ES 0x1b // Error accessing processor state <27>
291: #define CACHEERR_ET 0x1c // Error on tag field <28>
292: #define CACHEERR_ED 0x1d // Error on data field <29>
293: #define CACHEERR_EC 0x1e // Cache level of error <30>
294: #define CACHEERR_ER 0x1f // Type of reference <31>
295:
296: #define TAGLO_P 0x0 // primary tag even parity <0>
297: #define TAGLO_PSTATE 0x6 // primary cache state <7:6>
298: #define TAGLO_PTAGLO 0x8 // primary tag low physical address <31:8>
299:
300: #endif
301:
302: //
303: // Define R3000 and R4000 cause register bit offsets.
304: //
305:
306: #define CAUSE_XCODE 0x2 // Exception code <6:2>
307: #define CAUSE_INTPEND 0x8 // Interrupt pending <15:8>
308: #define CAUSE_CE 0x1c // Coprocessor unusable <29:28>
309: #define CAUSE_BD 0x1f // Branch delay slot <31>
310:
311: //
312: // Define R3000 and R4000 processor id register field offsets.
313: //
314:
315: #define PRID_REV 0x0 // Revision level <7:0>
316: #define PRID_IMP 0x8 // Implementation type <15:8>
317:
318: //
319: // Define R3000 and R4000 exception codes.
320: //
321:
322: #define XCODE_INTERRUPT 0x0 // Interrupt
323: #define XCODE_MODIFY 0x4 // TLB modify
324: #define XCODE_READ_MISS 0x8 // TLB read miss
325: #define XCODE_WRITE_MISS 0xc // TLB write miss
326: #define XCODE_READ_ADDRESS_ERROR 0x10 // Read alignment error
327: #define XCODE_WRITE_ADDRESS_ERROR 0x14 // Write alignment error
328: #define XCODE_INSTRUCTION_BUS_ERROR 0x18 // Instruction bus error
329: #define XCODE_DATA_BUS_ERROR 0x1c // Data bus error
330: #define XCODE_SYSTEM_CALL 0x20 // System call
331: #define XCODE_BREAKPOINT 0x24 // Breakpoint
332: #define XCODE_ILLEGAL_INSTRUCTION 0x28 // Illegal instruction
333: #define XCODE_COPROCESSOR_UNUSABLE 0x2c // Coprocessor unusable
334: #define XCODE_INTEGER_OVERFLOW 0x30 // Arithmetic overflow
335:
336: #if defined(R3000)
337:
338: #define XCODE_PANIC 0x3c // Stack overflow (software)
339:
340: #define R3000_XCODE_MASK (0xf << CAUSE_XCODE) // R3000 exception code mask
341:
342: #define R3000_MISS_MASK (R3000_XCODE_MASK & \
343: (~(XCODE_READ_MISS ^ XCODE_WRITE_MISS))) //
344:
345: #endif
346:
347: #if defined(R4000)
348:
349: #define XCODE_TRAP 0x34 // Trap instruction
350: #define XCODE_VIRTUAL_INSTRUCTION 0x38 // Virtual instruction coherency
351: #define XCODE_FLOATING_EXCEPTION 0x3c // Floating point exception
352: #define XCODE_WATCHPOINT 0x5c // Watch point
353: #define XCODE_PANIC 0x78 // Stack overflow (software)
354: #define XCODE_VIRTUAL_DATA 0x7c // Virtual data coherency
355:
356: #define R4000_XCODE_MASK (0x1f << CAUSE_XCODE) // R4000 exception code mask
357:
358: #define R4000_MISS_MASK (R4000_XCODE_MASK & \
359: (~(XCODE_READ_MISS ^ XCODE_WRITE_MISS))) //
360:
361: #endif
362:
363: //
364: // Define R4000 page mask values.
365: //
366:
367: #if defined(R4000)
368:
369: #define PAGEMASK_4KB 0x0 // 4kb page
370: #define PAGEMASK_16KB 0x3 // 16kb page
371: #define PAGEMASK_64KB 0xf // 64kb page
372: #define PAGEMASK_256KB 0x3f // 256kb page
373: #define PAGEMASK_1MB 0xff // 1mb page
374: #define PAGEMASK_4MB 0x3ff // 4mb page
375: #define PAGEMASK_16MB 0xfff // 16mb page
376:
377: #endif
378:
379: //
380: // Define R4000 primary cache states.
381: //
382:
383: #if defined(R4000)
384:
385: #define PRIMARY_CACHE_INVALID 0x0 // primary cache invalid
386: #define PRIMARY_CACHE_SHARED 0x1 // primary cache shared (clean or dirty)
387: #define PRIMARY_CACHE_CLEAN_EXCLUSIVE 0x2 // primary cache clean exclusive
388: #define PRIMARY_CACHE_DIRTY_EXCLUSIVE 0x3 // primary cache dirty exclusive
389:
390: #endif
391:
392: //
393: // Define R4000 cache instruction operation codes.
394: //
395:
396: #if defined(R4000)
397:
398: #define INDEX_INVALIDATE_I 0x0 // invalidate primary instruction cache
399: #define INDEX_WRITEBACK_INVALIDATE_D 0x1 // writeback/invalidate primary data cache
400: #define INDEX_INVALIDATE_SI 0x2 // invalidate secondary instruction cache
401: #define INDEX_WRITEBACK_INVALIDATE_SD 0x3 // writeback/invalidate secondary data cache
402:
403: #define INDEX_LOAD_TAG_I 0x4 // load primary instruction tag indexed
404: #define INDEX_LOAD_TAG_D 0x5 // load primary data tag indexed
405: #define INDEX_LOAD_TAG_SI 0x6 // load secondary instruction tag indexed
406: #define INDEX_LOAD_TAG_SD 0x7 // load secondary data tag indexed
407:
408: #define INDEX_STORE_TAG_I 0x8 // store primary instruction tag indexed
409: #define INDEX_STORE_TAG_D 0x9 // store primary data tag indexed
410: #define INDEX_STORE_TAG_SI 0xa // store secondary instruction tag indexed
411: #define INDEX_STORE_TAG_SD 0xb // store secondary data tag indexed
412:
413: #define CREATE_DIRTY_EXCLUSIVE_D 0xd // create dirty exclusive primary data cache
414: #define CREATE_DIRTY_EXCLUSIVE_SD 0xf // create dirty exclusive secondary data cache
415:
416: #define HIT_INVALIDATE_I 0x10 // invalidate primary instruction cache
417: #define HIT_INVALIDATE_D 0x11 // invalidate primary data cache
418: #define HIT_INVALIDATE_SI 0x12 // invalidate secondary instruction cache
419: #define HIT_INVALIDATE_SD 0x13 // invalidate secondary data cache
420:
421: #define HIT_WRITEBACK_INVALIDATE_D 0x15 // writeback/invalidate primary data cache
422: #define HIT_WRITEBACK_INVALIDATE_SD 0x17 // writeback/invalidate secondary data cache
423:
424: #define HIT_WRITEBACK_D 0x19 // writeback primary data cache
425: #define HIT_WRITEBACK_SD 0x1b // writeback secondary data cache
426:
427: #define HIT_SET_VIRTUAL_SI 0x1e // hit set virtual secondary instruction cache
428: #define HIT_SET_VIRTUAL_SD 0x1f // hit set virtual secondary data cache
429:
430: #endif
431:
432: //
433: // Define enable and disable interrupt macros.
434: //
435:
436: #if defined(R3000)
437:
438: #define DISABLE_INTERRUPTS(reg) \
439: .set noreorder; \
440: .set noat; \
441: li AT,1 << PSR_CU1; \
442: mfc0 reg,psr; \
443: mtc0 AT,psr; \
444: nop; \
445: .set at; \
446: .set reorder;
447:
448: #define ENABLE_INTERRUPTS(reg) \
449: .set noreorder; \
450: .set noat; \
451: mtc0 reg,psr; \
452: nop; \
453: .set at; \
454: .set reorder;
455:
456: #endif
457:
458: #if defined(R4000)
459:
460: #define DISABLE_INTERRUPTS(reg) \
461: .set noreorder; \
462: .set noat; \
463: li AT,1 << PSR_CU1; \
464: mfc0 reg,psr; \
465: mtc0 AT,psr; \
466: nop; \
467: nop; \
468: .set at; \
469: .set reorder;
470:
471: #define ENABLE_INTERRUPTS(reg) \
472: .set noreorder; \
473: .set noat; \
474: mtc0 reg,psr; \
475: nop; \
476: nop; \
477: .set at; \
478: .set reorder;
479:
480: #endif
481:
482: //
483: // Define floating coprocessor registers
484: //
485:
486: #define fsrid $0 // floating identification register
487: #define fsr $31 // floating status register
488:
489: //
490: // Define floating status register bit offsets.
491: //
492:
493: #define FSR_RM 0x0
494: #define FSR_SI 0x2
495: #define FSR_SU 0x3
496: #define FSR_SO 0x4
497: #define FSR_SZ 0x5
498: #define FSR_SV 0x6
499: #define FSR_EI 0x7
500: #define FSR_EU 0x8
501: #define FSR_EO 0x9
502: #define FSR_EZ 0xa
503: #define FSR_EV 0xb
504: #define FSR_XI 0xc
505: #define FSR_XU 0xd
506: #define FSR_XO 0xe
507: #define FSR_XZ 0xf
508: #define FSR_XV 0x10
509: #define FSR_XE 0x11
510: #define FSR_CC 0x17
511: #define FSR_FS 0x18
512:
513: //
514: // Define save and restore floating state macros.
515: //
516:
517: #if defined(R3000)
518:
519: #define RESTORE_VOLATILE_FLOAT_STATE \
520: lwc1 f0,TrFltF0(s8); \
521: jal KiRestoreVolatileFloatState;
522:
523: #define SAVE_VOLATILE_FLOAT_STATE \
524: swc1 f0,TrFltF0(s8); \
525: jal KiSaveVolatileFloatState;
526:
527: #endif
528:
529: #if defined(R4000)
530:
531: #define RESTORE_VOLATILE_FLOAT_STATE \
532: ldc1 f0,TrFltF0(s8); \
533: jal KiRestoreVolatileFloatState;
534:
535: #define SAVE_VOLATILE_FLOAT_STATE \
536: sdc1 f0,TrFltF0(s8); \
537: jal KiSaveVolatileFloatState;
538:
539: #endif
540:
541: #if defined(R3000)
542:
543: #define RESTORE_NONVOLATILE_FLOAT_STATE \
544: lwc1 f20,ExFltF20(sp); \
545: jal KiRestoreNonvolatileFloatState;
546:
547: #define SAVE_NONVOLATILE_FLOAT_STATE \
548: swc1 f20,ExFltF20(sp); \
549: jal KiSaveNonvolatileFloatState;
550:
551: #endif
552:
553: #if defined(R4000)
554:
555: #define RESTORE_NONVOLATILE_FLOAT_STATE \
556: ldc1 f20,ExFltF20(sp); \
557: jal KiRestoreNonvolatileFloatState;
558:
559: #define SAVE_NONVOLATILE_FLOAT_STATE \
560: sdc1 f20,ExFltF20(sp); \
561: jal KiSaveNonvolatileFloatState;
562:
563: #endif
564:
565: //
566: // Define TB and cache parameters.
567: //
568:
569: #if defined(R3000)
570:
571: #define NUMBER_PIDS 64 // number of process ids
572:
573: #define PCR_ENTRY 0 // TB entry numbers (2) for the PCR
574: #define PDR_ENTRY 2 // TB entry number (1) for the PDR
575: #define KSTACK_ENTRY 3 // TB entry numbers (2) for kernel stack
576: #define KDPORT_ENTRY 5 // TB entry number (1) for debug port
577: #define DMA_ENTRY 6 // TB entry number (1) for DMA registers
578: #define INTERRUPT_ENTRY 7 // TB entry number (1) for interrupt source
579:
580: #define TB_SIZE 64 // number of TB entries
581: #define TB_ENTRY_SIZE (2 * 4) // size of TB entry
582: #define FIXED_BASE 0 // base index of fixed TB entries
583: #define FIXED_ENTRIES (INTERRUPT_ENTRY + 1) // number of fixed TB entries
584: #define RANDOM_BASE FIXED_ENTRIES // base index of random TB entries
585: #define RANDOM_ENTRIES (TB_SIZE - RANDOM_BASE) // number of random TB entries
586:
587: #endif
588:
589: #if defined(R4000)
590:
591: #define PCR_ENTRY 0 // TB entry numbers (2) for the PCR
592: #define PDR_ENTRY 2 // TB entry number (1) for the PDR
593: #define KSTACK_ENTRY 3 // TB entry numbers (1) for kernel stack
594: #define DMA_ENTRY 4 // TB entry number (1) for DMA/InterruptSource
595:
596: #define TB_ENTRY_SIZE (3 * 4) // size of TB entry
597: #define FIXED_BASE 0 // base index of fixed TB entries
598: #define FIXED_ENTRIES (DMA_ENTRY + 1) // number of fixed TB entries
599:
600: #endif
601:
602: //
603: // Define cache parameters
604: //
605:
606: #define DCACHE_SIZE 4 * 1024 // size of data cache in bytes
607: #define ICACHE_SIZE 4 * 1024 // size of instruction cache in bytes
608: #define MINIMUM_CACHE_SIZE 4 * 1024 // minimum size of cache
609: #define MAXIMUM_CACHE_SIZE 128 * 1024 // maximum size fo cache
610:
611: //
612: // Define subtitle macro
613: //
614:
615: #define SBTTL(x)
616:
617: //
618: // Define global definition macros.
619: //
620:
621: #define END_REGION(Name) \
622: .globl Name; \
623: Name:;
624:
625: #define START_REGION(Name) \
626: .globl Name; \
627: Name:;
628:
629: //
630: // Define trap frame generation macro.
631: //
632:
633: #define GENERATE_TRAP_FRAME \
634: .set noat; \
635: sw AT,TrIntAt(s8); \
636: jal KiGenerateTrapFrame; \
637: .set at;
638:
639: //
640: // Define restore volatile integer state macro.
641: //
642:
643: #define RESTORE_VOLATILE_INTEGER_STATE \
644: .set noat; \
645: lw AT,TrIntAt(s8); \
646: jal KiRestoreVolatileIntegerState; \
647: .set at;
648:
649: //
650: // Define save volatile integer state macro.
651: //
652:
653: #define SAVE_VOLATILE_INTEGER_STATE \
654: .set noat; \
655: sw AT,TrIntAt(s8); \
656: jal KiSaveVolatileIntegerState; \
657: .set at;
658:
659: //
660: // Define procedure entry macros
661: //
662:
663: #define ALTERNATE_ENTRY(Name) \
664: .globl Name; \
665: Name:;
666:
667: #define LEAF_ENTRY(Name) \
668: .text; \
669: .align 4; \
670: .globl Name; \
671: .ent Name, 0; \
672: Name:; \
673: .frame sp, 0, ra; \
674: .prologue 0;
675:
676: #define NESTED_ENTRY(Name, fsize, retrg) \
677: .text; \
678: .align 4; \
679: .globl Name; \
680: .ent Name, 0; \
681: Name:; \
682: .frame sp, fsize, retrg;
683:
684: //
685: // Define exception handling macros.
686: //
687:
688: #define EXCEPTION_HANDLER(Handler) \
689: .edata 1, Handler;
690:
691: #define PROLOGUE_END .prologue 1;
692:
693: //
694: // Define exception data section and align.
695: //
696:
697: #ifndef HEADER_FILE
698:
699: .edata 0
700: .align 2
701: .text
702:
703: #endif
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