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nono 0.6.0
;
; nono
; Copyright (C) 2022 nono project
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
; RTL8019AS の DMA 転送の挙動を調べる。
; DCR.WTS (転送サイズ) と実際の DMA ポートのアクセス幅が異なる場合や
; RSAR が奇数アドレスから始まる場合にどうなるかとか。
; PROM 領域と RAM 領域ではサイズによる挙動が違うのでそれぞれ調べる。
; ただしその境界 ($3fff-$4001) で奇数だったら、については調べてない。
;
; WTS はアクセス後の、アドレスのインクリメントと残り転送バイト数の
; デクリメントを1回やるか2回やるかの切り替えのようだ。
; ここには書いてないが、ワード転送で RBCR=7 (奇数) にしても 8バイト
; (4ワード) 読み込める。
;
; これ実行後はネットワークが使えなくなるので Human68k を再起動すること。
.include doscall.mac
.include iocscall.mac
.xref hexstr_word
.xref hexstr_byte
RTL_BASE .equ 0xece300
CR .equ 0x00
RSAR0 .equ 0x10
RSAR1 .equ 0x12
RBCR0 .equ 0x14
RBCR1 .equ 0x16
DCR .equ 0x1c
DMA .equ 0x20
CR_RD .equ 0x09
CR_WR .equ 0x11
DCR_B .equ 0x08
DCR_W .equ 0x09
DMA_B .equ 0
DMA_W .equ 1
PRINT .macro str
pea str
DOS _PRINT
addq.l #4,sp
.endm
.cpu 68030
.list
.text
.even
start:
clr.l -(sp)
DOS _SUPER
addq.l #4,sp
clr.l a4
lea.l RTL_BASE(a4),a4
bsr read_macaddr
lea.l testdata(pc),a2
mainloop:
move.w (a2)+,d3 ; d3: start addr
bmi done ; If addr < 0, goto done.
lea.l dmabuf(pc),a0 ; Clear dmabuf
moveq.l #0,d0
move.l d0,(a0)+
move.l d0,(a0)+
move.l d0,(a0)+
move.l d0,(a0)+
lea.l buf(pc),a0 ; Display test parameters
move.w d3,d0
swap d0
bsr hexstr_word
move.b #'/',(a0)+
move.w (a2)+,d2 ; d2: DCR
move.w d2,d0
ror.l #8,d0
bsr hexstr_byte
move.b #'/',(a0)+
move.l #(('D'<<24)|('M'<<16)|('A'<<8)|'_'),(a0)+
move.w (a2)+,d1 ; d1: DMASizeIndex
bne @f
move.b #'B',(a0)+
bra @@f
@@:
move.b #'W',(a0)+
@@:
clr.b (a0)
PRINT buf(pc)
move.w d3,d0
lsr.w #8,d0 ; if (start_addr >> 8 == 00)
beq @f ; src is PROM, skip init_ram.
bsr init_ram
@@:
lea.l dmabuf(pc),a0
move.b d3,RSAR0(a4) ; Set registers
move.b d0,RSAR1(a4)
move.b #$10,RBCR0(a4)
move.b #$00,RBCR1(a4)
move.b d2,DCR(a4)
move.b #CR_RD,CR(a4) ; Issue Read command
tst.b d1 ; DMASizeIndex
bne dma_word
dma_byte:
moveq.l #$10-1,d3
@@:
move.b DMA(a4),(a0)+
dbra d3,@b
bra verify
dma_word:
moveq.l #8-1,d3
@@:
move.w DMA(a4),(a0)+
dbra d3,@b
verify:
lea.l expected(pc),a1
bsr read_expected
lea.l dmabuf(pc),a0
moveq.l #16-1,d3
verify_byte:
move.b (a1)+,d0
cmpi.b #$fe,d0 ; If expected==$fe, no check this byte
beq @f
cmp.b (a0),d0
bne fail
@@:
adda.l #1,a0
dbra d3,verify_byte
; success
PRINT msg_ok(pc)
bra mainloop
fail:
; At this point, a2 points begin of next testdata.
PRINT msg_fail(pc)
lea.l buf(pc),a0
lea.l expected(pc),a1
moveq.l #16-1,d3
@@:
move.b (a1)+,d0
ror.l #8,d0
bsr hexstr_byte
dbra d3,@b
clr.b (a0)
PRINT buf(pc)
PRINT msg_actual
lea.l buf(pc),a0
lea.l dmabuf(pc),a1
moveq.l #16-1,d3
@@:
move.b (a1)+,d0
ror.l #8,d0
bsr hexstr_byte
dbra d3,@b
clr.b (a0)
PRINT buf(pc)
PRINT msg_crlf
bra mainloop
done:
DOS _EXIT
read_macaddr:
; Read MAC addr using correct way.
moveq.l #0,d0
move.b d0,RSAR0(a4)
move.b d0,RSAR1(a4)
move.b #12,RBCR0(a4)
move.b d0,RBCR1(a4)
move.b #DCR_W,DCR(a4)
move.b #CR_RD,CR(a4)
moveq.l #6-1,d3
lea.l macaddr(pc),a0
@@:
move.w DMA(a4),d0
ror.w #8,d0
move.b d0,(a0)+
dbra d3,@b
rts
init_ram:
movem.l d0/d3,-(sp)
move.b #$00,RSAR0(a4)
move.b #$40,RSAR1(a4)
move.b #$20,RBCR0(a4)
move.b #$00,RBCR1(a4)
move.b #DCR_W,DCR(a4)
move.b #CR_WR,CR(a4)
move.w #$1011,d0
moveq.l #16-1,d3
@@:
move.w d0,DMA(a4)
addi.w #$0202,d0
dbra d3,@b
movem.l (sp)+,d0/d3
rts
; IN a1: destination buffer (expected), don't change a1
; a2: source buffer, don't save a2
read_expected:
movem.l d0/d3/a0-a1/a3,-(sp)
lea.l macaddr(pc),a3
moveq.l #0,d0
moveq.l #16-1,d3
@@:
move.b (a2)+,d0
cmpi.w #$fe,d0
bge @f
cmpi.w #$f0,d0
blt @f
; If $f0 <= d0 < $fe, replace them to mac addr
subi.b #$f0,d0
;move.b 0(a3,d0.b*1),d0
movea.l a3,a0
add.l d0,a0
move.b (a0),d0
@@:
move.b d0,(a1)+
dbra d3,@@b
movem.l (sp)+,d0/d3/a0-a1/a3
rts
testdata:
; RSAR DCR DMA Expected($f0-$f5: MACaddr, $fe: ignore)
.dc.w $0000, DCR_W, DMA_W, $f0ff,$f1ff,$f2ff,$f3ff, $f4ff,$f5ff,$ffff,$ffff
.dc.w $0001, DCR_W, DMA_W, $f0ff,$f1ff,$f2ff,$f3ff, $f4ff,$f5ff,$ffff,$ffff
.dc.w $4000, DCR_W, DMA_W, $1011,$1213,$1415,$1617, $1819,$1a1b,$1c1d,$1e1f
.dc.w $4001, DCR_W, DMA_W, $1011,$1213,$1415,$1617, $1819,$1a1b,$1c1d,$1e1f
.dc.w $0000, DCR_B, DMA_W, $f0ff,$f0ff,$f1ff,$f1ff, $f2ff,$f2ff,$f3ff,$f3ff
.dc.w $0001, DCR_B, DMA_W, $f0ff,$f1ff,$f1ff,$f2ff, $f2ff,$f3ff,$f3ff,$f4ff
.dc.w $4000, DCR_B, DMA_W, $1011,$fefe,$1213,$fefe, $1415,$fefe,$1617,$fefe
.dc.w $4001, DCR_B, DMA_W, $fefe,$1213,$fefe,$1415, $fefe,$1617,$fefe,$1819
; XXX +7バイト目から不定($22 が読める)になるのが謎
.dc.w $0000, DCR_W, DMA_B, $f0f1,$f2f3,$f4f5,$fffe, $fefe,$fefe,$fefe,$fefe
.dc.w $0001, DCR_W, DMA_B, $f0f1,$f2f3,$f4f5,$ffff, $fefe,$fefe,$fefe,$fefe
.dc.w $4000, DCR_W, DMA_B, $1012,$1416,$181a,$1c1e, $2020,$2020,$2020,$2020
.dc.w $4001, DCR_W, DMA_B, $1012,$1416,$181a,$1c1e, $2020,$2020,$2020,$2020
.dc.w $0000, DCR_B, DMA_B, $f0f0,$f1f1,$f2f2,$f3f3, $f4f4,$f5f5,$ffff,$ffff
.dc.w $0001, DCR_B, DMA_B, $f0f1,$f1f2,$f2f3,$f3f4, $f4f5,$f5ff,$ffff,$ffff
.dc.w $4000, DCR_B, DMA_B, $10fe,$12fe,$14fe,$16fe, $18fe,$1afe,$1cfe,$1efe
.dc.w $4001, DCR_B, DMA_B, $fe12,$fe14,$fe16,$fe18, $fe1a,$fe1c,$fe1e,$fe20
.dc.w $ffff ; Sentinel
msg_fail: .dc.b " failed",$d,$a
.dc.b " Expected ",0
msg_actual: .dc.b $d,$a," Actual ",0
msg_ok: .dc.b " OK",$d,$a,0
msg_crlf: .dc.b $d,$a,0
.even
macaddr: .ds.b 6
.align 4
expected: .ds.b 16
dmabuf: .ds.b 32
buf: .ds.b 64
.end
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.