--- nono/hd64180/hd64180ops.cpp 2026/04/29 17:05:18 1.1 +++ nono/hd64180/hd64180ops.cpp 2026/04/29 17:05:34 1.1.1.4 @@ -2,58 +2,47 @@ #define ACC (*(hd64180acc*)®.f) -// LDIR, INDR 等のリピート系命令の雛形。 +// LDIR, LDDR のリピート系命令の雛形。 // いずれも OP(name) を実行して BC == 0 になるまでこの PC を繰り返すもの。 // ジャンプする際には 2クロック追加で消費する。 // フラグも OP(name) が変更した以上にはここでは変更しない。 -#define REPEAT_UNTIL(name) do { \ +#define REPEAT_LD(name) do { \ OP_FUNC(name); \ - if (reg.GetBC() != 0) { \ + if (reg.f.IsV()) { \ reg.pc -= 2; \ CYCLE(2); \ } \ } while (0) -uint32 -MPU64180Device::Read16(uint32 addr) -{ - uint32 data; - - data = Read8(addr); - data |= Read8(addr + 1) << 8; - - return data; -} - -void -MPU64180Device::Write16(uint32 addr, uint32 data) -{ - Write8(addr, data & 0xff); - Write8(addr + 1, data >> 8); -} - -uint32 -MPU64180Device::Fetch16() -{ - uint32 data; - - data = Fetch8(); - data |= Fetch8() << 8; +// INIR, INDR, OTIR, OTDR 用。 +#define REPEAT_IO(name) do { \ + OP_FUNC(name); \ + if (reg.f.IsZ() == false) { \ + reg.pc -= 2; \ + CYCLE(2); \ + } \ +} while (0) - return data; -} +// CPIR, CPDR 用。 +#define REPEAT_CP(name) do { \ + OP_FUNC(name); \ + if (reg.f.IsZ() == false && reg.f.IsV()) { \ + reg.pc -= 2; \ + CYCLE(2); \ + } \ +} while (0) void -MPU64180Device::Push16(uint32 data) +MPU64180Device::Push2(uint32 data) { reg.sp -= 2; - Write16(reg.sp, data); + Write2(reg.sp, data); } uint32 -MPU64180Device::Pop16() +MPU64180Device::Pop2() { - uint16 data = Read16(reg.sp); + uint16 data = Read2(reg.sp); reg.sp += 2; return data; } @@ -67,7 +56,7 @@ MPU64180Device::GetIHL() const case USE_IX: return reg.ix; break; case USE_IY: return reg.iy; break; default: - PANIC("invalid ixiy = %d", (int)ixiy); + PANIC("invalid ixiy = %u", (uint)ixiy); } } @@ -80,7 +69,7 @@ MPU64180Device::SetIHL(uint32 data) case USE_IX: reg.ix = data; break; case USE_IY: reg.iy = data; break; default: - PANIC("invalid ixiy = %d", (int)ixiy); + PANIC("invalid ixiy = %u", (uint)ixiy); } } @@ -93,7 +82,7 @@ MPU64180Device::LeaIHL() if (ixiy != USE_HL) { // DD と DD CB で +d をフェッチする順序が違う。 if ((int32)ixd < 0) { - ixd = Fetch8(); + ixd = Fetch1(); } addr += (int32)(int8)ixd; } @@ -133,33 +122,33 @@ MPU64180Device::SetWW(uint ww, uint32 da // ここから命令 -// 00000000: NOP +// 00000000: 01R: NOP OP_DEF(nop) { CYCLE(3); } -// 00ww0001: LD ww,nn -// DD:00100001: LD IX,nn +// 00ww0001: 01R: LD ww,nn +// DD:00100001: 01R: LD IX,nn OP_DEF(ld_ww_nn) { - uint32 nn = Fetch16(); + uint32 nn = Fetch2(); uint ww = (op >> 4) & 3; SetWW(ww, nn); CYCLE_IX(9, 12); } -// 00ww0010: LD (ww),A +// 00ww0010: 01R: LD (ww),A OP_DEF(ld_wwin_a) { uint ww = op >> 4; uint32 addr = GetWW(ww); // ww は BC, DE のみ - Write8(addr, reg.a); + Write1(addr, reg.a); CYCLE_IX(7, 15); } -// 00ww0011: INC ww -// DD:00100011: INC IX +// 00ww0011: 01R: INC ww +// DD:00100011: 01R: INC IX OP_DEF(inc_ww) { uint ww = op >> 4; @@ -169,7 +158,7 @@ OP_DEF(inc_ww) CYCLE_IX(4, 7); } -// 00rrr100: INC r +// 00rrr100: 01R: INC r OP_DEF(inc_r) { uint r = op >> 3; @@ -177,7 +166,7 @@ OP_DEF(inc_r) CYCLE(4); } -// 00rrr101: DEC r +// 00rrr101: 01R: DEC r OP_DEF(dec_r) { uint r = op >> 3; @@ -185,22 +174,22 @@ OP_DEF(dec_r) CYCLE(4); } -// 00rrr110: LD r,n +// 00rrr110: 01R: LD r,n OP_DEF(ld_r_n) { uint r = op >> 3; - reg.r[r] = Fetch8(); + reg.r[r] = Fetch1(); CYCLE(6); } -// 00000111: RLCA +// 00000111: 01R: RLCA OP_DEF(rlca) { reg.a = ACC.rlc_8(reg.a); CYCLE(3); } -// 00001000: EX AF,AF' +// 00001000: 01R: EX AF,AF' OP_DEF(ex_af_af) { uint8 tmpa = reg.a; @@ -212,8 +201,8 @@ OP_DEF(ex_af_af) CYCLE(4); } -// 00ww1001: ADD HL,ww -// DD:00ww1001: ADD IX,ww +// 00ww1001: 01R: ADD HL,ww +// DD:00ww1001: 01R: ADD IX,ww OP_DEF(add_hl_ww) { uint ww = op >> 4; @@ -224,17 +213,17 @@ OP_DEF(add_hl_ww) CYCLE_IX(7, 10); } -// 00ww1010: LD A,(ww) +// 00ww1010: 01R: LD A,(ww) OP_DEF(ld_a_wwin) { uint ww = op >> 4; uint32 addr = GetWW(ww); // ww は BC, DE のみ - reg.a = Read8(addr); + reg.a = Read1(addr); CYCLE(6); } -// 00ww1011: DEC ww -// DD:00101011: DEC IX +// 00ww1011: 01R: DEC ww +// DD:00101011: 01R: DEC IX OP_DEF(dec_ww) { uint ww = op >> 4; @@ -244,17 +233,17 @@ OP_DEF(dec_ww) CYCLE_IX(4, 7); } -// 00001111: RRCA +// 00001111: 01R: RRCA OP_DEF(rrca) { reg.a = ACC.rrc_8(reg.a); CYCLE(3); } -// 00010000: DJNZ n +// 00010000: 01R: DJNZ n OP_DEF(djnz) { - int8 n = Fetch8(); + int8 n = Fetch1(); reg.b--; if (reg.b != 0) { Jump(reg.pc + n); @@ -264,32 +253,32 @@ OP_DEF(djnz) } } -// 00010111: RLA +// 00010111: 01R: RLA OP_DEF(rla) { reg.a = ACC.rl_8(reg.a); CYCLE(3); } -// 00011000: JR n +// 00011000: 01R: JR n OP_DEF(jr) { - int8 n = Fetch8(); + int8 n = Fetch1(); Jump(reg.pc + n); CYCLE(8); } -// 00011111: RRA +// 00011111: 01R: RRA OP_DEF(rra) { reg.a = ACC.rr_8(reg.a); CYCLE(3); } -// 00100000: JR NZ,n +// 00100000: 01R: JR NZ,n OP_DEF(jr_nz) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsZ() == false) { Jump(reg.pc + n); CYCLE(8); @@ -298,27 +287,26 @@ OP_DEF(jr_nz) } } -// 00100010: LD (nn),HL -// DD:00100010: LD (nn),IX +// 00100010: 01R: LD (nn),HL +// DD:00100010: 01R: LD (nn),IX OP_DEF(ld_nnin_hl) { - uint32 nn = Fetch16(); - Write16(nn, GetIHL()); + uint32 nn = Fetch2(); + Write2(nn, GetIHL()); CYCLE_IX(16, 19); } -// 00100111: DAA +// 00100111: 01R: DAA OP_DEF(daa) { - // XXX 未実装 - putlog(0, "DAA (NOT IMPLEMENTED)"); + reg.a = ACC.daa_8(reg.a); CYCLE(4); } -// 00101000: JR Z,n +// 00101000: 01R: JR Z,n OP_DEF(jr_z) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsZ()) { Jump(reg.pc + n); CYCLE(8); @@ -327,17 +315,17 @@ OP_DEF(jr_z) } } -// 00101010: LD HL,(nn) -// DD:00101010: LD IX,(nn) +// 00101010: 01R: LD HL,(nn) +// DD:00101010: 01R: LD IX,(nn) OP_DEF(ld_hl_nnin) { - uint32 nn = Fetch16(); - uint32 src = Read16(nn); + uint32 nn = Fetch2(); + uint32 src = Read2(nn); SetIHL(src); CYCLE_IX(15, 18); } -// 00101111: CPL +// 00101111: 01R: CPL OP_DEF(cpl) { reg.a = ~reg.a; @@ -346,10 +334,10 @@ OP_DEF(cpl) CYCLE(3); } -// 00110000: JR NC,n +// 00110000: 01R: JR NC,n OP_DEF(jr_nc) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsC() == false) { Jump(reg.pc + n); CYCLE(8); @@ -358,47 +346,47 @@ OP_DEF(jr_nc) } } -// 00110010: LD (nn),A +// 00110010: 01R: LD (nn),A OP_DEF(ld_nnin_a) { - uint32 addr = Fetch16(); - Write8(addr, reg.a); + uint32 addr = Fetch2(); + Write1(addr, reg.a); CYCLE(13); } -// 00110100: INC (HL) -// DD:00110100: INC (IX+d) +// 00110100: 01R: INC (HL) +// DD:00110100: 01R: INC (IX+d) OP_DEF(inc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 dst = ACC.inc_8(src); - Write8(addr, dst); + Write1(addr, dst); CYCLE_IX(10, 18); } -// 00110101: DEC (HL) -// DD:00110101: DEC (IX+d) +// 00110101: 01R: DEC (HL) +// DD:00110101: 01R: DEC (IX+d) OP_DEF(dec_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 dst = ACC.dec_8(src); - Write8(addr, dst); + Write1(addr, dst); CYCLE_IX(10, 18); } -// 00110110: LD (HL),n -// DD:00110110: LD (IX+d),n +// 00110110: 01R: LD (HL),n +// DD:00110110: 01R: LD (IX+d),n OP_DEF(ld_hlin_n) { uint32 addr = LeaIHL(); - uint32 src = Fetch8(); - Write8(addr, src); + uint32 src = Fetch1(); + Write1(addr, src); CYCLE_IX(9, 15); } -// 00110111: SCF +// 00110111: 01R: SCF OP_DEF(scf) { reg.f.SetC(true); @@ -407,10 +395,10 @@ OP_DEF(scf) CYCLE(3); } -// 00111000: JR C,n +// 00111000: 01R: JR C,n OP_DEF(jr_c) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsC()) { Jump(reg.pc + n); CYCLE(8); @@ -419,15 +407,15 @@ OP_DEF(jr_c) } } -// 00111010: LD A,(nn) +// 00111010: 01R: LD A,(nn) OP_DEF(ld_a_nnin) { - uint32 nn = Fetch16(); - reg.a = Read8(nn); + uint32 nn = Fetch2(); + reg.a = Read1(nn); CYCLE(12); } -// 00111111: CCF +// 00111111: 01R: CCF OP_DEF(ccf) { reg.f.SetC(!reg.f.IsC()); @@ -436,7 +424,7 @@ OP_DEF(ccf) CYCLE(3); } -// 01rrrsss: LD r,s +// 01rrrsss: 01R: LD r,s OP_DEF(ld_r_s) { uint d = (op >> 3) & 7; @@ -445,27 +433,27 @@ OP_DEF(ld_r_s) CYCLE(4); } -// 01rrr110: LD r,(HL) -// DD:01rrr110: LD r,(IX+d) +// 01rrr110: 01R: LD r,(HL) +// DD:01rrr110: 01R: LD r,(IX+d) OP_DEF(ld_r_hlin) { uint d = (op >> 3) & 7; uint16 addr = LeaIHL(); - reg.r[d] = Read8(addr); + reg.r[d] = Read1(addr); CYCLE_IX(6, 14); } -// 01110sss: LD (HL),s -// DD:01110sss: LD (IX+d),s +// 01110sss: 01R: LD (HL),s +// DD:01110sss: 01R: LD (IX+d),s OP_DEF(ld_hlin_s) { uint s = op & 7; uint32 addr = LeaIHL(); - Write8(addr, reg.r[s]); + Write1(addr, reg.r[s]); CYCLE_IX(7, 15); } -// 01110110: HALT +// 01110110: 01R: HALT OP_DEF(halt) { opmode = OpMode::Halt; @@ -473,7 +461,7 @@ OP_DEF(halt) CYCLE(3); } -// 10000rrr: ADD A,r +// 10000rrr: 01R: ADD A,r OP_DEF(add_a_r) { uint r = op & 7; @@ -481,17 +469,17 @@ OP_DEF(add_a_r) CYCLE(4); } -// 10000110: ADD A,(HL) -// DD:10000110: ADD A,(IX+d) +// 10000110: 01R: ADD A,(HL) +// DD:10000110: 01R: ADD A,(IX+d) OP_DEF(add_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.add_8(reg.a, src); CYCLE_IX(6, 14); } -// 10001rrr: ADC A,r +// 10001rrr: 01R: ADC A,r OP_DEF(adc_a_r) { uint r = op & 7; @@ -499,17 +487,17 @@ OP_DEF(adc_a_r) CYCLE(4); } -// 10001110: ADC A,(HL) -// DD:10001110: ADC A,(IX+d) +// 10001110: 01R: ADC A,(HL) +// DD:10001110: 01R: ADC A,(IX+d) OP_DEF(adc_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.adc_8(reg.a, src); CYCLE_IX(6, 14); } -// 10010rrr: SUB r +// 10010rrr: 01R: SUB r OP_DEF(sub_r) { uint r = op & 7; @@ -517,17 +505,17 @@ OP_DEF(sub_r) CYCLE(4); } -// 10010110: SUB (HL) -// DD:10010110: SUB (IX+d) +// 10010110: 01R: SUB (HL) +// DD:10010110: 01R: SUB (IX+d) OP_DEF(sub_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.sub_8(reg.a, src); CYCLE_IX(6, 14); } -// 10011rrr: SBC A,r +// 10011rrr: 01R: SBC A,r OP_DEF(sbc_a_r) { uint r = op & 7; @@ -535,17 +523,17 @@ OP_DEF(sbc_a_r) CYCLE(4); } -// 10011110: SBC A,(HL) -// DD:10011110: SBC A,(IX+d) +// 10011110: 01R: SBC A,(HL) +// DD:10011110: 01R: SBC A,(IX+d) OP_DEF(sbc_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.sbc_8(reg.a, src); CYCLE_IX(6, 14); } -// 10100rrr: AND r +// 10100rrr: 01R: AND r OP_DEF(and_r) { uint r = op & 7; @@ -553,17 +541,17 @@ OP_DEF(and_r) CYCLE(4); } -// 10100110: AND (HL) -// DD:10100110: AND (IX+d) +// 10100110: 01R: AND (HL) +// DD:10100110: 01R: AND (IX+d) OP_DEF(and_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.and_8(reg.a, src); CYCLE_IX(6, 14); } -// 10101rrr: XOR r +// 10101rrr: 01R: XOR r OP_DEF(xor_r) { uint r = op & 7; @@ -571,17 +559,17 @@ OP_DEF(xor_r) CYCLE(4); } -// 10101110: XOR (HL) -// DD:10101110: XOR (IX+d) +// 10101110: 01R: XOR (HL) +// DD:10101110: 01R: XOR (IX+d) OP_DEF(xor_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.xor_8(reg.a, src); CYCLE_IX(6, 14); } -// 10110rrr: OR r +// 10110rrr: 01R: OR r OP_DEF(or_r) { uint r = op & 7; @@ -589,17 +577,17 @@ OP_DEF(or_r) CYCLE(4); } -// 10110110: OR (HL) -// DD:10110110: OR (IX+d) +// 10110110: 01R: OR (HL) +// DD:10110110: 01R: OR (IX+d) OP_DEF(or_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.or_8(reg.a, src); CYCLE_IX(6, 14); } -// 10111rrr: CP r +// 10111rrr: 01R: CP r OP_DEF(cp_r) { uint r = op & 7; @@ -607,12 +595,12 @@ OP_DEF(cp_r) CYCLE(4); } -// 10111110: CP (HL) -// DD:10111110: CP (IX+d) +// 10111110: 01R: CP (HL) +// DD:10111110: 01R: CP (IX+d) OP_DEF(cp_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); ACC.sub_8(reg.a, src); CYCLE_IX(6, 14); } @@ -620,11 +608,11 @@ OP_DEF(cp_hlin) void MPU64180Device::ops_ret() { - uint16 addr = Pop16(); + uint16 addr = Pop2(); Jump(addr); } -// 11fff000: RET f +// 11fff000: 01R: RET f OP_DEF(ret_f) { uint fff = (op >> 3) & 7; @@ -636,22 +624,22 @@ OP_DEF(ret_f) } } -// 11zz0001: POP zz -// DD:11100001: POP IX +// 11zz0001: 01R: POP zz +// DD:11100001: 01R: POP IX OP_DEF(pop_zz) { // ここでは zz のうち BC, DE, HL のみなので ww が使える uint zz = (op >> 4) & 3; - uint16 data = Pop16(); + uint16 data = Pop2(); SetWW(zz, data); CYCLE_IX(9, 12); } -// 11fff010: JP f,nn +// 11fff010: 01R: JP f,nn OP_DEF(jp_f_nn) { uint fff = (op >> 3) & 7; - uint16 addr = Fetch16(); + uint16 addr = Fetch2(); if (reg.f.IsCond(fff)) { Jump(addr); CYCLE(9); @@ -660,21 +648,21 @@ OP_DEF(jp_f_nn) } } -// 11000011: JP nn +// 11000011: 01R: JP nn OP_DEF(jp_nn) { - uint32 addr = Fetch16(); + uint32 addr = Fetch2(); Jump(addr); CYCLE(9); } -// 11fff100: CALL f,nn +// 11fff100: 01R: CALL f,nn OP_DEF(call_f_nn) { uint fff = (op >> 3) & 7; - uint16 nn = Fetch16(); + uint16 nn = Fetch2(); if (reg.f.IsCond(fff)) { - Push16(reg.pc); + Push2(reg.pc); Jump(nn); CYCLE(16); } else { @@ -682,46 +670,46 @@ OP_DEF(call_f_nn) } } -// 11zz0101: PUSH zz -// DD:11100101: PUSH IX +// 11zz0101: 01R: PUSH zz +// DD:11100101: 01R: PUSH IX OP_DEF(push_zz) { // ここでは zz のうち BC, DE, HL のみなので ww が使える uint zz = (op >> 4) & 3; uint16 data = GetWW(zz); - Push16(data); + Push2(data); CYCLE_IX(11, 14); } -// 11000110: ADD A,n +// 11000110: 01R: ADD A,n OP_DEF(add_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.add_8(reg.a, n); CYCLE(6); } -// 11vvv111: RST v +// 11vvv111: 01R: RST v OP_DEF(rst) { - Push16(reg.pc); + Push2(reg.pc); uint v = op & 0x38; Jump(v); CYCLE(11); } -// 11001001: RET +// 11001001: 01R: RET OP_DEF(ret) { ops_ret(); CYCLE(9); } -// 11001011: op_CB +// 11001011: 01R: op_CB OP_DEF(cb) { // 2バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) { #include "hd64180switch_cb.inc" @@ -731,42 +719,42 @@ OP_DEF(cb) } } -// 11001101: CALL nn +// 11001101: 01R: CALL nn OP_DEF(call) { - uint16 nn = Fetch16(); - Push16(reg.pc); + uint16 nn = Fetch2(); + Push2(reg.pc); Jump(nn); CYCLE(16); } -// 11001110: ADC A,n +// 11001110: 01R: ADC A,n OP_DEF(adc_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.adc_8(reg.a, n); CYCLE(6); } -// 11010011: OUT (n),A +// 11010011: 01R: OUT (n),A OP_DEF(out_n_a) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); // バスの上位には A が出る uint32 addr = (reg.a << 8) | n; WriteIO(addr, reg.a); CYCLE(10); } -// 11010110: SUB n +// 11010110: 01R: SUB n OP_DEF(sub_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.sub_8(reg.a, n); CYCLE(6); } -// 11011001: EXX +// 11011001: 01R: EXX OP_DEF(exx) { uint8 tmpb = reg.b; @@ -790,10 +778,10 @@ OP_DEF(exx) CYCLE(3); } -// 11011011: IN A,(n) +// 11011011: 01R: IN A,(n) OP_DEF(in_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); // バスの上位には A が出る uint32 addr = (reg.a << 8) | n; reg.a = ReadIO(addr); @@ -807,7 +795,7 @@ MPU64180Device::ops_ddfd(ixiy_t xy) ixiy = xy; // 2バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) { #include "hd64180switch_dd.inc" @@ -817,47 +805,47 @@ MPU64180Device::ops_ddfd(ixiy_t xy) } } -// 11011101: op_DD +// 11011101: 01R: op_DD OP_DEF(dd) { ops_ddfd(USE_IX); } -// 11011110: SBC A,n +// 11011110: 01R: SBC A,n OP_DEF(sbc_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.sbc_8(reg.a, n); CYCLE(6); } -// 11100011: EX (SP),HL -// DD:11100011: EX (SP),IX +// 11100011: 01R: EX (SP),HL +// DD:11100011: 01R: EX (SP),IX OP_DEF(ex_sp_hl) { - uint32 tmp = Read16(reg.sp); - Write16(reg.sp, GetIHL()); + uint32 tmp = Read2(reg.sp); + Write2(reg.sp, GetIHL()); SetIHL(tmp); CYCLE_IX(16, 19); } -// 11100110: AND n +// 11100110: 01R: AND n OP_DEF(and_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.and_8(reg.a, src); CYCLE(6); } -// 11101001: JP (HL) -// DD:11101001: JP (IX) +// 11101001: 01R: JP (HL) +// DD:11101001: 01R: JP (IX) OP_DEF(jp_hl) { Jump(GetIHL()); CYCLE_IX(3, 6); } -// 11101011: EX DE,HL +// 11101011: 01R: EX DE,HL OP_DEF(ex_de_hl) { uint16 tmp = reg.GetDE(); @@ -866,10 +854,10 @@ OP_DEF(ex_de_hl) CYCLE(3); } -// 11101101: op_ED +// 11101101: 01R: op_ED OP_DEF(ed) { - op = Fetch8(); + op = Fetch1(); switch (op) { #include "hd64180switch_ed.inc" @@ -879,24 +867,24 @@ OP_DEF(ed) } } -// 11101110: XOR n +// 11101110: 01R: XOR n OP_DEF(xor_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.xor_8(reg.a, src); CYCLE(6); } -// 11110001: POP AF +// 11110001: 01R: POP AF OP_DEF(pop_af) { - uint16 data = Pop16(); + uint16 data = Pop2(); reg.a = data >> 8; reg.f.Set(data & 0xff); CYCLE(9); } -// 11110011: DI +// 11110011: 01R: DI OP_DEF(di) { ief1 = false; @@ -908,33 +896,33 @@ OP_DEF(di) CYCLE(3); } -// 11110101: PUSH AF +// 11110101: 01R: PUSH AF OP_DEF(push_af) { uint16 data; data = reg.a << 8; data |= reg.f.Get(); - Push16(data); + Push2(data); CYCLE(11); } -// 11110110: OR n +// 11110110: 01R: OR n OP_DEF(or_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.or_8(reg.a, src); CYCLE(6); } -// 11111001: LD SP,HL -// DD:11111001: LD SP,IX +// 11111001: 01R: LD SP,HL +// DD:11111001: 01R: LD SP,IX OP_DEF(ld_sp_hl) { reg.sp = GetIHL(); CYCLE_IX(4, 7); } -// 11111011: EI +// 11111011: 01R: EI OP_DEF(ei) { ief1 = true; @@ -946,21 +934,21 @@ OP_DEF(ei) CYCLE(3); } -// 11111101: op_FD +// 11111101: 01R: op_FD OP_DEF(fd) { ops_ddfd(USE_IY); } -// 11111110: CP n +// 11111110: 01R: CP n OP_DEF(cp_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); ACC.sub_8(reg.a, n); CYCLE(6); } -// CB:00000rrr: RLC r +// CB:00000rrr: 01R: RLC r OP_DEF(rlc_r) { uint r = op & 7; @@ -968,18 +956,18 @@ OP_DEF(rlc_r) CYCLE(7); } -// CB:00000110: RLC (HL) -// DD_CB:00000110: RLC (IX+d) +// CB:00000110: 01R: RLC (HL) +// DD_CB:00000110: 01R: RLC (IX+d) OP_DEF(rlc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rlc_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00001rrr: RRC r +// CB:00001rrr: 01R: RRC r OP_DEF(rrc_r) { uint r = op & 7; @@ -987,18 +975,18 @@ OP_DEF(rrc_r) CYCLE(7); } -// CB:00001110: RRC (HL) -// DD_CB:00001110: RRC (IX+d) +// CB:00001110: 01R: RRC (HL) +// DD_CB:00001110: 01R: RRC (IX+d) OP_DEF(rrc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rrc_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00010rrr: RL r +// CB:00010rrr: 01R: RL r OP_DEF(rl_r) { uint r = op & 7; @@ -1006,18 +994,18 @@ OP_DEF(rl_r) CYCLE(7); } -// CB:00010110: RL (HL) -// DD_CB:00010110: RL (IX+d) +// CB:00010110: 01R: RL (HL) +// DD_CB:00010110: 01R: RL (IX+d) OP_DEF(rl_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rl_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00011rrr: RR r +// CB:00011rrr: 01R: RR r OP_DEF(rr_r) { uint r = op & 7; @@ -1025,18 +1013,18 @@ OP_DEF(rr_r) CYCLE(7); } -// CB:00011110: RR (HL) -// DD_CB:00011110: RR (IX+d) +// CB:00011110: 01R: RR (HL) +// DD_CB:00011110: 01R: RR (IX+d) OP_DEF(rr_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rr_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00100rrr: SLA r +// CB:00100rrr: 01R: SLA r OP_DEF(sla_r) { uint r = op & 7; @@ -1044,18 +1032,18 @@ OP_DEF(sla_r) CYCLE(7); } -// CB:00100110: SLA (HL) -// DD_CB:00100110: SLA (IX+d) +// CB:00100110: 01R: SLA (HL) +// DD_CB:00100110: 01R: SLA (IX+d) OP_DEF(sla_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.sla_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00101rrr: SRA r +// CB:00101rrr: 01R: SRA r OP_DEF(sra_r) { uint r = op & 7; @@ -1063,18 +1051,49 @@ OP_DEF(sra_r) CYCLE(7); } -// CB:00101110: SRA (HL) -// DD_CB:00101110: SRA (IX+d) +// CB:00101110: 01R: SRA (HL) +// DD_CB:00101110: 01R: SRA (IX+d) OP_DEF(sra_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.sra_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:00111rrr: SRL r +// CB:00110rrr: Z--: SLL +OP_DEF(sll_r) +{ + if (1) { + op_illegal(2); + } else { + uint r = op & 7; + reg.r[r] = ACC.in_8(ACC.sll_8(reg.r[r])); + CYCLE(7); + } +} + +// CB:00110110: Z--: SLL (HL) +// DD_CB:00110110: Z--: SLL (IX+d) +OP_DEF(sll_hlin) +{ + if (1) { + if (ixiy == USE_HL) { + op_illegal(2); + } else { + op_illegal(3); + } + } else { + uint32 addr = LeaIHL(); + uint32 src = Read1(addr); + uint32 res = ACC.in_8(ACC.sll_8(src)); + Write1(addr, res); + CYCLE_IX(13, 19); + } +} + +// CB:00111rrr: 01R: SRL r OP_DEF(srl_r) { uint r = op & 7; @@ -1082,18 +1101,18 @@ OP_DEF(srl_r) CYCLE(7); } -// CB:00111110: SRL (HL) -// DD_CB:00111110: SRL (IX+d) +// CB:00111110: 01R: SRL (HL) +// DD_CB:00111110: 01R: SRL (IX+d) OP_DEF(srl_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.srl_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } -// CB:01bbbrrr: BIT b,r +// CB:01bbbrrr: 01R: BIT b,r OP_DEF(bit_r) { uint b = (op >> 3) & 7; @@ -1102,18 +1121,18 @@ OP_DEF(bit_r) CYCLE(6); } -// CB:01bbb110: BIT b,(HL) -// DD_CB:01bbb110: BIT b,(IX+d) +// CB:01bbb110: 01R: BIT b,(HL) +// DD_CB:01bbb110: 01R: BIT b,(IX+d) OP_DEF(bit_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); ACC.bit_8(b, data); CYCLE_IX(9, 15); } -// CB:10bbbrrr: RES b,r +// CB:10bbbrrr: 01R: RES b,r OP_DEF(res_r) { uint b = (op >> 3) & 7; @@ -1122,19 +1141,19 @@ OP_DEF(res_r) CYCLE(7); } -// CB:10bbb110: RES b,(HL) -// DD_CB:10bbb110: RES b,(IX+d) +// CB:10bbb110: 01R: RES b,(HL) +// DD_CB:10bbb110: 01R: RES b,(IX+d) OP_DEF(res_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); data &= ~(1U << b); - Write8(addr, data); + Write1(addr, data); CYCLE_IX(13, 19); } -// CB:11bbbrrr: SET b,r +// CB:11bbbrrr: 01R: SET b,r OP_DEF(set_r) { uint b = (op >> 3) & 7; @@ -1143,38 +1162,38 @@ OP_DEF(set_r) CYCLE(7); } -// CB:11bbb110: SET b,(HL) -// DD_CB:11bbb110: SET b,(IX+d) +// CB:11bbb110: 01R: SET b,(HL) +// DD_CB:11bbb110: 01R: SET b,(IX+d) OP_DEF(set_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); data |= 1U << b; - Write8(addr, data); + Write1(addr, data); CYCLE_IX(13, 19); } -// ED:00rrr000: IN0 r,(n) (HD64*180 only) +// ED:00rrr000: -1-: IN0 r,(n) OP_DEF(in0_r_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 src = ReadIO(n); uint r = op >> 3; reg.r[r] = ACC.in_8(src); CYCLE(12); } -// ED:00rrr001: OUT0 (n),r (HD64*180 only) +// ED:00rrr001: -1-: OUT0 (n),r OP_DEF(out0_n_r) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 r = op >> 3; WriteIO(n, reg.r[r]); CYCLE(13); } -// ED:00rrr100: TST r (HD64*180 only) +// ED:00rrr100: -1-: TST r OP_DEF(tst_r) { uint r = op & 7; @@ -1182,25 +1201,25 @@ OP_DEF(tst_r) CYCLE(7); } -// ED:00110000: IN0 F,(n) (HD64*180 only) +// ED:00110000: -1-: IN0 F,(n) OP_DEF(in0_f_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 src = ReadIO(n); ACC.in_8(src); CYCLE(12); } -// ED:00110100: TST (HL) (HD64*180 only) +// ED:00110100: -1-: TST (HL) OP_DEF(tst_hlin) { uint16 addr = reg.GetHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); ACC.tst_8(reg.a, src); CYCLE(10); } -// ED:01rrr000: IN r,(C) +// ED:01rrr000: 01R: IN r,(C) OP_DEF(in_r_c) { uint r = (op >> 3) & 7; @@ -1211,7 +1230,7 @@ OP_DEF(in_r_c) CYCLE(9); } -// ED:01rrr001: OUT (C),r +// ED:01rrr001: 01R: OUT (C),r OP_DEF(out_c_r) { uint r = (op >> 3) & 7; @@ -1221,7 +1240,7 @@ OP_DEF(out_c_r) CYCLE(10); } -// ED:01ww0010: SBC HL,ww +// ED:01ww0010: 01R: SBC HL,ww OP_DEF(sbc_hl_ww) { uint ww = (op >> 4) & 3; @@ -1232,46 +1251,46 @@ OP_DEF(sbc_hl_ww) CYCLE(10); } -// ED:01ww0011: LD (nn),ww +// ED:01ww0011: 01R: LD (nn),ww OP_DEF(ld_nnin_ww) { uint ww = (op >> 4) & 3; uint32 src = GetWW(ww); - uint32 nn = Fetch16(); - Write16(nn, src); + uint32 nn = Fetch2(); + Write2(nn, src); CYCLE(19); } -// ED:01000100: NEG +// ED:01000100: 01R: NEG OP_DEF(neg) { reg.a = ACC.sub_8(0, reg.a); CYCLE(6); } -// ED:01000101: RETN +// ED:01000101: 01R: RETN OP_DEF(retn) { ief1 = ief2; - Jump(Pop16()); + Jump(Pop2()); } -// ED:01000110: IM 0 +// ED:01000110: 01R: IM 0 OP_DEF(im_0) { int0mode = 0; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } -// ED:01000111: LD I,A +// ED:01000111: 01R: LD I,A OP_DEF(ld_i_a) { reg_i = reg.a; CYCLE(6); } -// ED:01ww1010: ADC HL,ww +// ED:01ww1010: 01R: ADC HL,ww OP_DEF(adc_hl_ww) { uint ww = (op >> 4) & 3; @@ -1282,17 +1301,17 @@ OP_DEF(adc_hl_ww) CYCLE(10); } -// ED:01ww1011: LD ww,(nn) +// ED:01ww1011: 01R: LD ww,(nn) OP_DEF(ld_ww_nnin) { uint ww = (op >> 4) & 3; - uint32 nn = Fetch16(); - uint32 src = Read16(nn); + uint32 nn = Fetch2(); + uint32 src = Read2(nn); SetWW(ww, src); CYCLE(18); } -// ED:01ww1100: MLT ww (HD64*180 only) +// ED:01ww1100: -1-: MLT ww OP_DEF(mlt) { uint ww = (op >> 4) & 3; @@ -1303,29 +1322,29 @@ OP_DEF(mlt) CYCLE(17); } -// ED:01001101: RETI +// ED:01001101: 01R: RETI OP_DEF(reti) { ops_ret(); CYCLE(12); } -// ED:01001111: LD R,A +// ED:01001111: 01R: LD R,A OP_DEF(ld_r_a) { reg_r = reg.a; CYCLE(6); } -// ED:01010110: IM 1 +// ED:01010110: 01R: IM 1 OP_DEF(im_1) { int0mode = 1; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } -// ED:01010111: LD A,I +// ED:01010111: 01R: LD A,I OP_DEF(ld_a_i) { reg.a = ACC.ld_ir8(reg_i); @@ -1339,15 +1358,15 @@ OP_DEF(ld_a_i) CYCLE(6); } -// ED:01011110: IM 2 +// ED:01011110: 01R: IM 2 OP_DEF(im_2) { int0mode = 2; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } -// ED:01011111: LD A,R +// ED:01011111: 01R: LD A,R OP_DEF(ld_a_r) { reg.a = ACC.ld_ir8(GetR()); @@ -1361,15 +1380,15 @@ OP_DEF(ld_a_r) CYCLE(6); } -// ED:01100100: TST n (HD64*180 only) +// ED:01100100: -1-: TST n OP_DEF(tst_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); ACC.and_8(reg.a, src); CYCLE(9); } -// ED:01100111: RRD +// ED:01100111: 01R: RRD OP_DEF(rrd) { // +-----------+ +---+ @@ -1381,15 +1400,15 @@ OP_DEF(rrd) // +-------------------+ uint32 hl = reg.GetHL(); - uint32 m = Read8(hl); + uint32 m = Read1(hl); uint32 a = (reg.a & 0xf0) | (m & 0x0f); uint32 b = (reg.a << 4) | (m >> 4); - Write8(hl, b); + Write1(hl, b); reg.a = ACC.in_8(a); CYCLE(16); } -// ED:01101111: RLD +// ED:01101111: 01R: RLD OP_DEF(rld) { // +-------------------+ @@ -1401,15 +1420,15 @@ OP_DEF(rld) // +-----------+ +---+ uint32 hl = reg.GetHL(); - uint32 m = Read8(hl); + uint32 m = Read1(hl); uint32 a = (reg.a & 0xf0) | (m >> 4); uint32 b = (m << 4) | (reg.a & 0x0f); - Write8(hl, b); + Write1(hl, b); reg.a = ACC.in_8(a); CYCLE(16); } -// ED:01110000: IN F,(C) +// ED:01110000: 01R: IN F,(C) OP_DEF(in_f_c) { // バスの上位には B が出る @@ -1419,17 +1438,17 @@ OP_DEF(in_f_c) CYCLE(9); } -// ED:01110100: TSTIO n (HD64*180 only) +// ED:01110100: -1-: TSTIO n OP_DEF(tstio_n) { // バスの上位は 0 になる - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 dst = ReadIO(reg.c); ACC.tst_8(dst, n); CYCLE(12); } -// ED:01110110: SLP (HD64*180 only) +// ED:01110110: -1-: SLP OP_DEF(slp) { putlog(0, "SLP (NOT IMPLEMENTED)"); @@ -1442,7 +1461,7 @@ void MPU64180Device::ops_otim(int inc) { uint32 hl = reg.GetHL(); - uint32 src = Read8(hl); + uint32 src = Read1(hl); // バスの上位は 0 になる WriteIO(reg.c, src); reg.c += inc; @@ -1452,13 +1471,13 @@ MPU64180Device::ops_otim(int inc) CYCLE(14); } -// ED:10000011: OTIM (HD64*180 only) +// ED:10000011: -1-: OTIM OP_DEF(otim) { ops_otim(+1); } -// ED:10001011: OTDM (HD64*180 only) +// ED:10001011: -1-: OTDM OP_DEF(otdm) { ops_otim(-1); @@ -1481,14 +1500,14 @@ MPU64180Device::ops_otmr_until() } } -// ED:10010011: OTIMR (HD64*180 only) +// ED:10010011: -1-: OTIMR OP_DEF(otimr) { OP_FUNC(otim); ops_otmr_until(); } -// ED:10011011: OTDMR (HD64*180 only) +// ED:10011011: -1-: OTDMR OP_DEF(otdmr) { OP_FUNC(otdm); @@ -1503,8 +1522,8 @@ MPU64180Device::ops_ldi(int inc) uint32 de = reg.GetDE(); uint32 bc = reg.GetBC(); - uint32 data = Read8(hl); - Write8(de, data); + uint32 data = Read1(hl); + Write1(de, data); hl += inc; de += inc; bc--; @@ -1519,7 +1538,7 @@ MPU64180Device::ops_ldi(int inc) CYCLE(12); } -// ED:10100000: LDI +// ED:10100000: 01R: LDI OP_DEF(ldi) { ops_ldi(+1); @@ -1532,7 +1551,7 @@ MPU64180Device::ops_cpi(int inc) uint32 hl = reg.GetHL(); uint32 bc = reg.GetBC(); - uint32 src = Read8(hl); + uint32 src = Read1(hl); ACC.sub_8(reg.a, src, true); hl += inc; bc--; @@ -1544,7 +1563,7 @@ MPU64180Device::ops_cpi(int inc) CYCLE(12); } -// ED:10100001: CPI +// ED:10100001: 01R: CPI OP_DEF(cpi) { ops_cpi(+1); @@ -1558,7 +1577,7 @@ MPU64180Device::ops_ini(int inc) // バスの上位には B が出る uint32 addr = reg.GetBC(); uint32 data = ReadIO(addr); - Write8(hl, data); + Write1(hl, data); hl += inc; reg.b--; reg.SetHL(hl); @@ -1568,7 +1587,7 @@ MPU64180Device::ops_ini(int inc) CYCLE(12); } -// ED:10100010: INI +// ED:10100010: 01R: INI OP_DEF(ini) { ops_ini(+1); @@ -1581,7 +1600,7 @@ MPU64180Device::ops_outi(int inc) uint32 hl = reg.GetHL(); // バスの上位には B が出る uint32 addr = reg.GetBC(); - uint32 data = Read8(hl); + uint32 data = Read1(hl); WriteIO(addr, data); hl += inc; reg.b--; @@ -1592,103 +1611,103 @@ MPU64180Device::ops_outi(int inc) CYCLE(12); } -// ED:10100011: OUTI +// ED:10100011: 01R: OUTI OP_DEF(outi) { ops_outi(+1); } -// ED:10101000: LDD +// ED:10101000: 01R: LDD OP_DEF(ldd) { ops_ldi(-1); } -// ED:10101001: CPD +// ED:10101001: 01R: CPD OP_DEF(cpd) { ops_cpi(-1); } -// ED:10101010: IND +// ED:10101010: 01R: IND OP_DEF(ind) { ops_ini(-1); } -// ED:10101011: OUTD +// ED:10101011: 01R: OUTD OP_DEF(outd) { ops_outi(-1); } -// ED:10110000: LDIR +// ED:10110000: 01R: LDIR OP_DEF(ldir) { - REPEAT_UNTIL(ldi); + REPEAT_LD(ldi); } -// ED:10110001: CPIR +// ED:10110001: 01R: CPIR OP_DEF(cpir) { - REPEAT_UNTIL(cpi); + REPEAT_CP(cpi); } -// ED:10110010: INIR +// ED:10110010: 01R: INIR OP_DEF(inir) { - REPEAT_UNTIL(ini); + REPEAT_IO(ini); } -// ED:10110011: OTIR +// ED:10110011: 01R: OTIR OP_DEF(otir) { - REPEAT_UNTIL(outi); + REPEAT_IO(outi); } -// ED:10111000: LDDR +// ED:10111000: 01R: LDDR OP_DEF(lddr) { - REPEAT_UNTIL(ldd); + REPEAT_LD(ldd); } -// ED:10111001: CPDR +// ED:10111001: 01R: CPDR OP_DEF(cpdr) { - REPEAT_UNTIL(cpd); + REPEAT_CP(cpd); } -// ED:10111010: INDR +// ED:10111010: 01R: INDR OP_DEF(indr) { - REPEAT_UNTIL(ind); + REPEAT_IO(ind); } -// ED:10111011: OTDR +// ED:10111011: 01R: OTDR OP_DEF(otdr) { - REPEAT_UNTIL(outd); + REPEAT_IO(outd); } -// ED:11rrr001: MULUB A,r (R800 only) +// ED:11rrr001: --R: MULUB A,r OP_DEF(mulub_a_r) { op_illegal(2); } -// ED:11000011: MULUB HL,BC (R800 only) +// ED:11000011: --R: MULUB HL,BC OP_DEF(mulub_hl_bc) { op_illegal(2); } -// ED:11110011: MULUB HL,SP (R800 only) +// ED:11110011: --R: MULUB HL,SP OP_DEF(mulub_hl_sp) { op_illegal(2); } -// ED:11111111: SYSCALL (HD64*180 only) +// ED:11111111: -N-: SYSCALL OP_DEF(syscall) { // MSX-DOS エミュレーションのような何か。 @@ -1705,80 +1724,86 @@ OP_DEF(syscall) } } -// DD:00rrr100: INC ixr (Z80/R800) +// DD:00rrr100: Z-Z: INC ixr OP_DEF(inc_ixr) { op_illegal(2); } -// DD:00rrr101: DEC ixr (Z80/R800) +// DD:00rrr101: Z-Z: DEC ixr OP_DEF(dec_ixr) { op_illegal(2); } -// DD:01rrrsss: LD r,ixs (Z80/R800) +// DD:00rrr110: Z-Z: LD ixr,n +OP_DEF(ld_ixr_n) +{ + op_illegal(2); +} + +// DD:01rrrsss: Z-Z: LD r,ixs OP_DEF(ld_r_ixs) { op_illegal(2); } -// DD:10000rrr: ADD A,ixr (Z80/R800) +// DD:10000rrr: Z-Z: ADD A,ixr OP_DEF(add_a_ixr) { op_illegal(2); } -// DD:10001rrr: ADC A,ixr (Z80/R800) +// DD:10001rrr: Z-Z: ADC A,ixr OP_DEF(adc_a_ixr) { op_illegal(2); } -// DD:10010rrr: SUB ixr (Z80/R800) +// DD:10010rrr: Z-Z: SUB ixr OP_DEF(sub_ixr) { op_illegal(2); } -// DD:10011rrr: SBC A,ixr (Z80/R800) +// DD:10011rrr: Z-Z: SBC A,ixr OP_DEF(sbc_a_ixr) { op_illegal(2); } -// DD:10100rrr: AND ixr (Z80/R800) +// DD:10100rrr: Z-Z: AND ixr OP_DEF(and_ixr) { op_illegal(2); } -// DD:10101rrr: XOR ixr (Z80/R800) +// DD:10101rrr: Z-Z: XOR ixr OP_DEF(xor_ixr) { op_illegal(2); } -// DD:10110rrr: OR ixr (Z80/R800) +// DD:10110rrr: Z-Z: OR ixr OP_DEF(or_ixr) { op_illegal(2); } -// DD:10111rrr: CP ixr (Z80/R800) +// DD:10111rrr: Z-Z: CP ixr OP_DEF(cp_ixr) { op_illegal(2); } -// DD:11001011: op_DD_CB +// DD:11001011: 01R: op_DD_CB OP_DEF(dd_cb) { // DD CB の場合は 3バイト目が d で、4バイト目が命令語。 - ixd = Fetch8(); + ixd = Fetch1(); // 4バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) {