--- nono/hd64180/hd64180ops.cpp 2026/04/29 17:05:18 1.1 +++ nono/hd64180/hd64180ops.cpp 2026/04/29 17:05:30 1.1.1.3 @@ -14,46 +14,17 @@ } \ } while (0) -uint32 -MPU64180Device::Read16(uint32 addr) -{ - uint32 data; - - data = Read8(addr); - data |= Read8(addr + 1) << 8; - - return data; -} - -void -MPU64180Device::Write16(uint32 addr, uint32 data) -{ - Write8(addr, data & 0xff); - Write8(addr + 1, data >> 8); -} - -uint32 -MPU64180Device::Fetch16() -{ - uint32 data; - - data = Fetch8(); - data |= Fetch8() << 8; - - return data; -} - void -MPU64180Device::Push16(uint32 data) +MPU64180Device::Push2(uint32 data) { reg.sp -= 2; - Write16(reg.sp, data); + Write2(reg.sp, data); } uint32 -MPU64180Device::Pop16() +MPU64180Device::Pop2() { - uint16 data = Read16(reg.sp); + uint16 data = Read2(reg.sp); reg.sp += 2; return data; } @@ -67,7 +38,7 @@ MPU64180Device::GetIHL() const case USE_IX: return reg.ix; break; case USE_IY: return reg.iy; break; default: - PANIC("invalid ixiy = %d", (int)ixiy); + PANIC("invalid ixiy = %u", (uint)ixiy); } } @@ -80,7 +51,7 @@ MPU64180Device::SetIHL(uint32 data) case USE_IX: reg.ix = data; break; case USE_IY: reg.iy = data; break; default: - PANIC("invalid ixiy = %d", (int)ixiy); + PANIC("invalid ixiy = %u", (uint)ixiy); } } @@ -93,7 +64,7 @@ MPU64180Device::LeaIHL() if (ixiy != USE_HL) { // DD と DD CB で +d をフェッチする順序が違う。 if ((int32)ixd < 0) { - ixd = Fetch8(); + ixd = Fetch1(); } addr += (int32)(int8)ixd; } @@ -143,7 +114,7 @@ OP_DEF(nop) // DD:00100001: LD IX,nn OP_DEF(ld_ww_nn) { - uint32 nn = Fetch16(); + uint32 nn = Fetch2(); uint ww = (op >> 4) & 3; SetWW(ww, nn); CYCLE_IX(9, 12); @@ -154,7 +125,7 @@ OP_DEF(ld_wwin_a) { uint ww = op >> 4; uint32 addr = GetWW(ww); // ww は BC, DE のみ - Write8(addr, reg.a); + Write1(addr, reg.a); CYCLE_IX(7, 15); } @@ -189,7 +160,7 @@ OP_DEF(dec_r) OP_DEF(ld_r_n) { uint r = op >> 3; - reg.r[r] = Fetch8(); + reg.r[r] = Fetch1(); CYCLE(6); } @@ -229,7 +200,7 @@ OP_DEF(ld_a_wwin) { uint ww = op >> 4; uint32 addr = GetWW(ww); // ww は BC, DE のみ - reg.a = Read8(addr); + reg.a = Read1(addr); CYCLE(6); } @@ -254,7 +225,7 @@ OP_DEF(rrca) // 00010000: DJNZ n OP_DEF(djnz) { - int8 n = Fetch8(); + int8 n = Fetch1(); reg.b--; if (reg.b != 0) { Jump(reg.pc + n); @@ -274,7 +245,7 @@ OP_DEF(rla) // 00011000: JR n OP_DEF(jr) { - int8 n = Fetch8(); + int8 n = Fetch1(); Jump(reg.pc + n); CYCLE(8); } @@ -289,7 +260,7 @@ OP_DEF(rra) // 00100000: JR NZ,n OP_DEF(jr_nz) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsZ() == false) { Jump(reg.pc + n); CYCLE(8); @@ -302,23 +273,22 @@ OP_DEF(jr_nz) // DD:00100010: LD (nn),IX OP_DEF(ld_nnin_hl) { - uint32 nn = Fetch16(); - Write16(nn, GetIHL()); + uint32 nn = Fetch2(); + Write2(nn, GetIHL()); CYCLE_IX(16, 19); } // 00100111: DAA OP_DEF(daa) { - // XXX 未実装 - putlog(0, "DAA (NOT IMPLEMENTED)"); + reg.a = ACC.daa_8(reg.a); CYCLE(4); } // 00101000: JR Z,n OP_DEF(jr_z) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsZ()) { Jump(reg.pc + n); CYCLE(8); @@ -331,8 +301,8 @@ OP_DEF(jr_z) // DD:00101010: LD IX,(nn) OP_DEF(ld_hl_nnin) { - uint32 nn = Fetch16(); - uint32 src = Read16(nn); + uint32 nn = Fetch2(); + uint32 src = Read2(nn); SetIHL(src); CYCLE_IX(15, 18); } @@ -349,7 +319,7 @@ OP_DEF(cpl) // 00110000: JR NC,n OP_DEF(jr_nc) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsC() == false) { Jump(reg.pc + n); CYCLE(8); @@ -361,8 +331,8 @@ OP_DEF(jr_nc) // 00110010: LD (nn),A OP_DEF(ld_nnin_a) { - uint32 addr = Fetch16(); - Write8(addr, reg.a); + uint32 addr = Fetch2(); + Write1(addr, reg.a); CYCLE(13); } @@ -371,9 +341,9 @@ OP_DEF(ld_nnin_a) OP_DEF(inc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 dst = ACC.inc_8(src); - Write8(addr, dst); + Write1(addr, dst); CYCLE_IX(10, 18); } @@ -382,9 +352,9 @@ OP_DEF(inc_hlin) OP_DEF(dec_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 dst = ACC.dec_8(src); - Write8(addr, dst); + Write1(addr, dst); CYCLE_IX(10, 18); } @@ -393,8 +363,8 @@ OP_DEF(dec_hlin) OP_DEF(ld_hlin_n) { uint32 addr = LeaIHL(); - uint32 src = Fetch8(); - Write8(addr, src); + uint32 src = Fetch1(); + Write1(addr, src); CYCLE_IX(9, 15); } @@ -410,7 +380,7 @@ OP_DEF(scf) // 00111000: JR C,n OP_DEF(jr_c) { - int8 n = Fetch8(); + int8 n = Fetch1(); if (reg.f.IsC()) { Jump(reg.pc + n); CYCLE(8); @@ -422,8 +392,8 @@ OP_DEF(jr_c) // 00111010: LD A,(nn) OP_DEF(ld_a_nnin) { - uint32 nn = Fetch16(); - reg.a = Read8(nn); + uint32 nn = Fetch2(); + reg.a = Read1(nn); CYCLE(12); } @@ -451,7 +421,7 @@ OP_DEF(ld_r_hlin) { uint d = (op >> 3) & 7; uint16 addr = LeaIHL(); - reg.r[d] = Read8(addr); + reg.r[d] = Read1(addr); CYCLE_IX(6, 14); } @@ -461,7 +431,7 @@ OP_DEF(ld_hlin_s) { uint s = op & 7; uint32 addr = LeaIHL(); - Write8(addr, reg.r[s]); + Write1(addr, reg.r[s]); CYCLE_IX(7, 15); } @@ -486,7 +456,7 @@ OP_DEF(add_a_r) OP_DEF(add_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.add_8(reg.a, src); CYCLE_IX(6, 14); } @@ -504,7 +474,7 @@ OP_DEF(adc_a_r) OP_DEF(adc_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.adc_8(reg.a, src); CYCLE_IX(6, 14); } @@ -522,7 +492,7 @@ OP_DEF(sub_r) OP_DEF(sub_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.sub_8(reg.a, src); CYCLE_IX(6, 14); } @@ -540,7 +510,7 @@ OP_DEF(sbc_a_r) OP_DEF(sbc_a_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.sbc_8(reg.a, src); CYCLE_IX(6, 14); } @@ -558,7 +528,7 @@ OP_DEF(and_r) OP_DEF(and_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.and_8(reg.a, src); CYCLE_IX(6, 14); } @@ -576,7 +546,7 @@ OP_DEF(xor_r) OP_DEF(xor_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.xor_8(reg.a, src); CYCLE_IX(6, 14); } @@ -594,7 +564,7 @@ OP_DEF(or_r) OP_DEF(or_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); reg.a = ACC.or_8(reg.a, src); CYCLE_IX(6, 14); } @@ -612,7 +582,7 @@ OP_DEF(cp_r) OP_DEF(cp_hlin) { uint16 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); ACC.sub_8(reg.a, src); CYCLE_IX(6, 14); } @@ -620,7 +590,7 @@ OP_DEF(cp_hlin) void MPU64180Device::ops_ret() { - uint16 addr = Pop16(); + uint16 addr = Pop2(); Jump(addr); } @@ -642,7 +612,7 @@ OP_DEF(pop_zz) { // ここでは zz のうち BC, DE, HL のみなので ww が使える uint zz = (op >> 4) & 3; - uint16 data = Pop16(); + uint16 data = Pop2(); SetWW(zz, data); CYCLE_IX(9, 12); } @@ -651,7 +621,7 @@ OP_DEF(pop_zz) OP_DEF(jp_f_nn) { uint fff = (op >> 3) & 7; - uint16 addr = Fetch16(); + uint16 addr = Fetch2(); if (reg.f.IsCond(fff)) { Jump(addr); CYCLE(9); @@ -663,7 +633,7 @@ OP_DEF(jp_f_nn) // 11000011: JP nn OP_DEF(jp_nn) { - uint32 addr = Fetch16(); + uint32 addr = Fetch2(); Jump(addr); CYCLE(9); } @@ -672,9 +642,9 @@ OP_DEF(jp_nn) OP_DEF(call_f_nn) { uint fff = (op >> 3) & 7; - uint16 nn = Fetch16(); + uint16 nn = Fetch2(); if (reg.f.IsCond(fff)) { - Push16(reg.pc); + Push2(reg.pc); Jump(nn); CYCLE(16); } else { @@ -689,14 +659,14 @@ OP_DEF(push_zz) // ここでは zz のうち BC, DE, HL のみなので ww が使える uint zz = (op >> 4) & 3; uint16 data = GetWW(zz); - Push16(data); + Push2(data); CYCLE_IX(11, 14); } // 11000110: ADD A,n OP_DEF(add_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.add_8(reg.a, n); CYCLE(6); } @@ -704,7 +674,7 @@ OP_DEF(add_a_n) // 11vvv111: RST v OP_DEF(rst) { - Push16(reg.pc); + Push2(reg.pc); uint v = op & 0x38; Jump(v); CYCLE(11); @@ -721,7 +691,7 @@ OP_DEF(ret) OP_DEF(cb) { // 2バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) { #include "hd64180switch_cb.inc" @@ -734,8 +704,8 @@ OP_DEF(cb) // 11001101: CALL nn OP_DEF(call) { - uint16 nn = Fetch16(); - Push16(reg.pc); + uint16 nn = Fetch2(); + Push2(reg.pc); Jump(nn); CYCLE(16); } @@ -743,7 +713,7 @@ OP_DEF(call) // 11001110: ADC A,n OP_DEF(adc_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.adc_8(reg.a, n); CYCLE(6); } @@ -751,7 +721,7 @@ OP_DEF(adc_a_n) // 11010011: OUT (n),A OP_DEF(out_n_a) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); // バスの上位には A が出る uint32 addr = (reg.a << 8) | n; WriteIO(addr, reg.a); @@ -761,7 +731,7 @@ OP_DEF(out_n_a) // 11010110: SUB n OP_DEF(sub_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.sub_8(reg.a, n); CYCLE(6); } @@ -793,7 +763,7 @@ OP_DEF(exx) // 11011011: IN A,(n) OP_DEF(in_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); // バスの上位には A が出る uint32 addr = (reg.a << 8) | n; reg.a = ReadIO(addr); @@ -807,7 +777,7 @@ MPU64180Device::ops_ddfd(ixiy_t xy) ixiy = xy; // 2バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) { #include "hd64180switch_dd.inc" @@ -826,7 +796,7 @@ OP_DEF(dd) // 11011110: SBC A,n OP_DEF(sbc_a_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); reg.a = ACC.sbc_8(reg.a, n); CYCLE(6); } @@ -835,8 +805,8 @@ OP_DEF(sbc_a_n) // DD:11100011: EX (SP),IX OP_DEF(ex_sp_hl) { - uint32 tmp = Read16(reg.sp); - Write16(reg.sp, GetIHL()); + uint32 tmp = Read2(reg.sp); + Write2(reg.sp, GetIHL()); SetIHL(tmp); CYCLE_IX(16, 19); } @@ -844,7 +814,7 @@ OP_DEF(ex_sp_hl) // 11100110: AND n OP_DEF(and_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.and_8(reg.a, src); CYCLE(6); } @@ -869,7 +839,7 @@ OP_DEF(ex_de_hl) // 11101101: op_ED OP_DEF(ed) { - op = Fetch8(); + op = Fetch1(); switch (op) { #include "hd64180switch_ed.inc" @@ -882,7 +852,7 @@ OP_DEF(ed) // 11101110: XOR n OP_DEF(xor_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.xor_8(reg.a, src); CYCLE(6); } @@ -890,7 +860,7 @@ OP_DEF(xor_n) // 11110001: POP AF OP_DEF(pop_af) { - uint16 data = Pop16(); + uint16 data = Pop2(); reg.a = data >> 8; reg.f.Set(data & 0xff); CYCLE(9); @@ -914,14 +884,14 @@ OP_DEF(push_af) uint16 data; data = reg.a << 8; data |= reg.f.Get(); - Push16(data); + Push2(data); CYCLE(11); } // 11110110: OR n OP_DEF(or_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); reg.a = ACC.or_8(reg.a, src); CYCLE(6); } @@ -955,7 +925,7 @@ OP_DEF(fd) // 11111110: CP n OP_DEF(cp_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); ACC.sub_8(reg.a, n); CYCLE(6); } @@ -973,9 +943,9 @@ OP_DEF(rlc_r) OP_DEF(rlc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rlc_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -992,9 +962,9 @@ OP_DEF(rrc_r) OP_DEF(rrc_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rrc_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1011,9 +981,9 @@ OP_DEF(rl_r) OP_DEF(rl_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rl_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1030,9 +1000,9 @@ OP_DEF(rr_r) OP_DEF(rr_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.rr_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1049,9 +1019,9 @@ OP_DEF(sla_r) OP_DEF(sla_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.sla_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1068,9 +1038,9 @@ OP_DEF(sra_r) OP_DEF(sra_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.sra_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1087,9 +1057,9 @@ OP_DEF(srl_r) OP_DEF(srl_hlin) { uint32 addr = LeaIHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); uint32 res = ACC.in_8(ACC.srl_8(src)); - Write8(addr, res); + Write1(addr, res); CYCLE_IX(13, 19); } @@ -1108,7 +1078,7 @@ OP_DEF(bit_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); ACC.bit_8(b, data); CYCLE_IX(9, 15); } @@ -1128,9 +1098,9 @@ OP_DEF(res_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); data &= ~(1U << b); - Write8(addr, data); + Write1(addr, data); CYCLE_IX(13, 19); } @@ -1149,16 +1119,16 @@ OP_DEF(set_hlin) { uint b = (op >> 3) & 7; uint32 addr = LeaIHL(); - uint32 data = Read8(addr); + uint32 data = Read1(addr); data |= 1U << b; - Write8(addr, data); + Write1(addr, data); CYCLE_IX(13, 19); } // ED:00rrr000: IN0 r,(n) (HD64*180 only) OP_DEF(in0_r_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 src = ReadIO(n); uint r = op >> 3; reg.r[r] = ACC.in_8(src); @@ -1168,7 +1138,7 @@ OP_DEF(in0_r_n) // ED:00rrr001: OUT0 (n),r (HD64*180 only) OP_DEF(out0_n_r) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 r = op >> 3; WriteIO(n, reg.r[r]); CYCLE(13); @@ -1185,7 +1155,7 @@ OP_DEF(tst_r) // ED:00110000: IN0 F,(n) (HD64*180 only) OP_DEF(in0_f_n) { - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 src = ReadIO(n); ACC.in_8(src); CYCLE(12); @@ -1195,7 +1165,7 @@ OP_DEF(in0_f_n) OP_DEF(tst_hlin) { uint16 addr = reg.GetHL(); - uint32 src = Read8(addr); + uint32 src = Read1(addr); ACC.tst_8(reg.a, src); CYCLE(10); } @@ -1237,8 +1207,8 @@ OP_DEF(ld_nnin_ww) { uint ww = (op >> 4) & 3; uint32 src = GetWW(ww); - uint32 nn = Fetch16(); - Write16(nn, src); + uint32 nn = Fetch2(); + Write2(nn, src); CYCLE(19); } @@ -1253,14 +1223,14 @@ OP_DEF(neg) OP_DEF(retn) { ief1 = ief2; - Jump(Pop16()); + Jump(Pop2()); } // ED:01000110: IM 0 OP_DEF(im_0) { int0mode = 0; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } @@ -1286,8 +1256,8 @@ OP_DEF(adc_hl_ww) OP_DEF(ld_ww_nnin) { uint ww = (op >> 4) & 3; - uint32 nn = Fetch16(); - uint32 src = Read16(nn); + uint32 nn = Fetch2(); + uint32 src = Read2(nn); SetWW(ww, src); CYCLE(18); } @@ -1321,7 +1291,7 @@ OP_DEF(ld_r_a) OP_DEF(im_1) { int0mode = 1; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } @@ -1343,7 +1313,7 @@ OP_DEF(ld_a_i) OP_DEF(im_2) { int0mode = 2; - putlog(1, "IM %d", int0mode); + putlog(1, "IM %u", int0mode); CYCLE(6); } @@ -1364,7 +1334,7 @@ OP_DEF(ld_a_r) // ED:01100100: TST n (HD64*180 only) OP_DEF(tst_n) { - uint32 src = Fetch8(); + uint32 src = Fetch1(); ACC.and_8(reg.a, src); CYCLE(9); } @@ -1381,10 +1351,10 @@ OP_DEF(rrd) // +-------------------+ uint32 hl = reg.GetHL(); - uint32 m = Read8(hl); + uint32 m = Read1(hl); uint32 a = (reg.a & 0xf0) | (m & 0x0f); uint32 b = (reg.a << 4) | (m >> 4); - Write8(hl, b); + Write1(hl, b); reg.a = ACC.in_8(a); CYCLE(16); } @@ -1401,10 +1371,10 @@ OP_DEF(rld) // +-----------+ +---+ uint32 hl = reg.GetHL(); - uint32 m = Read8(hl); + uint32 m = Read1(hl); uint32 a = (reg.a & 0xf0) | (m >> 4); uint32 b = (m << 4) | (reg.a & 0x0f); - Write8(hl, b); + Write1(hl, b); reg.a = ACC.in_8(a); CYCLE(16); } @@ -1423,7 +1393,7 @@ OP_DEF(in_f_c) OP_DEF(tstio_n) { // バスの上位は 0 になる - uint32 n = Fetch8(); + uint32 n = Fetch1(); uint32 dst = ReadIO(reg.c); ACC.tst_8(dst, n); CYCLE(12); @@ -1442,7 +1412,7 @@ void MPU64180Device::ops_otim(int inc) { uint32 hl = reg.GetHL(); - uint32 src = Read8(hl); + uint32 src = Read1(hl); // バスの上位は 0 になる WriteIO(reg.c, src); reg.c += inc; @@ -1503,8 +1473,8 @@ MPU64180Device::ops_ldi(int inc) uint32 de = reg.GetDE(); uint32 bc = reg.GetBC(); - uint32 data = Read8(hl); - Write8(de, data); + uint32 data = Read1(hl); + Write1(de, data); hl += inc; de += inc; bc--; @@ -1532,7 +1502,7 @@ MPU64180Device::ops_cpi(int inc) uint32 hl = reg.GetHL(); uint32 bc = reg.GetBC(); - uint32 src = Read8(hl); + uint32 src = Read1(hl); ACC.sub_8(reg.a, src, true); hl += inc; bc--; @@ -1558,7 +1528,7 @@ MPU64180Device::ops_ini(int inc) // バスの上位には B が出る uint32 addr = reg.GetBC(); uint32 data = ReadIO(addr); - Write8(hl, data); + Write1(hl, data); hl += inc; reg.b--; reg.SetHL(hl); @@ -1581,7 +1551,7 @@ MPU64180Device::ops_outi(int inc) uint32 hl = reg.GetHL(); // バスの上位には B が出る uint32 addr = reg.GetBC(); - uint32 data = Read8(hl); + uint32 data = Read1(hl); WriteIO(addr, data); hl += inc; reg.b--; @@ -1775,10 +1745,10 @@ OP_DEF(cp_ixr) OP_DEF(dd_cb) { // DD CB の場合は 3バイト目が d で、4バイト目が命令語。 - ixd = Fetch8(); + ixd = Fetch1(); // 4バイト目をフェッチ - op = Fetch8(); + op = Fetch1(); // で分岐 switch (op) {