--- nono/hd64180/hd64180ops.cpp	2026/04/29 17:05:30	1.1.1.3
+++ nono/hd64180/hd64180ops.cpp	2026/04/29 17:05:34	1.1.1.4
@@ -2,13 +2,31 @@
 
 #define ACC (*(hd64180acc*)&reg.f)
 
-// LDIR, INDR 等のリピート系命令の雛形。
+// LDIR, LDDR のリピート系命令の雛形。
 // いずれも OP(name) を実行して BC == 0 になるまでこの PC を繰り返すもの。
 // ジャンプする際には 2クロック追加で消費する。
 // フラグも OP(name) が変更した以上にはここでは変更しない。
-#define REPEAT_UNTIL(name)	do {	\
+#define REPEAT_LD(name)	do {	\
 	OP_FUNC(name);	\
-	if (reg.GetBC() != 0) {	\
+	if (reg.f.IsV()) {	\
+		reg.pc -= 2;	\
+		CYCLE(2);	\
+	}	\
+} while (0)
+
+// INIR, INDR, OTIR, OTDR 用。
+#define REPEAT_IO(name)	do {	\
+	OP_FUNC(name);	\
+	if (reg.f.IsZ() == false) {	\
+		reg.pc -= 2;	\
+		CYCLE(2);	\
+	}	\
+} while (0)
+
+// CPIR, CPDR 用。
+#define REPEAT_CP(name)	do {	\
+	OP_FUNC(name);	\
+	if (reg.f.IsZ() == false && reg.f.IsV()) {	\
 		reg.pc -= 2;	\
 		CYCLE(2);	\
 	}	\
@@ -104,14 +122,14 @@ MPU64180Device::SetWW(uint ww, uint32 da
 
 // ここから命令
 
-// 00000000: NOP
+// 00000000: 01R:	NOP
 OP_DEF(nop)
 {
 	CYCLE(3);
 }
 
-//    00ww0001: LD ww,nn
-// DD:00100001: LD IX,nn
+//    00ww0001: 01R:	LD ww,nn
+// DD:00100001: 01R:	LD IX,nn
 OP_DEF(ld_ww_nn)
 {
 	uint32 nn = Fetch2();
@@ -120,7 +138,7 @@ OP_DEF(ld_ww_nn)
 	CYCLE_IX(9, 12);
 }
 
-// 00ww0010: LD (ww),A
+// 00ww0010: 01R:	LD (ww),A
 OP_DEF(ld_wwin_a)
 {
 	uint ww = op >> 4;
@@ -129,8 +147,8 @@ OP_DEF(ld_wwin_a)
 	CYCLE_IX(7, 15);
 }
 
-//    00ww0011: INC ww
-// DD:00100011: INC IX
+//    00ww0011: 01R:	INC ww
+// DD:00100011: 01R:	INC IX
 OP_DEF(inc_ww)
 {
 	uint ww = op >> 4;
@@ -140,7 +158,7 @@ OP_DEF(inc_ww)
 	CYCLE_IX(4, 7);
 }
 
-// 00rrr100: INC r
+// 00rrr100: 01R:	INC r
 OP_DEF(inc_r)
 {
 	uint r = op >> 3;
@@ -148,7 +166,7 @@ OP_DEF(inc_r)
 	CYCLE(4);
 }
 
-// 00rrr101: DEC r
+// 00rrr101: 01R:	DEC r
 OP_DEF(dec_r)
 {
 	uint r = op >> 3;
@@ -156,7 +174,7 @@ OP_DEF(dec_r)
 	CYCLE(4);
 }
 
-// 00rrr110: LD r,n
+// 00rrr110: 01R:	LD r,n
 OP_DEF(ld_r_n)
 {
 	uint r = op >> 3;
@@ -164,14 +182,14 @@ OP_DEF(ld_r_n)
 	CYCLE(6);
 }
 
-// 00000111: RLCA
+// 00000111: 01R:	RLCA
 OP_DEF(rlca)
 {
 	reg.a = ACC.rlc_8(reg.a);
 	CYCLE(3);
 }
 
-// 00001000: EX AF,AF'
+// 00001000: 01R:	EX AF,AF'
 OP_DEF(ex_af_af)
 {
 	uint8 tmpa = reg.a;
@@ -183,8 +201,8 @@ OP_DEF(ex_af_af)
 	CYCLE(4);
 }
 
-//    00ww1001: ADD HL,ww
-// DD:00ww1001: ADD IX,ww
+//    00ww1001: 01R:	ADD HL,ww
+// DD:00ww1001: 01R:	ADD IX,ww
 OP_DEF(add_hl_ww)
 {
 	uint ww = op >> 4;
@@ -195,7 +213,7 @@ OP_DEF(add_hl_ww)
 	CYCLE_IX(7, 10);
 }
 
-// 00ww1010: LD A,(ww)
+// 00ww1010: 01R:	LD A,(ww)
 OP_DEF(ld_a_wwin)
 {
 	uint ww = op >> 4;
@@ -204,8 +222,8 @@ OP_DEF(ld_a_wwin)
 	CYCLE(6);
 }
 
-//    00ww1011: DEC ww
-// DD:00101011: DEC IX
+//    00ww1011: 01R:	DEC ww
+// DD:00101011: 01R:	DEC IX
 OP_DEF(dec_ww)
 {
 	uint ww = op >> 4;
@@ -215,14 +233,14 @@ OP_DEF(dec_ww)
 	CYCLE_IX(4, 7);
 }
 
-// 00001111: RRCA
+// 00001111: 01R:	RRCA
 OP_DEF(rrca)
 {
 	reg.a = ACC.rrc_8(reg.a);
 	CYCLE(3);
 }
 
-// 00010000: DJNZ n
+// 00010000: 01R:	DJNZ n
 OP_DEF(djnz)
 {
 	int8 n = Fetch1();
@@ -235,14 +253,14 @@ OP_DEF(djnz)
 	}
 }
 
-// 00010111: RLA
+// 00010111: 01R:	RLA
 OP_DEF(rla)
 {
 	reg.a = ACC.rl_8(reg.a);
 	CYCLE(3);
 }
 
-// 00011000: JR n
+// 00011000: 01R:	JR n
 OP_DEF(jr)
 {
 	int8 n = Fetch1();
@@ -250,14 +268,14 @@ OP_DEF(jr)
 	CYCLE(8);
 }
 
-// 00011111: RRA
+// 00011111: 01R:	RRA
 OP_DEF(rra)
 {
 	reg.a = ACC.rr_8(reg.a);
 	CYCLE(3);
 }
 
-// 00100000: JR NZ,n
+// 00100000: 01R:	JR NZ,n
 OP_DEF(jr_nz)
 {
 	int8 n = Fetch1();
@@ -269,8 +287,8 @@ OP_DEF(jr_nz)
 	}
 }
 
-//    00100010: LD (nn),HL
-// DD:00100010: LD (nn),IX
+//    00100010: 01R:	LD (nn),HL
+// DD:00100010: 01R:	LD (nn),IX
 OP_DEF(ld_nnin_hl)
 {
 	uint32 nn = Fetch2();
@@ -278,14 +296,14 @@ OP_DEF(ld_nnin_hl)
 	CYCLE_IX(16, 19);
 }
 
-// 00100111: DAA
+// 00100111: 01R:	DAA
 OP_DEF(daa)
 {
 	reg.a = ACC.daa_8(reg.a);
 	CYCLE(4);
 }
 
-// 00101000: JR Z,n
+// 00101000: 01R:	JR Z,n
 OP_DEF(jr_z)
 {
 	int8 n = Fetch1();
@@ -297,8 +315,8 @@ OP_DEF(jr_z)
 	}
 }
 
-//    00101010: LD HL,(nn)
-// DD:00101010: LD IX,(nn)
+//    00101010: 01R:	LD HL,(nn)
+// DD:00101010: 01R:	LD IX,(nn)
 OP_DEF(ld_hl_nnin)
 {
 	uint32 nn = Fetch2();
@@ -307,7 +325,7 @@ OP_DEF(ld_hl_nnin)
 	CYCLE_IX(15, 18);
 }
 
-// 00101111: CPL
+// 00101111: 01R:	CPL
 OP_DEF(cpl)
 {
 	reg.a = ~reg.a;
@@ -316,7 +334,7 @@ OP_DEF(cpl)
 	CYCLE(3);
 }
 
-// 00110000: JR NC,n
+// 00110000: 01R:	JR NC,n
 OP_DEF(jr_nc)
 {
 	int8 n = Fetch1();
@@ -328,7 +346,7 @@ OP_DEF(jr_nc)
 	}
 }
 
-// 00110010: LD (nn),A
+// 00110010: 01R:	LD (nn),A
 OP_DEF(ld_nnin_a)
 {
 	uint32 addr = Fetch2();
@@ -336,8 +354,8 @@ OP_DEF(ld_nnin_a)
 	CYCLE(13);
 }
 
-//    00110100: INC (HL)
-// DD:00110100: INC (IX+d)
+//    00110100: 01R:	INC (HL)
+// DD:00110100: 01R:	INC (IX+d)
 OP_DEF(inc_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -347,8 +365,8 @@ OP_DEF(inc_hlin)
 	CYCLE_IX(10, 18);
 }
 
-//    00110101: DEC (HL)
-// DD:00110101: DEC (IX+d)
+//    00110101: 01R:	DEC (HL)
+// DD:00110101: 01R:	DEC (IX+d)
 OP_DEF(dec_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -358,8 +376,8 @@ OP_DEF(dec_hlin)
 	CYCLE_IX(10, 18);
 }
 
-//    00110110: LD (HL),n
-// DD:00110110: LD (IX+d),n
+//    00110110: 01R:	LD (HL),n
+// DD:00110110: 01R:	LD (IX+d),n
 OP_DEF(ld_hlin_n)
 {
 	uint32 addr = LeaIHL();
@@ -368,7 +386,7 @@ OP_DEF(ld_hlin_n)
 	CYCLE_IX(9, 15);
 }
 
-// 00110111: SCF
+// 00110111: 01R:	SCF
 OP_DEF(scf)
 {
 	reg.f.SetC(true);
@@ -377,7 +395,7 @@ OP_DEF(scf)
 	CYCLE(3);
 }
 
-// 00111000: JR C,n
+// 00111000: 01R:	JR C,n
 OP_DEF(jr_c)
 {
 	int8 n = Fetch1();
@@ -389,7 +407,7 @@ OP_DEF(jr_c)
 	}
 }
 
-// 00111010: LD A,(nn)
+// 00111010: 01R:	LD A,(nn)
 OP_DEF(ld_a_nnin)
 {
 	uint32 nn = Fetch2();
@@ -397,7 +415,7 @@ OP_DEF(ld_a_nnin)
 	CYCLE(12);
 }
 
-// 00111111: CCF
+// 00111111: 01R:	CCF
 OP_DEF(ccf)
 {
 	reg.f.SetC(!reg.f.IsC());
@@ -406,7 +424,7 @@ OP_DEF(ccf)
 	CYCLE(3);
 }
 
-// 01rrrsss: LD r,s
+// 01rrrsss: 01R:	LD r,s
 OP_DEF(ld_r_s)
 {
 	uint d = (op >> 3) & 7;
@@ -415,8 +433,8 @@ OP_DEF(ld_r_s)
 	CYCLE(4);
 }
 
-//    01rrr110: LD r,(HL)
-// DD:01rrr110: LD r,(IX+d)
+//    01rrr110: 01R:	LD r,(HL)
+// DD:01rrr110: 01R:	LD r,(IX+d)
 OP_DEF(ld_r_hlin)
 {
 	uint d = (op >> 3) & 7;
@@ -425,8 +443,8 @@ OP_DEF(ld_r_hlin)
 	CYCLE_IX(6, 14);
 }
 
-//    01110sss: LD (HL),s
-// DD:01110sss: LD (IX+d),s
+//    01110sss: 01R:	LD (HL),s
+// DD:01110sss: 01R:	LD (IX+d),s
 OP_DEF(ld_hlin_s)
 {
 	uint s = op & 7;
@@ -435,7 +453,7 @@ OP_DEF(ld_hlin_s)
 	CYCLE_IX(7, 15);
 }
 
-// 01110110: HALT
+// 01110110: 01R:	HALT
 OP_DEF(halt)
 {
 	opmode = OpMode::Halt;
@@ -443,7 +461,7 @@ OP_DEF(halt)
 	CYCLE(3);
 }
 
-// 10000rrr: ADD A,r
+// 10000rrr: 01R:	ADD A,r
 OP_DEF(add_a_r)
 {
 	uint r = op & 7;
@@ -451,8 +469,8 @@ OP_DEF(add_a_r)
 	CYCLE(4);
 }
 
-//    10000110: ADD A,(HL)
-// DD:10000110: ADD A,(IX+d)
+//    10000110: 01R:	ADD A,(HL)
+// DD:10000110: 01R:	ADD A,(IX+d)
 OP_DEF(add_a_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -461,7 +479,7 @@ OP_DEF(add_a_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10001rrr: ADC A,r
+// 10001rrr: 01R:	ADC A,r
 OP_DEF(adc_a_r)
 {
 	uint r = op & 7;
@@ -469,8 +487,8 @@ OP_DEF(adc_a_r)
 	CYCLE(4);
 }
 
-//    10001110: ADC A,(HL)
-// DD:10001110: ADC A,(IX+d)
+//    10001110: 01R:	ADC A,(HL)
+// DD:10001110: 01R:	ADC A,(IX+d)
 OP_DEF(adc_a_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -479,7 +497,7 @@ OP_DEF(adc_a_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10010rrr: SUB r
+// 10010rrr: 01R:	SUB r
 OP_DEF(sub_r)
 {
 	uint r = op & 7;
@@ -487,8 +505,8 @@ OP_DEF(sub_r)
 	CYCLE(4);
 }
 
-//    10010110: SUB (HL)
-// DD:10010110: SUB (IX+d)
+//    10010110: 01R:	SUB (HL)
+// DD:10010110: 01R:	SUB (IX+d)
 OP_DEF(sub_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -497,7 +515,7 @@ OP_DEF(sub_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10011rrr: SBC A,r
+// 10011rrr: 01R:	SBC A,r
 OP_DEF(sbc_a_r)
 {
 	uint r = op & 7;
@@ -505,8 +523,8 @@ OP_DEF(sbc_a_r)
 	CYCLE(4);
 }
 
-//    10011110: SBC A,(HL)
-// DD:10011110: SBC A,(IX+d)
+//    10011110: 01R:	SBC A,(HL)
+// DD:10011110: 01R:	SBC A,(IX+d)
 OP_DEF(sbc_a_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -515,7 +533,7 @@ OP_DEF(sbc_a_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10100rrr: AND r
+// 10100rrr: 01R:	AND r
 OP_DEF(and_r)
 {
 	uint r = op & 7;
@@ -523,8 +541,8 @@ OP_DEF(and_r)
 	CYCLE(4);
 }
 
-//    10100110: AND (HL)
-// DD:10100110: AND (IX+d)
+//    10100110: 01R:	AND (HL)
+// DD:10100110: 01R:	AND (IX+d)
 OP_DEF(and_hlin)
 {
 	uint16 addr = LeaIHL();
@@ -533,7 +551,7 @@ OP_DEF(and_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10101rrr: XOR r
+// 10101rrr: 01R:	XOR r
 OP_DEF(xor_r)
 {
 	uint r = op & 7;
@@ -541,8 +559,8 @@ OP_DEF(xor_r)
 	CYCLE(4);
 }
 
-//    10101110: XOR (HL)
-// DD:10101110: XOR (IX+d)
+//    10101110: 01R:	XOR (HL)
+// DD:10101110: 01R:	XOR (IX+d)
 OP_DEF(xor_hlin)
 {
 	uint16 addr = LeaIHL();
@@ -551,7 +569,7 @@ OP_DEF(xor_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10110rrr: OR r
+// 10110rrr: 01R:	OR r
 OP_DEF(or_r)
 {
 	uint r = op & 7;
@@ -559,8 +577,8 @@ OP_DEF(or_r)
 	CYCLE(4);
 }
 
-//    10110110: OR (HL)
-// DD:10110110: OR (IX+d)
+//    10110110: 01R:	OR (HL)
+// DD:10110110: 01R:	OR (IX+d)
 OP_DEF(or_hlin)
 {
 	uint16 addr = LeaIHL();
@@ -569,7 +587,7 @@ OP_DEF(or_hlin)
 	CYCLE_IX(6, 14);
 }
 
-// 10111rrr: CP r
+// 10111rrr: 01R:	CP r
 OP_DEF(cp_r)
 {
 	uint r = op & 7;
@@ -577,8 +595,8 @@ OP_DEF(cp_r)
 	CYCLE(4);
 }
 
-//    10111110: CP (HL)
-// DD:10111110: CP (IX+d)
+//    10111110: 01R:	CP (HL)
+// DD:10111110: 01R:	CP (IX+d)
 OP_DEF(cp_hlin)
 {
 	uint16 addr = LeaIHL();
@@ -594,7 +612,7 @@ MPU64180Device::ops_ret()
 	Jump(addr);
 }
 
-// 11fff000: RET f
+// 11fff000: 01R:	RET f
 OP_DEF(ret_f)
 {
 	uint fff = (op >> 3) & 7;
@@ -606,8 +624,8 @@ OP_DEF(ret_f)
 	}
 }
 
-//    11zz0001: POP zz
-// DD:11100001: POP IX
+//    11zz0001: 01R:	POP zz
+// DD:11100001: 01R:	POP IX
 OP_DEF(pop_zz)
 {
 	// ここでは zz のうち BC, DE, HL のみなので ww が使える
@@ -617,7 +635,7 @@ OP_DEF(pop_zz)
 	CYCLE_IX(9, 12);
 }
 
-// 11fff010: JP f,nn
+// 11fff010: 01R:	JP f,nn
 OP_DEF(jp_f_nn)
 {
 	uint fff = (op >> 3) & 7;
@@ -630,7 +648,7 @@ OP_DEF(jp_f_nn)
 	}
 }
 
-// 11000011: JP nn
+// 11000011: 01R:	JP nn
 OP_DEF(jp_nn)
 {
 	uint32 addr = Fetch2();
@@ -638,7 +656,7 @@ OP_DEF(jp_nn)
 	CYCLE(9);
 }
 
-// 11fff100: CALL f,nn
+// 11fff100: 01R:	CALL f,nn
 OP_DEF(call_f_nn)
 {
 	uint fff = (op >> 3) & 7;
@@ -652,8 +670,8 @@ OP_DEF(call_f_nn)
 	}
 }
 
-//    11zz0101: PUSH zz
-// DD:11100101: PUSH IX
+//    11zz0101: 01R:	PUSH zz
+// DD:11100101: 01R:	PUSH IX
 OP_DEF(push_zz)
 {
 	// ここでは zz のうち BC, DE, HL のみなので ww が使える
@@ -663,7 +681,7 @@ OP_DEF(push_zz)
 	CYCLE_IX(11, 14);
 }
 
-// 11000110: ADD A,n
+// 11000110: 01R:	ADD A,n
 OP_DEF(add_a_n)
 {
 	uint32 n = Fetch1();
@@ -671,7 +689,7 @@ OP_DEF(add_a_n)
 	CYCLE(6);
 }
 
-// 11vvv111: RST v
+// 11vvv111: 01R:	RST v
 OP_DEF(rst)
 {
 	Push2(reg.pc);
@@ -680,14 +698,14 @@ OP_DEF(rst)
 	CYCLE(11);
 }
 
-// 11001001: RET
+// 11001001: 01R:	RET
 OP_DEF(ret)
 {
 	ops_ret();
 	CYCLE(9);
 }
 
-// 11001011: op_CB
+// 11001011: 01R:	op_CB
 OP_DEF(cb)
 {
 	// 2バイト目をフェッチ
@@ -701,7 +719,7 @@ OP_DEF(cb)
 	}
 }
 
-// 11001101: CALL nn
+// 11001101: 01R:	CALL nn
 OP_DEF(call)
 {
 	uint16 nn = Fetch2();
@@ -710,7 +728,7 @@ OP_DEF(call)
 	CYCLE(16);
 }
 
-// 11001110: ADC A,n
+// 11001110: 01R:	ADC A,n
 OP_DEF(adc_a_n)
 {
 	uint32 n = Fetch1();
@@ -718,7 +736,7 @@ OP_DEF(adc_a_n)
 	CYCLE(6);
 }
 
-// 11010011: OUT (n),A
+// 11010011: 01R:	OUT (n),A
 OP_DEF(out_n_a)
 {
 	uint32 n = Fetch1();
@@ -728,7 +746,7 @@ OP_DEF(out_n_a)
 	CYCLE(10);
 }
 
-// 11010110: SUB n
+// 11010110: 01R:	SUB n
 OP_DEF(sub_n)
 {
 	uint32 n = Fetch1();
@@ -736,7 +754,7 @@ OP_DEF(sub_n)
 	CYCLE(6);
 }
 
-// 11011001: EXX
+// 11011001: 01R:	EXX
 OP_DEF(exx)
 {
 	uint8 tmpb = reg.b;
@@ -760,7 +778,7 @@ OP_DEF(exx)
 	CYCLE(3);
 }
 
-// 11011011: IN A,(n)
+// 11011011: 01R:	IN A,(n)
 OP_DEF(in_a_n)
 {
 	uint32 n = Fetch1();
@@ -787,13 +805,13 @@ MPU64180Device::ops_ddfd(ixiy_t xy)
 	}
 }
 
-// 11011101: op_DD
+// 11011101: 01R:	op_DD
 OP_DEF(dd)
 {
 	ops_ddfd(USE_IX);
 }
 
-// 11011110: SBC A,n
+// 11011110: 01R:	SBC A,n
 OP_DEF(sbc_a_n)
 {
 	uint32 n = Fetch1();
@@ -801,8 +819,8 @@ OP_DEF(sbc_a_n)
 	CYCLE(6);
 }
 
-//    11100011: EX (SP),HL
-// DD:11100011: EX (SP),IX
+//    11100011: 01R:	EX (SP),HL
+// DD:11100011: 01R:	EX (SP),IX
 OP_DEF(ex_sp_hl)
 {
 	uint32 tmp = Read2(reg.sp);
@@ -811,7 +829,7 @@ OP_DEF(ex_sp_hl)
 	CYCLE_IX(16, 19);
 }
 
-// 11100110: AND n
+// 11100110: 01R:	AND n
 OP_DEF(and_n)
 {
 	uint32 src = Fetch1();
@@ -819,15 +837,15 @@ OP_DEF(and_n)
 	CYCLE(6);
 }
 
-//    11101001: JP (HL)
-// DD:11101001: JP (IX)
+//    11101001: 01R:	JP (HL)
+// DD:11101001: 01R:	JP (IX)
 OP_DEF(jp_hl)
 {
 	Jump(GetIHL());
 	CYCLE_IX(3, 6);
 }
 
-// 11101011: EX DE,HL
+// 11101011: 01R:	EX DE,HL
 OP_DEF(ex_de_hl)
 {
 	uint16 tmp = reg.GetDE();
@@ -836,7 +854,7 @@ OP_DEF(ex_de_hl)
 	CYCLE(3);
 }
 
-// 11101101: op_ED
+// 11101101: 01R:	op_ED
 OP_DEF(ed)
 {
 	op = Fetch1();
@@ -849,7 +867,7 @@ OP_DEF(ed)
 	}
 }
 
-// 11101110: XOR n
+// 11101110: 01R:	XOR n
 OP_DEF(xor_n)
 {
 	uint32 src = Fetch1();
@@ -857,7 +875,7 @@ OP_DEF(xor_n)
 	CYCLE(6);
 }
 
-// 11110001: POP AF
+// 11110001: 01R:	POP AF
 OP_DEF(pop_af)
 {
 	uint16 data = Pop2();
@@ -866,7 +884,7 @@ OP_DEF(pop_af)
 	CYCLE(9);
 }
 
-// 11110011: DI
+// 11110011: 01R:	DI
 OP_DEF(di)
 {
 	ief1 = false;
@@ -878,7 +896,7 @@ OP_DEF(di)
 	CYCLE(3);
 }
 
-// 11110101: PUSH AF
+// 11110101: 01R:	PUSH AF
 OP_DEF(push_af)
 {
 	uint16 data;
@@ -888,7 +906,7 @@ OP_DEF(push_af)
 	CYCLE(11);
 }
 
-// 11110110: OR n
+// 11110110: 01R:	OR n
 OP_DEF(or_n)
 {
 	uint32 src = Fetch1();
@@ -896,15 +914,15 @@ OP_DEF(or_n)
 	CYCLE(6);
 }
 
-//    11111001: LD SP,HL
-// DD:11111001: LD SP,IX
+//    11111001: 01R:	LD SP,HL
+// DD:11111001: 01R:	LD SP,IX
 OP_DEF(ld_sp_hl)
 {
 	reg.sp = GetIHL();
 	CYCLE_IX(4, 7);
 }
 
-// 11111011: EI
+// 11111011: 01R:	EI
 OP_DEF(ei)
 {
 	ief1 = true;
@@ -916,13 +934,13 @@ OP_DEF(ei)
 	CYCLE(3);
 }
 
-// 11111101: op_FD
+// 11111101: 01R:	op_FD
 OP_DEF(fd)
 {
 	ops_ddfd(USE_IY);
 }
 
-// 11111110: CP n
+// 11111110: 01R:	CP n
 OP_DEF(cp_n)
 {
 	uint32 n = Fetch1();
@@ -930,7 +948,7 @@ OP_DEF(cp_n)
 	CYCLE(6);
 }
 
-// CB:00000rrr: RLC r
+// CB:00000rrr: 01R:	RLC r
 OP_DEF(rlc_r)
 {
 	uint r = op & 7;
@@ -938,8 +956,8 @@ OP_DEF(rlc_r)
 	CYCLE(7);
 }
 
-//    CB:00000110: RLC (HL)
-// DD_CB:00000110: RLC (IX+d)
+//    CB:00000110: 01R:	RLC (HL)
+// DD_CB:00000110: 01R:	RLC (IX+d)
 OP_DEF(rlc_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -949,7 +967,7 @@ OP_DEF(rlc_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00001rrr: RRC r
+// CB:00001rrr: 01R:	RRC r
 OP_DEF(rrc_r)
 {
 	uint r = op & 7;
@@ -957,8 +975,8 @@ OP_DEF(rrc_r)
 	CYCLE(7);
 }
 
-//    CB:00001110: RRC (HL)
-// DD_CB:00001110: RRC (IX+d)
+//    CB:00001110: 01R:	RRC (HL)
+// DD_CB:00001110: 01R:	RRC (IX+d)
 OP_DEF(rrc_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -968,7 +986,7 @@ OP_DEF(rrc_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00010rrr: RL r
+// CB:00010rrr: 01R:	RL r
 OP_DEF(rl_r)
 {
 	uint r = op & 7;
@@ -976,8 +994,8 @@ OP_DEF(rl_r)
 	CYCLE(7);
 }
 
-//    CB:00010110: RL (HL)
-// DD_CB:00010110: RL (IX+d)
+//    CB:00010110: 01R:	RL (HL)
+// DD_CB:00010110: 01R:	RL (IX+d)
 OP_DEF(rl_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -987,7 +1005,7 @@ OP_DEF(rl_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00011rrr: RR r
+// CB:00011rrr: 01R:	RR r
 OP_DEF(rr_r)
 {
 	uint r = op & 7;
@@ -995,8 +1013,8 @@ OP_DEF(rr_r)
 	CYCLE(7);
 }
 
-//    CB:00011110: RR (HL)
-// DD_CB:00011110: RR (IX+d)
+//    CB:00011110: 01R:	RR (HL)
+// DD_CB:00011110: 01R:	RR (IX+d)
 OP_DEF(rr_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -1006,7 +1024,7 @@ OP_DEF(rr_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00100rrr: SLA r
+// CB:00100rrr: 01R:	SLA r
 OP_DEF(sla_r)
 {
 	uint r = op & 7;
@@ -1014,8 +1032,8 @@ OP_DEF(sla_r)
 	CYCLE(7);
 }
 
-//    CB:00100110: SLA (HL)
-// DD_CB:00100110: SLA (IX+d)
+//    CB:00100110: 01R:	SLA (HL)
+// DD_CB:00100110: 01R:	SLA (IX+d)
 OP_DEF(sla_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -1025,7 +1043,7 @@ OP_DEF(sla_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00101rrr: SRA r
+// CB:00101rrr: 01R:	SRA r
 OP_DEF(sra_r)
 {
 	uint r = op & 7;
@@ -1033,8 +1051,8 @@ OP_DEF(sra_r)
 	CYCLE(7);
 }
 
-//    CB:00101110: SRA (HL)
-// DD_CB:00101110: SRA (IX+d)
+//    CB:00101110: 01R:	SRA (HL)
+// DD_CB:00101110: 01R:	SRA (IX+d)
 OP_DEF(sra_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -1044,7 +1062,38 @@ OP_DEF(sra_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:00111rrr: SRL r
+// CB:00110rrr: Z--:	SLL
+OP_DEF(sll_r)
+{
+	if (1) {
+		op_illegal(2);
+	} else {
+		uint r = op & 7;
+		reg.r[r] = ACC.in_8(ACC.sll_8(reg.r[r]));
+		CYCLE(7);
+	}
+}
+
+//    CB:00110110: Z--:	SLL (HL)
+// DD_CB:00110110: Z--:	SLL (IX+d)
+OP_DEF(sll_hlin)
+{
+	if (1) {
+		if (ixiy == USE_HL) {
+			op_illegal(2);
+		} else {
+			op_illegal(3);
+		}
+	} else {
+		uint32 addr = LeaIHL();
+		uint32 src = Read1(addr);
+		uint32 res = ACC.in_8(ACC.sll_8(src));
+		Write1(addr, res);
+		CYCLE_IX(13, 19);
+	}
+}
+
+// CB:00111rrr: 01R:	SRL r
 OP_DEF(srl_r)
 {
 	uint r = op & 7;
@@ -1052,8 +1101,8 @@ OP_DEF(srl_r)
 	CYCLE(7);
 }
 
-//    CB:00111110: SRL (HL)
-// DD_CB:00111110: SRL (IX+d)
+//    CB:00111110: 01R:	SRL (HL)
+// DD_CB:00111110: 01R:	SRL (IX+d)
 OP_DEF(srl_hlin)
 {
 	uint32 addr = LeaIHL();
@@ -1063,7 +1112,7 @@ OP_DEF(srl_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:01bbbrrr: BIT b,r
+// CB:01bbbrrr: 01R:	BIT b,r
 OP_DEF(bit_r)
 {
 	uint b = (op >> 3) & 7;
@@ -1072,8 +1121,8 @@ OP_DEF(bit_r)
 	CYCLE(6);
 }
 
-//    CB:01bbb110: BIT b,(HL)
-// DD_CB:01bbb110: BIT b,(IX+d)
+//    CB:01bbb110: 01R:	BIT b,(HL)
+// DD_CB:01bbb110: 01R:	BIT b,(IX+d)
 OP_DEF(bit_hlin)
 {
 	uint b = (op >> 3) & 7;
@@ -1083,7 +1132,7 @@ OP_DEF(bit_hlin)
 	CYCLE_IX(9, 15);
 }
 
-// CB:10bbbrrr: RES b,r
+// CB:10bbbrrr: 01R:	RES b,r
 OP_DEF(res_r)
 {
 	uint b = (op >> 3) & 7;
@@ -1092,8 +1141,8 @@ OP_DEF(res_r)
 	CYCLE(7);
 }
 
-//    CB:10bbb110: RES b,(HL)
-// DD_CB:10bbb110: RES b,(IX+d)
+//    CB:10bbb110: 01R:	RES b,(HL)
+// DD_CB:10bbb110: 01R:	RES b,(IX+d)
 OP_DEF(res_hlin)
 {
 	uint b = (op >> 3) & 7;
@@ -1104,7 +1153,7 @@ OP_DEF(res_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// CB:11bbbrrr: SET b,r
+// CB:11bbbrrr: 01R:	SET b,r
 OP_DEF(set_r)
 {
 	uint b = (op >> 3) & 7;
@@ -1113,8 +1162,8 @@ OP_DEF(set_r)
 	CYCLE(7);
 }
 
-//    CB:11bbb110: SET b,(HL)
-// DD_CB:11bbb110: SET b,(IX+d)
+//    CB:11bbb110: 01R:	SET b,(HL)
+// DD_CB:11bbb110: 01R:	SET b,(IX+d)
 OP_DEF(set_hlin)
 {
 	uint b = (op >> 3) & 7;
@@ -1125,7 +1174,7 @@ OP_DEF(set_hlin)
 	CYCLE_IX(13, 19);
 }
 
-// ED:00rrr000: IN0 r,(n)	(HD64*180 only)
+// ED:00rrr000: -1-:	IN0 r,(n)
 OP_DEF(in0_r_n)
 {
 	uint32 n = Fetch1();
@@ -1135,7 +1184,7 @@ OP_DEF(in0_r_n)
 	CYCLE(12);
 }
 
-// ED:00rrr001: OUT0 (n),r	(HD64*180 only)
+// ED:00rrr001: -1-:	OUT0 (n),r
 OP_DEF(out0_n_r)
 {
 	uint32 n = Fetch1();
@@ -1144,7 +1193,7 @@ OP_DEF(out0_n_r)
 	CYCLE(13);
 }
 
-// ED:00rrr100: TST r	(HD64*180 only)
+// ED:00rrr100: -1-:	TST r
 OP_DEF(tst_r)
 {
 	uint r = op & 7;
@@ -1152,7 +1201,7 @@ OP_DEF(tst_r)
 	CYCLE(7);
 }
 
-// ED:00110000: IN0 F,(n)	(HD64*180 only)
+// ED:00110000: -1-:	IN0 F,(n)
 OP_DEF(in0_f_n)
 {
 	uint32 n = Fetch1();
@@ -1161,7 +1210,7 @@ OP_DEF(in0_f_n)
 	CYCLE(12);
 }
 
-// ED:00110100: TST (HL)	(HD64*180 only)
+// ED:00110100: -1-:	TST (HL)
 OP_DEF(tst_hlin)
 {
 	uint16 addr = reg.GetHL();
@@ -1170,7 +1219,7 @@ OP_DEF(tst_hlin)
 	CYCLE(10);
 }
 
-// ED:01rrr000: IN r,(C)
+// ED:01rrr000: 01R:	IN r,(C)
 OP_DEF(in_r_c)
 {
 	uint r = (op >> 3) & 7;
@@ -1181,7 +1230,7 @@ OP_DEF(in_r_c)
 	CYCLE(9);
 }
 
-// ED:01rrr001: OUT (C),r
+// ED:01rrr001: 01R:	OUT (C),r
 OP_DEF(out_c_r)
 {
 	uint r = (op >> 3) & 7;
@@ -1191,7 +1240,7 @@ OP_DEF(out_c_r)
 	CYCLE(10);
 }
 
-// ED:01ww0010: SBC HL,ww
+// ED:01ww0010: 01R:	SBC HL,ww
 OP_DEF(sbc_hl_ww)
 {
 	uint ww = (op >> 4) & 3;
@@ -1202,7 +1251,7 @@ OP_DEF(sbc_hl_ww)
 	CYCLE(10);
 }
 
-// ED:01ww0011: LD (nn),ww
+// ED:01ww0011: 01R:	LD (nn),ww
 OP_DEF(ld_nnin_ww)
 {
 	uint ww = (op >> 4) & 3;
@@ -1212,21 +1261,21 @@ OP_DEF(ld_nnin_ww)
 	CYCLE(19);
 }
 
-// ED:01000100: NEG
+// ED:01000100: 01R:	NEG
 OP_DEF(neg)
 {
 	reg.a = ACC.sub_8(0, reg.a);
 	CYCLE(6);
 }
 
-// ED:01000101: RETN
+// ED:01000101: 01R:	RETN
 OP_DEF(retn)
 {
 	ief1 = ief2;
 	Jump(Pop2());
 }
 
-// ED:01000110: IM 0
+// ED:01000110: 01R:	IM 0
 OP_DEF(im_0)
 {
 	int0mode = 0;
@@ -1234,14 +1283,14 @@ OP_DEF(im_0)
 	CYCLE(6);
 }
 
-// ED:01000111: LD I,A
+// ED:01000111: 01R:	LD I,A
 OP_DEF(ld_i_a)
 {
 	reg_i = reg.a;
 	CYCLE(6);
 }
 
-// ED:01ww1010: ADC HL,ww
+// ED:01ww1010: 01R:	ADC HL,ww
 OP_DEF(adc_hl_ww)
 {
 	uint ww = (op >> 4) & 3;
@@ -1252,7 +1301,7 @@ OP_DEF(adc_hl_ww)
 	CYCLE(10);
 }
 
-// ED:01ww1011: LD ww,(nn)
+// ED:01ww1011: 01R:	LD ww,(nn)
 OP_DEF(ld_ww_nnin)
 {
 	uint ww = (op >> 4) & 3;
@@ -1262,7 +1311,7 @@ OP_DEF(ld_ww_nnin)
 	CYCLE(18);
 }
 
-// ED:01ww1100: MLT ww	(HD64*180 only)
+// ED:01ww1100: -1-:	MLT ww
 OP_DEF(mlt)
 {
 	uint ww = (op >> 4) & 3;
@@ -1273,21 +1322,21 @@ OP_DEF(mlt)
 	CYCLE(17);
 }
 
-// ED:01001101: RETI
+// ED:01001101: 01R:	RETI
 OP_DEF(reti)
 {
 	ops_ret();
 	CYCLE(12);
 }
 
-// ED:01001111: LD R,A
+// ED:01001111: 01R:	LD R,A
 OP_DEF(ld_r_a)
 {
 	reg_r = reg.a;
 	CYCLE(6);
 }
 
-// ED:01010110: IM 1
+// ED:01010110: 01R:	IM 1
 OP_DEF(im_1)
 {
 	int0mode = 1;
@@ -1295,7 +1344,7 @@ OP_DEF(im_1)
 	CYCLE(6);
 }
 
-// ED:01010111: LD A,I
+// ED:01010111: 01R:	LD A,I
 OP_DEF(ld_a_i)
 {
 	reg.a = ACC.ld_ir8(reg_i);
@@ -1309,7 +1358,7 @@ OP_DEF(ld_a_i)
 	CYCLE(6);
 }
 
-// ED:01011110: IM 2
+// ED:01011110: 01R:	IM 2
 OP_DEF(im_2)
 {
 	int0mode = 2;
@@ -1317,7 +1366,7 @@ OP_DEF(im_2)
 	CYCLE(6);
 }
 
-// ED:01011111: LD A,R
+// ED:01011111: 01R:	LD A,R
 OP_DEF(ld_a_r)
 {
 	reg.a = ACC.ld_ir8(GetR());
@@ -1331,7 +1380,7 @@ OP_DEF(ld_a_r)
 	CYCLE(6);
 }
 
-// ED:01100100: TST n	(HD64*180 only)
+// ED:01100100: -1-:	TST n
 OP_DEF(tst_n)
 {
 	uint32 src = Fetch1();
@@ -1339,7 +1388,7 @@ OP_DEF(tst_n)
 	CYCLE(9);
 }
 
-// ED:01100111: RRD
+// ED:01100111: 01R:	RRD
 OP_DEF(rrd)
 {
 	//            +-----------+   +---+
@@ -1359,7 +1408,7 @@ OP_DEF(rrd)
 	CYCLE(16);
 }
 
-// ED:01101111: RLD
+// ED:01101111: 01R:	RLD
 OP_DEF(rld)
 {
 	//            +-------------------+
@@ -1379,7 +1428,7 @@ OP_DEF(rld)
 	CYCLE(16);
 }
 
-// ED:01110000: IN F,(C)
+// ED:01110000: 01R:	IN F,(C)
 OP_DEF(in_f_c)
 {
 	// バスの上位には B が出る
@@ -1389,7 +1438,7 @@ OP_DEF(in_f_c)
 	CYCLE(9);
 }
 
-// ED:01110100: TSTIO n	(HD64*180 only)
+// ED:01110100: -1-:	TSTIO n
 OP_DEF(tstio_n)
 {
 	// バスの上位は 0 になる
@@ -1399,7 +1448,7 @@ OP_DEF(tstio_n)
 	CYCLE(12);
 }
 
-// ED:01110110: SLP	(HD64*180 only)
+// ED:01110110: -1-:	SLP
 OP_DEF(slp)
 {
 	putlog(0, "SLP (NOT IMPLEMENTED)");
@@ -1422,13 +1471,13 @@ MPU64180Device::ops_otim(int inc)
 	CYCLE(14);
 }
 
-// ED:10000011: OTIM	(HD64*180 only)
+// ED:10000011: -1-:	OTIM
 OP_DEF(otim)
 {
 	ops_otim(+1);
 }
 
-// ED:10001011: OTDM	(HD64*180 only)
+// ED:10001011: -1-:	OTDM
 OP_DEF(otdm)
 {
 	ops_otim(-1);
@@ -1451,14 +1500,14 @@ MPU64180Device::ops_otmr_until()
 	}
 }
 
-// ED:10010011: OTIMR	(HD64*180 only)
+// ED:10010011: -1-:	OTIMR
 OP_DEF(otimr)
 {
 	OP_FUNC(otim);
 	ops_otmr_until();
 }
 
-// ED:10011011: OTDMR	(HD64*180 only)
+// ED:10011011: -1-:	OTDMR
 OP_DEF(otdmr)
 {
 	OP_FUNC(otdm);
@@ -1489,7 +1538,7 @@ MPU64180Device::ops_ldi(int inc)
 	CYCLE(12);
 }
 
-// ED:10100000: LDI
+// ED:10100000: 01R:	LDI
 OP_DEF(ldi)
 {
 	ops_ldi(+1);
@@ -1514,7 +1563,7 @@ MPU64180Device::ops_cpi(int inc)
 	CYCLE(12);
 }
 
-// ED:10100001: CPI
+// ED:10100001: 01R:	CPI
 OP_DEF(cpi)
 {
 	ops_cpi(+1);
@@ -1538,7 +1587,7 @@ MPU64180Device::ops_ini(int inc)
 	CYCLE(12);
 }
 
-// ED:10100010: INI
+// ED:10100010: 01R:	INI
 OP_DEF(ini)
 {
 	ops_ini(+1);
@@ -1562,103 +1611,103 @@ MPU64180Device::ops_outi(int inc)
 	CYCLE(12);
 }
 
-// ED:10100011: OUTI
+// ED:10100011: 01R:	OUTI
 OP_DEF(outi)
 {
 	ops_outi(+1);
 }
 
-// ED:10101000: LDD
+// ED:10101000: 01R:	LDD
 OP_DEF(ldd)
 {
 	ops_ldi(-1);
 }
 
-// ED:10101001: CPD
+// ED:10101001: 01R:	CPD
 OP_DEF(cpd)
 {
 	ops_cpi(-1);
 }
 
-// ED:10101010: IND
+// ED:10101010: 01R:	IND
 OP_DEF(ind)
 {
 	ops_ini(-1);
 }
 
-// ED:10101011: OUTD
+// ED:10101011: 01R:	OUTD
 OP_DEF(outd)
 {
 	ops_outi(-1);
 }
 
-// ED:10110000: LDIR
+// ED:10110000: 01R:	LDIR
 OP_DEF(ldir)
 {
-	REPEAT_UNTIL(ldi);
+	REPEAT_LD(ldi);
 }
 
-// ED:10110001: CPIR
+// ED:10110001: 01R:	CPIR
 OP_DEF(cpir)
 {
-	REPEAT_UNTIL(cpi);
+	REPEAT_CP(cpi);
 }
 
-// ED:10110010: INIR
+// ED:10110010: 01R:	INIR
 OP_DEF(inir)
 {
-	REPEAT_UNTIL(ini);
+	REPEAT_IO(ini);
 }
 
-// ED:10110011: OTIR
+// ED:10110011: 01R:	OTIR
 OP_DEF(otir)
 {
-	REPEAT_UNTIL(outi);
+	REPEAT_IO(outi);
 }
 
-// ED:10111000: LDDR
+// ED:10111000: 01R:	LDDR
 OP_DEF(lddr)
 {
-	REPEAT_UNTIL(ldd);
+	REPEAT_LD(ldd);
 }
 
-// ED:10111001: CPDR
+// ED:10111001: 01R:	CPDR
 OP_DEF(cpdr)
 {
-	REPEAT_UNTIL(cpd);
+	REPEAT_CP(cpd);
 }
 
-// ED:10111010: INDR
+// ED:10111010: 01R:	INDR
 OP_DEF(indr)
 {
-	REPEAT_UNTIL(ind);
+	REPEAT_IO(ind);
 }
 
-// ED:10111011: OTDR
+// ED:10111011: 01R:	OTDR
 OP_DEF(otdr)
 {
-	REPEAT_UNTIL(outd);
+	REPEAT_IO(outd);
 }
 
-// ED:11rrr001: MULUB A,r	(R800 only)
+// ED:11rrr001: --R:	MULUB A,r
 OP_DEF(mulub_a_r)
 {
 	op_illegal(2);
 }
 
-// ED:11000011: MULUB HL,BC	(R800 only)
+// ED:11000011: --R:	MULUB HL,BC
 OP_DEF(mulub_hl_bc)
 {
 	op_illegal(2);
 }
 
-// ED:11110011: MULUB HL,SP	(R800 only)
+// ED:11110011: --R:	MULUB HL,SP
 OP_DEF(mulub_hl_sp)
 {
 	op_illegal(2);
 }
 
-// ED:11111111: SYSCALL	(HD64*180 only)
+// ED:11111111: -N-:	SYSCALL
 OP_DEF(syscall)
 {
 	// MSX-DOS エミュレーションのような何か。
@@ -1675,73 +1724,79 @@ OP_DEF(syscall)
 	}
 }
 
-// DD:00rrr100: INC ixr	(Z80/R800)
+// DD:00rrr100: Z-Z:	INC ixr
 OP_DEF(inc_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:00rrr101: DEC ixr	(Z80/R800)
+// DD:00rrr101: Z-Z:	DEC ixr
 OP_DEF(dec_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:01rrrsss: LD r,ixs	(Z80/R800)
+// DD:00rrr110: Z-Z:	LD ixr,n
+OP_DEF(ld_ixr_n)
+{
+	op_illegal(2);
+}
+
+// DD:01rrrsss: Z-Z:	LD r,ixs
 OP_DEF(ld_r_ixs)
 {
 	op_illegal(2);
 }
 
-// DD:10000rrr: ADD A,ixr	(Z80/R800)
+// DD:10000rrr: Z-Z:	ADD A,ixr
 OP_DEF(add_a_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10001rrr: ADC A,ixr	(Z80/R800)
+// DD:10001rrr: Z-Z:	ADC A,ixr
 OP_DEF(adc_a_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10010rrr: SUB ixr	(Z80/R800)
+// DD:10010rrr: Z-Z:	SUB ixr
 OP_DEF(sub_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10011rrr: SBC A,ixr	(Z80/R800)
+// DD:10011rrr: Z-Z:	SBC A,ixr
 OP_DEF(sbc_a_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10100rrr: AND ixr	(Z80/R800)
+// DD:10100rrr: Z-Z:	AND ixr
 OP_DEF(and_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10101rrr: XOR ixr	(Z80/R800)
+// DD:10101rrr: Z-Z:	XOR ixr
 OP_DEF(xor_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10110rrr: OR ixr	(Z80/R800)
+// DD:10110rrr: Z-Z:	OR ixr
 OP_DEF(or_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:10111rrr: CP ixr	(Z80/R800)
+// DD:10111rrr: Z-Z:	CP ixr
 OP_DEF(cp_ixr)
 {
 	op_illegal(2);
 }
 
-// DD:11001011: op_DD_CB
+// DD:11001011: 01R:	op_DD_CB
 OP_DEF(dd_cb)
 {
 	// DD CB の場合は 3バイト目が d で、4バイト目が命令語。