--- nono/m680x0/m68030disasm.cpp	2026/04/29 17:04:31	1.1
+++ nono/m680x0/m68030disasm.cpp	2026/04/29 17:05:26	1.1.1.9
@@ -1,15 +1,14 @@
 //
 // nono
-// Copyright (C) 2017 isaki@NetBSD.org
+// Copyright (C) 2020 nono project
+// Licensed under nono-license.txt
 //
 
 #include "m68030disasm.h"
-#include "bus.h"
-#include "mystring.h"
+#include "debugger_memory.h"
 
 // コンストラクタ
-m680x0disasm::m680x0disasm(DebuggerMD *m)
-	: inherited(m)
+m680x0disasm::m680x0disasm()
 {
 }
 
@@ -20,9 +19,9 @@ m680x0disasm::~m680x0disasm()
 
 // 逆アセンブルを実行
 bool
-m680x0disasm::Exec(saddr_t addr)
+m680x0disasm::Exec(DebuggerMemoryStream *mem_)
 {
-	ExecInit();
+	ExecInit(mem_);
 
 	ir.clear();
 	name.clear();
@@ -30,10 +29,9 @@ m680x0disasm::Exec(saddr_t addr)
 	src.clear();
 	dst.clear();
 
-	pc  = addr;
-	pc0 = pc.addr;
+	pc0 = mem->laddr.Addr();
 
-	switch (fetch16() >> 6) {
+	switch (fetch2() >> 6) {
 #include "m68030switch.h"
 	 default:
 		__unreachable();
@@ -42,7 +40,7 @@ m680x0disasm::Exec(saddr_t addr)
 	// 出力文字列(ダンプ)
 	for (const auto& i : ir) {
 		dump += string_format("%04x ", i);
-    }
+	}
 	if (ir.size() < 5) {
 		dump += std::string(25 - ir.size() * 5, ' ');
 	}
@@ -84,43 +82,28 @@ m680x0disasm::Exec(saddr_t addr)
 
 // ワードピーク (PCを進めずワードを取得する)
 uint32
-m680x0disasm::peek16()
+m680x0disasm::peek2()
 {
-	uint64 paddr;
-
-	if (pc.IsLogical() && md->MMUEnabled()) {
-		paddr = md->TranslateAddr(pc);
-		if ((int64)paddr < 0)
-			return 0xffff;
-	} else {
-		paddr = pc.addr;
-	}
-
-	// 物理空間から読み込む
-	uint16 data;
-	data = vm_phys_peek_8(paddr) << 8;
-	data |= vm_phys_peek_8(paddr + 1);
-	return data;
+	return mem->Peek(2);
 }
 
 // ワードフェッチ
 uint32
-m680x0disasm::fetch16()
+m680x0disasm::fetch2()
 {
-	uint16 data = peek16();
-	// IR に入れて PC を進める
+	uint16 data = mem->Read(2);
+	// IR にも入れる
 	ir.push_back(data);
-	pc.addr += 2;
 	return data;
 }
 
 // ロングワードフェッチ
 uint32
-m680x0disasm::fetch32()
+m680x0disasm::fetch4()
 {
 	uint32 data;
-	data = fetch16() << 16;
-	data |= fetch16();
+	data = fetch2() << 16;
+	data |= fetch2();
 	return data;
 }
 
@@ -215,19 +198,19 @@ m680x0disasm::make_ea(uint mmrr)
 		s = make_anpd(rr);
 		break;
 	 case 0x28 ... 0x2f:	// 5
-		s = disp16() + make_anin(rr);
+		s = disp2() + make_anin(rr);
 		break;
 	 case 0x30 ... 0x37:	// 6
 		s = make_eaix(make_an(rr));
 		break;
 	 case 0x38:			// Abs.W
-		s = addr16();
+		s = addr2();
 		break;
 	 case 0x39:			// Abs.L
-		s = addr32();
+		s = addr4();
 		break;
 	 case 0x3a:			// d16(pc)
-		s = addr32(pc.addr + (int32)(int16)fetch16()) +
+		s = addr4(mem->laddr.Addr() + (int32)(int16)fetch2()) +
 			"(" + make_reg(Reg::PC) + ")";
 		break;
 	 case 0x3b:			// d8(pc,IX)
@@ -236,24 +219,24 @@ m680x0disasm::make_ea(uint mmrr)
 	 case 0x3c:			// imm
 		switch (size) {
 		 case Size::B:
-			s = imm8();
+			s = imm1();
 			break;
 		 case Size::W:
-			s = imm16();
+			s = imm2();
 			break;
 		 case Size::L:
 		 case Size::S:
-			s = imm32();
+			s = imm4();
 			break;
 		 case Size::D:
-			s = imm32();
-			s += string_format("_%08x", fetch32());
+			s = imm4();
+			s += string_format("_%08x", fetch4());
 			break;
 		 case Size::X:
 		 case Size::P:
-			s = imm32();
-			s += string_format("_%08x", fetch32());
-			s += string_format("_%08x", fetch32());
+			s = imm4();
+			s += string_format("_%08x", fetch4());
+			s += string_format("_%08x", fetch4());
 			break;
 		 default:
 			s = "(invalid ea size?)";
@@ -273,7 +256,7 @@ m680x0disasm::make_eaix(std::string base
 	static const char * const scalestr[] = {
 		"", "*2", "*4", "*8",
 	};
-	uint16 ext = fetch16();
+	uint16 ext = fetch2();
 	bool full = (ext & 0x0100);
 	uint rn = (ext >> 12);
 	bool wl = (ext & 0x0800);
@@ -321,11 +304,11 @@ m680x0disasm::make_eaix(std::string base
 		 case 1:	// ベースはヌル
 			break;
 		 case 2:	// ベース.W
-			bd = disp16();
+			bd = disp2();
 			bd += ",";
 			break;
 		 case 3:	// ベース.L
-			bd = disp32();
+			bd = disp4();
 			bd += ",";
 			break;
 		}
@@ -337,11 +320,11 @@ m680x0disasm::make_eaix(std::string base
 			break;
 		 case 2:	// アウター.W
 			od = ",";
-			od += disp16();
+			od += disp2();
 			break;
 		 case 3:	// アウター.L
 			od = ",";
-			od += disp32();
+			od += disp4();
 			break;
 		}
 
@@ -410,7 +393,7 @@ m680x0disasm::make_eaix(std::string base
 				s += ")";
 				break;
 			 default:
-				return string_format("<invalid EA(is=1,iis=%d)>", iis);
+				return string_format("<invalid EA(is=1,iis=%u)>", iis);
 			}
 		}
 	}
@@ -420,65 +403,65 @@ m680x0disasm::make_eaix(std::string base
 
 // addr をワードアドレスとした時の文字列を返す
 std::string
-m680x0disasm::addr16(uint32 addr)
+m680x0disasm::addr2(uint32 addr)
 {
 	return hex16(addr & 0xffff);
 }
 
 // addr をロングワードアドレスとした時の文字列を返す
 std::string
-m680x0disasm::addr32(uint32 addr)
+m680x0disasm::addr4(uint32 addr)
 {
 	return hex32(addr);
 }
 
 // フェッチした値をワードアドレスとして文字列を返す
 std::string
-m680x0disasm::addr16()
+m680x0disasm::addr2()
 {
-	return addr16(fetch16());
+	return addr2(fetch2());
 }
 
 // フェッチした値をロングワードアドレスとして文字列を返す
 std::string
-m680x0disasm::addr32()
+m680x0disasm::addr4()
 {
-	return addr32(fetch32());
+	return addr4(fetch4());
 }
 
 // フェッチした値をワードディスプレースメントとして文字列を返す
 std::string
-m680x0disasm::disp16()
+m680x0disasm::disp2()
 {
-	return shex16(fetch16());
+	return shex16(fetch2());
 }
 
 // フェッチした値をロングワードディスプレースメントとして文字列を返す
 std::string
-m680x0disasm::disp32()
+m680x0disasm::disp4()
 {
-	return shex32(fetch32());
+	return shex32(fetch4());
 }
 
 // バイト即値 imm を文字列にして返す
 std::string
-m680x0disasm::imm8()
+m680x0disasm::imm1()
 {
-	return "#" + hex8(fetch16() & 0xff);
+	return "#" + hex8(fetch2() & 0xff);
 }
 
 // ワード即値 imm を文字列にして返す
 std::string
-m680x0disasm::imm16()
+m680x0disasm::imm2()
 {
-	return "#" + hex16(fetch16());
+	return "#" + hex16(fetch2());
 }
 
 // ロングワード即値 imm を文字列にして返す
 std::string
-m680x0disasm::imm32()
+m680x0disasm::imm4()
 {
-	return "#" + hex32(fetch32());
+	return "#" + hex32(fetch4());
 }
 
 // Dn を文字列にして返す。n の上位ビットは無視する。
@@ -554,7 +537,7 @@ m680x0disasm::make_q8()
 	if (q == 0) {
 		q = 8;
 	}
-	return string_format("#%d", q);
+	return string_format("#%u", q);
 }
 
 // regno で示されるレジスタ名を返す
@@ -615,7 +598,7 @@ m680x0disasm::make_reglist_half(std::str
 			if (top < 0) {
 				// 非表示中ならこのレジスタを出力する。
 				// 初回以外は区切りを先に出力する。
-				if (s.length() != 0) {
+				if (s.empty() == false) {
 					s += '/';
 				}
 				s += reg;
@@ -656,11 +639,11 @@ m680x0disasm::make_bf()
 		if (offset < 8) {
 			s += make_dn(offset);
 		} else {
-			s += string_format("<invalid regno %d>", offset);
+			s += string_format("<invalid regno %u>", offset);
 		}
 	} else {
 		// オフセットは 0..31
-		s += string_format("#%d", offset);
+		s += string_format("#%u", offset);
 	}
 
 	s += ":";
@@ -670,14 +653,14 @@ m680x0disasm::make_bf()
 		if (width < 8) {
 			s += make_dn(width);
 		} else {
-			s += string_format("<invalid regno %d>", width); 
+			s += string_format("<invalid regno %u>", width);
 		}
 	} else {
 		// 幅は 0 なら 32 を意味する
 		if (width == 0) {
 			width = 32;
 		}
-		s += string_format("#%d", width);
+		s += string_format("#%u", width);
 	}
 
 	s += "}";
@@ -699,9 +682,9 @@ m680x0disasm::make_fc()
 	 case 0x08 ... 0x0f:
 		return make_dn(fc);
 	 case 0x10 ... 0x17:
-		return string_format("#%d", fc & 7);
+		return string_format("#%u", fc & 7);
 	 default:
-		return string_format("<invalid fc %d>", fc);
+		return string_format("<invalid fc %u>", fc);
 	}
 }
 
@@ -864,6 +847,12 @@ m680x0disasm::make_fpnlist()
 	"fpcr",
 	"fpsr",
 	"fpiar",
+
+	"urp",
+	"itt0",
+	"itt1",
+	"dtt0",
+	"dtt1",
 };
 
 /*static*/ const char * const m680x0disasm::size_str[] = {
@@ -1844,7 +1833,7 @@ OP_DEF(ori_b)
 {
 	name = "ori";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::CCR);
 	} else {
@@ -1858,7 +1847,7 @@ OP_DEF(ori_w)
 {
 	name = "ori";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::SR);
 	} else {
@@ -1871,14 +1860,14 @@ OP_DEF(ori_l)
 {
 	name = "ori";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
 void
 m680x0disasm::ops_cmp2chk2(m680x0disasm::Size sz)
 {
-	fetch16();
+	fetch2();
 	if ((ir[1] & 0x0800) == 0) {
 		// CMP2.[BWL] <ea>,Rn
 		name = "cmp2";
@@ -1932,23 +1921,23 @@ m680x0disasm::ops_movep()
 	switch (mode) {
 	 case 0:	// MOVEP.W (d,Ay),Dx
 		size = Size::W;
-		src = "(" + addr16() + "," + make_an(ir[0]) + ")";
+		src = "(" + addr2() + "," + make_an(ir[0]) + ")";
 		dst = make_dn(ir[0] >> 9);
 		break;
 	 case 1:	// MOVEP.L (d,Ay),Dx
 		size = Size::L;
-		src = "(" + addr16() + "," + make_an(ir[0]) + ")";
+		src = "(" + addr2() + "," + make_an(ir[0]) + ")";
 		dst = make_dn(ir[0] >> 9);
 		break;
 	 case 2:	// MOVEP.W Dx,(d,Ay)
 		size = Size::W;
 		src = make_dn(ir[0] >> 9);
-		dst = "(" + addr16() + "," + make_an(ir[0]) + ")";
+		dst = "(" + addr2() + "," + make_an(ir[0]) + ")";
 		break;
 	 case 3:	// MOVEP.L Dx,(d,Ay)
 		size = Size::L;
 		src = make_dn(ir[0] >> 9);
-		dst = "(" + addr16() + "," + make_an(ir[0]) + ")";
+		dst = "(" + addr2() + "," + make_an(ir[0]) + ")";
 		break;
 	}
 }
@@ -1991,7 +1980,7 @@ OP_DEF(andi_b)
 {
 	name = "andi";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::CCR);
 	} else {
@@ -2005,7 +1994,7 @@ OP_DEF(andi_w)
 {
 	name = "andi";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::SR);
 	} else {
@@ -2018,7 +2007,7 @@ OP_DEF(andi_l)
 {
 	name = "andi";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
@@ -2033,7 +2022,7 @@ OP_DEF(subi_b)
 {
 	name = "subi";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	dst = make_ea();
 }
 
@@ -2042,7 +2031,7 @@ OP_DEF(subi_w)
 {
 	name = "subi";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	dst = make_ea();
 }
 
@@ -2051,7 +2040,7 @@ OP_DEF(subi_l)
 {
 	name = "subi";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
@@ -2066,7 +2055,7 @@ OP_DEF(addi_b)
 {
 	name = "addi";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	dst = make_ea();
 }
 
@@ -2075,7 +2064,7 @@ OP_DEF(addi_w)
 {
 	name = "addi";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	dst = make_ea();
 }
 
@@ -2084,10 +2073,26 @@ OP_DEF(addi_l)
 {
 	name = "addi";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
+// %0000_011011_00nnnn	RTM Rn
+// %0000_011011_mmmrrr	CALLM #<imm>,<ea>
+OP_DEF(callm)
+{
+	uint n = ir[0] & 0x3f;
+
+	if (n < 16) {
+		name = "rtm";
+		src  = make_rn(n);
+	} else {
+		name = "callm";
+		src  = imm2();
+		dst  = make_ea();
+	}
+}
+
 // BTST,BCHG,BCLR,BSET #<imm>,<ea> の共通部分。
 void
 m680x0disasm::ops_btst_imm_ea()
@@ -2095,15 +2100,15 @@ m680x0disasm::ops_btst_imm_ea()
 	uint n = ir[0] & 0x3f;
 	uint op = (ir[0] >> 6) & 3;
 
-	fetch16();
+	fetch2();
 	name = btst_names[op];
 	if (n < 8) {
 		size = Size::L;
-		src = string_format("#%d", ir[1] & 31);
+		src = string_format("#%u", ir[1] & 31);
 		dst = make_dn(n);
 	} else {
 		size = Size::B;
-		src = string_format("#%d", ir[1] & 7);
+		src = string_format("#%u", ir[1] & 7);
 		dst = make_ea();
 	}
 }
@@ -2142,7 +2147,7 @@ OP_DEF(eori_b)
 {
 	name = "eori";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::CCR);
 	} else {
@@ -2156,7 +2161,7 @@ OP_DEF(eori_w)
 {
 	name = "eori";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	if ((ir[0] & 0x3f) == 0x3c) {
 		dst = make_reg(Reg::SR);
 	} else {
@@ -2169,7 +2174,7 @@ OP_DEF(eori_l)
 {
 	name = "eori";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
@@ -2177,7 +2182,7 @@ OP_DEF(eori_l)
 void
 m680x0disasm::ops_cas(m680x0disasm::Size sz)
 {
-	fetch16();
+	fetch2();
 
 	name = "cas";
 	size = sz;
@@ -2193,11 +2198,11 @@ m680x0disasm::ops_cas2(m680x0disasm::Siz
 {
 	name = "cas2";
 	size = sz;
-	fetch16();
+	fetch2();
 	uint dc1 = ir[1] & 7;
 	uint du1 = ir[1] >> 6;
 	uint rn1 = ir[1] >> 12;
-	fetch16();
+	fetch2();
 	uint dc2 = ir[2] & 7;
 	uint du2 = ir[2] >> 6;
 	uint rn2 = ir[2] >> 12;
@@ -2217,7 +2222,7 @@ OP_DEF(cmpi_b)
 {
 	name = "cmpi";
 	size = Size::B;
-	src = imm8();
+	src = imm1();
 	dst = make_ea();
 }
 
@@ -2226,7 +2231,7 @@ OP_DEF(cmpi_w)
 {
 	name = "cmpi";
 	size = Size::W;
-	src = imm16();
+	src = imm2();
 	dst = make_ea();
 }
 
@@ -2235,7 +2240,7 @@ OP_DEF(cmpi_l)
 {
 	name = "cmpi";
 	size = Size::L;
-	src = imm32();
+	src = imm4();
 	dst = make_ea();
 }
 
@@ -2258,7 +2263,7 @@ OP_DEF(cas_w)
 void
 m680x0disasm::ops_moves(m680x0disasm::Size sz)
 {
-	fetch16();
+	fetch2();
 
 	name = "moves";
 	size = sz;
@@ -2666,7 +2671,7 @@ OP_DEF(nbcd)
 		name = "link";
 		size = Size::L;
 		src = make_an(ir[0]);
-		dst = "#" + disp32();
+		dst = "#" + disp4();
 	} else {
 		// NBCD.B <ea>
 		name = "nbcd";
@@ -2690,7 +2695,7 @@ OP_DEF(pea)
 	} else if (n < 16) {
 		// BKPT #<imm>
 		name = "bkpt";
-		src = string_format("#%d", ir[0] & 7);
+		src = string_format("#%u", ir[0] & 7);
 	} else {
 		// PEA.L <ea>
 		name = "pea";
@@ -2712,7 +2717,7 @@ m680x0disasm::ops_movem_ext(m680x0disasm
 		src = make_dn(ir[0]);
 	} else {
 		// MOVEM.W <list>,<ea>
-		fetch16();
+		fetch2();
 		name = "movem";
 		src = make_reglist();
 		dst = make_ea();
@@ -2776,7 +2781,7 @@ OP_DEF(tas)
 // %0100_110000_mmmrrr	MUL{U,S}.L <ea>,Dl
 OP_DEF(mul)
 {
-	fetch16();
+	fetch2();
 
 	if ((ir[1] & 0x0800) == 0) {
 		name = "mulu";
@@ -2795,7 +2800,7 @@ OP_DEF(mul)
 // %0100_110001_mmmrrr	DIV{U,UL,S,SL}.L <ea>,Dq
 OP_DEF(div)
 {
-	fetch16();
+	fetch2();
 
 	if ((ir[1] & 0x0800) == 0) {
 		name = "divu";
@@ -2821,7 +2826,7 @@ OP_DEF(div)
 // %0100_110010_mmmrrr	MOVEM.W <ea>,<list>
 OP_DEF(movem_w)
 {
-	fetch16();
+	fetch2();
 	name = "movem";
 	size = Size::W;
 	src = make_ea();
@@ -2831,7 +2836,7 @@ OP_DEF(movem_w)
 // %0100_110011_mmmrrr	MOVEM.L <ea>,<list>
 OP_DEF(movem_l)
 {
-	fetch16();
+	fetch2();
 	name = "movem";
 	size = Size::L;
 	src = make_ea();
@@ -2859,13 +2864,13 @@ OP_DEF(trap)
 	switch (n) {
 	 case 0x00 ... 0x0f:	// TRAP #<vector>
 		name = "trap";
-		src = string_format("#%d", n);
+		src = string_format("#%u", n);
 		break;
 	 case 0x10 ... 0x17:	// LINK.W Ay,#<imm>
 		name = "link";
 		size = Size::W;
 		src = make_an(ir[0]);
-		dst = "#" + disp16();
+		dst = "#" + disp2();
 		break;
 	 case 0x18 ... 0x1f:	// UNLK Ay
 		name = "unlk";
@@ -2891,14 +2896,14 @@ OP_DEF(trap)
 		break;
 	 case 0x32:				// STOP #<imm>
 		name = "stop";
-		src = imm16();
+		src = imm2();
 		break;
 	 case 0x33:				// RTE
 		name = "rte";
 		break;
 	 case 0x34:				// RTD #<imm>
 		name = "rtd";
-		src = imm16();
+		src = imm2();
 		break;
 	 case 0x35:				// RTS
 		name = "rts";
@@ -2910,14 +2915,14 @@ OP_DEF(trap)
 		name = "rtr";
 		break;
 	 case 0x3a:				// MOVEC.L Rc,Rn
-		fetch16();
+		fetch2();
 		name = "movec";
 		size = Size::L;
 		src = make_movec();
 		dst = make_rn(ir[1] >> 12);
 		break;
 	 case 0x3b:				// MOVEC.L Rn,Rc
-		fetch16();
+		fetch2();
 		name = "movec";
 		size = Size::L;
 		src = make_rn(ir[1] >> 12);
@@ -2974,9 +2979,13 @@ OP_DEF(addq_l)
 	dst = make_ea();
 }
 
-// Scc/SF のメイン部分。
-void
-m680x0disasm::ops_scc()
+// %0101_cccc11_mmmrrr	Scc.B <ea>
+// %0101_cccc11_001yyy	DBcc.W Dy,<label>
+// %0101_cccc11_111010	TRAPcc.W #<imm>
+// %0101_cccc11_111011	TRAPcc.L #<imm>
+// %0101_cccc11_111100	TRAPcc
+// %0101_000111_001yyy	DBRA.W Dy,<label>
+OP_DEF(scc)
 {
 	uint n = ir[0] & 0x3f;
 	uint cc = (ir[0] >> 8) & 15;
@@ -2997,19 +3006,19 @@ m680x0disasm::ops_scc()
 		}
 		size = Size::W;
 		src = make_dn(ir[0]);
-		dst = addr32(pc0 + 2 + (int32)(int16)fetch16());
+		dst = addr4(pc0 + 2 + (int32)(int16)fetch2());
 		break;
 	 case 0x3a:				// TRAPcc.W #<imm>
 		name = "trap";
 		name += conditions[cc];
 		size = Size::W;
-		src = imm16();
+		src = imm2();
 		break;
 	 case 0x3b:				// TRAPcc.L #<imm>
 		name = "trap";
 		name += conditions[cc];
 		size = Size::L;
-		src = imm32();
+		src = imm4();
 		break;
 	 case 0x3c:				// TRAPcc
 		name = "trap";
@@ -3022,16 +3031,6 @@ m680x0disasm::ops_scc()
 	}
 }
 
-// %0101_000011_mmmrrr	ST.B <ea>
-// %0101_000011_001yyy	DBT.W Dy,<label>
-// %0101_000011_111010	TRAPT.W #<imm>
-// %0101_000011_111011	TRAPT.L #<imm>
-// %0101_000011_111100	TRAPT
-OP_DEF(st)
-{
-	ops_scc();
-}
-
 // %0101_qqq100_mmmrrr	SUBQ.B #qqq,<ea>
 OP_DEF(subq_b)
 {
@@ -3063,187 +3062,27 @@ OP_DEF(subq_l)
 	dst = make_ea();
 }
 
-// %0101_000111_mmmrrr	SF.B <ea>
-// %0101_000111_001yyy	DBRA.W Dy,<label>
-// %0101_000111_111010	TRAPF.W #<imm>
-// %0101_000111_111011	TRAPF.L #<imm>
-// %0101_000111_111100	TRAPF
-OP_DEF(sf)
-{
-	ops_scc();
-}
-
-// %0101_001011_mmmrrr	SHI.B <ea>
-// %0101_001011_001yyy	DBHI.W Dy,<label>
-// %0101_001011_111010	TRAPHI.W #<imm>
-// %0101_001011_111011	TRAPHI.L #<imm>
-// %0101_001011_111100	TRAPHI
-OP_DEF(shi)
-{
-	ops_scc();
-}
-
-// %0101_001111_mmmrrr	SLS.B <ea>
-// %0101_001111_001yyy	DBLS.W Dy,<label>
-// %0101_001111_111010	TRAPLS.W #<imm>
-// %0101_001111_111011	TRAPLS.L #<imm>
-// %0101_001111_111100	TRAPLS
-OP_DEF(sls)
-{
-	ops_scc();
-}
-
-// %0101_010011_mmmrrr	SCC.B <ea>
-// %0101_010011_001yyy	DBCC.W Dy,<label>
-// %0101_010011_111010	TRAPCC.W #<imm>
-// %0101_010011_111011	TRAPCC.L #<imm>
-// %0101_010011_111100	TRAPCC
-OP_DEF(scc)
-{
-	ops_scc();
-}
-
-// %0101_010111_mmmrrr	SCS.B <ea>
-// %0101_010111_001yyy	DBCS.W Dy,<label>
-// %0101_010111_111010	TRAPCS.W #<imm>
-// %0101_010111_111011	TRAPCS.L #<imm>
-// %0101_010111_111100	TRAPCS
-OP_DEF(scs)
-{
-	ops_scc();
-}
-
-// %0101_011011_mmmrrr	SNE.B <ea>
-// %0101_011011_001yyy	DBNE.W Dy,<label>
-// %0101_011011_111010	TRAPNE.W #<imm>
-// %0101_011011_111011	TRAPNE.L #<imm>
-// %0101_011011_111100	TRAPNE
-OP_DEF(sne)
-{
-	ops_scc();
-}
-
-// %0101_011111_mmmrrr	SEQ.B <ea>
-// %0101_011111_001yyy	DBEQ.W Dy,<label>
-// %0101_011111_111010	TRAPEQ.W #<imm>
-// %0101_011111_111011	TRAPEQ.L #<imm>
-// %0101_011111_111100	TRAPEQ
-OP_DEF(seq)
-{
-	ops_scc();
-}
-
-// %0101_100011_mmmrrr	SVC.B <ea>
-// %0101_100011_001yyy	DBVC.W Dy,<label>
-// %0101_100011_111010	TRAPVC.W #<imm>
-// %0101_100011_111011	TRAPVC.L #<imm>
-// %0101_100011_111100	TRAPVC
-OP_DEF(svc)
-{
-	ops_scc();
-}
-
-// %0101_100111_mmmrrr	SVS.B <ea>
-// %0101_100111_001yyy	DBVS.W Dy,<label>
-// %0101_100111_111010	TRAPVS.W #<imm>
-// %0101_100111_111011	TRAPVS.L #<imm>
-// %0101_100111_111100	TRAPVS
-OP_DEF(svs)
-{
-	ops_scc();
-}
-
-// %0101_101011_mmmrrr	SPL.B <ea>
-// %0101_101011_001yyy	DBPL.W Dy,<label>
-// %0101_101011_111010	TRAPPL.W #<imm>
-// %0101_101011_111011	TRAPPL.L #<imm>
-// %0101_101011_111100	TRAPPL
-OP_DEF(spl)
-{
-	ops_scc();
-}
-
-// %0101_101111_mmmrrr	SMI.B <ea>
-// %0101_101111_001yyy	DBMI.W Dy,<label>
-// %0101_101111_111010	TRAPMI.W #<imm>
-// %0101_101111_111011	TRAPMI.L #<imm>
-// %0101_101111_111100	TRAPMI
-OP_DEF(smi)
-{
-	ops_scc();
-}
-
-// %0101_110011_mmmrrr	SGE.B <ea>
-// %0101_110011_001yyy	DBGE.W Dy,<label>
-// %0101_110011_111010	TRAPGE.W #<imm>
-// %0101_110011_111011	TRAPGE.L #<imm>
-// %0101_110011_111100	TRAPGE
-OP_DEF(sge)
-{
-	ops_scc();
-}
-
-// %0101_110111_mmmrrr	SLT.B <ea>
-// %0101_110111_001yyy	DBLT.W Dy,<label>
-// %0101_110111_111010	TRAPLT.W #<imm>
-// %0101_110111_111011	TRAPLT.L #<imm>
-// %0101_110111_111100	TRAPLT
-OP_DEF(slt)
-{
-	ops_scc();
-}
-
-// %0101_111011_mmmrrr	SGT.B <ea>
-// %0101_111011_001yyy	DBGT.W Dy,<label>
-// %0101_111011_111010	TRAPGT.W #<imm>
-// %0101_111011_111011	TRAPGT.L #<imm>
-// %0101_111011_111100	TRAPGT
-OP_DEF(sgt)
-{
-	ops_scc();
-}
-
-// %0101_111111_mmmrrr	SLE.B <ea>
-// %0101_111111_001yyy	DBLE.W Dy,<label>
-// %0101_111111_111010	TRAPLE.W #<imm>
-// %0101_111111_111011	TRAPLE.L #<imm>
-// %0101_111111_111100	TRAPLE
-OP_DEF(sle)
-{
-	ops_scc();
-}
-
-
 // BRA/BSR/Bcc の共通部分。
+// name は呼び出し側で処理済み。
 void
 m680x0disasm::ops_bcc()
 {
-	uint cond = (ir[0] >> 8) & 0x0f;
 	uint32 disp = ir[0] & 0xff;
 
-	switch (cond) {
-	 case 0:	name = "bra";	break;
-	 case 1:	name = "bsr";	break;
-	 default:
-		name = "b";
-		name += conditions[cond];
-		break;
-	}
-
 	if (disp == 0) {
 		// Bxx.W <label>
 		size = Size::W;
-		disp = (int32)(int16)fetch16();
+		disp = (int32)(int16)fetch2();
 	} else if (disp == 0xff) {
 		// Bxx.L <label>
 		size = Size::L;
-		disp = (int32)fetch32();
+		disp = (int32)fetch4();
 	} else {
 		// Bxx.B <label>
 		size = Size::B;
 		disp = (int32)(int8)disp;
 	}
-	src = addr32(pc0 + 2 + disp);
+	src = addr4(pc0 + 2 + disp);
 }
 
 // %0110_000000_000000	BRA.W <label>
@@ -3251,6 +3090,7 @@ m680x0disasm::ops_bcc()
 // %0110_000011_111111	BRA.L <label>
 OP_DEF(bra)
 {
+	name = "bra";
 	ops_bcc();
 }
 
@@ -3259,118 +3099,18 @@ OP_DEF(bra)
 // %0110_000111_111111	BSR.L <label>
 OP_DEF(bsr)
 {
+	name = "bsr";
 	ops_bcc();
 }
 
-// %0110_001000_000000	BHI.W <label>
-// %0110_0010nn_nnnnnn	BHI.B <label>
-// %0110_001011_111111	BHI.L <label>
-OP_DEF(bhi)
-{
-	ops_bcc();
-}
-
-// %0110_001100_000000	BLS.W <label>
-// %0110_0011nn_nnnnnn	BLS.B <label>
-// %0110_001111_111111	BLS.L <label>
-OP_DEF(bls)
-{
-	ops_bcc();
-}
-
-// %0110_010000_000000	BCC.W <label>
-// %0110_0100nn_nnnnnn	BCC.B <label>
-// %0110_010011_111111	BCC.L <label>
+// %0110_cccc00_000000	Bcc.W <label>
+// %0110_ccccnn_nnnnnn	Bcc.B <label>
+// %0110_cccc11_111111	Bcc.L <label>
 OP_DEF(bcc)
 {
-	ops_bcc();
-}
-
-// %0110_010100_000000	BCS.W <label>
-// %0110_0101nn_nnnnnn	BCS.B <label>
-// %0110_010111_111111	BCS.L <label>
-OP_DEF(bcs)
-{
-	ops_bcc();
-}
-
-// %0110_011000_000000	BNE.W <label>
-// %0110_0110nn_nnnnnn	BNE.B <label>
-// %0110_011011_111111	BNE.L <label>
-OP_DEF(bne)
-{
-	ops_bcc();
-}
-
-// %0110_011100_000000	BEQ.W <label>
-// %0110_0111nn_nnnnnn	BEQ.B <label>
-// %0110_011111_111111	BEQ.L <label>
-OP_DEF(beq)
-{
-	ops_bcc();
-}
-
-// %0110_100000_000000	BVC.W <label>
-// %0110_1000nn_nnnnnn	BVC.B <label>
-// %0110_100011_111111	BVC.L <label>
-OP_DEF(bvc)
-{
-	ops_bcc();
-}
-
-// %0110_100100_000000	BVS.W <label>
-// %0110_1001nn_nnnnnn	BVS.B <label>
-// %0110_100111_111111	BVS.L <label>
-OP_DEF(bvs)
-{
-	ops_bcc();
-}
-
-// %0110_101000_000000	BPL.W <label>
-// %0110_1010nn_nnnnnn	BPL.B <label>
-// %0110_101011_111111	BPL.L <label>
-OP_DEF(bpl)
-{
-	ops_bcc();
-}
-
-// %0110_101100_000000	BMI.W <label>
-// %0110_1011nn_nnnnnn	BMI.B <label>
-// %0110_101111_111111	BMI.L <label>
-OP_DEF(bmi)
-{
-	ops_bcc();
-}
-
-// %0110_110000_000000	BGE.W <label>
-// %0110_1100nn_nnnnnn	BGE.B <label>
-// %0110_110011_111111	BGE.L <label>
-OP_DEF(bge)
-{
-	ops_bcc();
-}
-
-// %0110_110100_000000	BLT.W <label>
-// %0110_1101nn_nnnnnn	BLT.B <label>
-// %0110_110111_111111	BLT.L <label>
-OP_DEF(blt)
-{
-	ops_bcc();
-}
-
-// %0110_111000_000000	BGT.W <label>
-// %0110_1110nn_nnnnnn	BGT.B <label>
-// %0110_111011_111111	BGT.L <label>
-OP_DEF(bgt)
-{
-	ops_bcc();
-}
-
-// %0110_111100_000000	BLE.W <label>
-// %0110_1111nn_nnnnnn	BLE.B <label>
-// %0110_111111_111111	BLE.L <label>
-OP_DEF(ble)
-{
+	uint cond = (ir[0] >> 8) & 0x0f;
+	name = "b";
+	name += conditions[cond];
 	ops_bcc();
 }
 
@@ -3384,10 +3124,10 @@ OP_DEF(moveq)
 	//  70NN moveq.l #nn,d0
 	//  4e4f trap #15
 	// という命令列になっているので、これを検出する。
-	uint16 next = peek16();
-	if (next == 0x4e4f) {
+	uint16 next = peek2();
+	if ((ir[0] & 0xff00) == 0x7000 && next == 0x4e4f) {
 		// IOCS コールと確定したら TRAP のワードも取り出しておく
-		fetch16();
+		fetch2();
 		name = "IOCS";
 		src = x68k_iocscall[(uint)val] ?: "<undefined>";
 		return;
@@ -3480,11 +3220,11 @@ OP_DEF(or_w_dn_ea)
 	if (n < 8) {
 		name = "pack";
 		src = make_dn(n) + "," + make_dn(x);
-		dst = imm16();
+		dst = imm2();
 	} else if (n < 16) {
 		name = "pack";
 		src = make_anpd(n) + "," + make_anpd(x);
-		dst = imm16();
+		dst = imm2();
 	} else {
 		// OR.W Dx,<ea>
 		name = "or";
@@ -3505,11 +3245,11 @@ OP_DEF(or_l_dn_ea)
 	if (n < 8) {
 		name = "unpk";
 		src = make_dn(n) + "," + make_dn(x);
-		dst = imm16();
+		dst = imm2();
 	} else if (n < 16) {
 		name = "unpk";
 		src = make_anpd(n) + "," + make_anpd(x);
-		dst = imm16();
+		dst = imm2();
 	} else {
 		// OR.L Dx,<ea>
 		name = "or";
@@ -4125,7 +3865,7 @@ OP_DEF(rol_w)
 // %1110_100011_mmmrrr	BFTST <ea>{#o:#w}
 OP_DEF(bftst)
 {
-	fetch16();
+	fetch2();
 	name = "bftst";
 	src = make_ea() + make_bf();
 }
@@ -4133,7 +3873,7 @@ OP_DEF(bftst)
 // %1110_100111_mmmrrr	BFEXTU <ea>{#o:#w},Dn
 OP_DEF(bfextu)
 {
-	fetch16();
+	fetch2();
 	name = "bfextu";
 	src = make_ea() + make_bf();
 	dst = make_dn(ir[1] >> 12);
@@ -4142,7 +3882,7 @@ OP_DEF(bfextu)
 // %1110_101011_mmmrrr	BFCHG <ea>{#o:#w}
 OP_DEF(bfchg)
 {
-	fetch16();
+	fetch2();
 	name = "bfchg";
 	src = make_ea() + make_bf();
 }
@@ -4150,7 +3890,7 @@ OP_DEF(bfchg)
 // %1110_101111_mmmrrr	BFEXTS <ea>{#o:#w},Dn
 OP_DEF(bfexts)
 {
-	fetch16();
+	fetch2();
 	name = "bfexts";
 	src = make_ea() + make_bf();
 	dst = make_dn(ir[1] >> 12);
@@ -4159,7 +3899,7 @@ OP_DEF(bfexts)
 // %1110_110011_mmmrrr	BFCLR <ea>{#o:#w}
 OP_DEF(bfclr)
 {
-	fetch16();
+	fetch2();
 	name = "bfclr";
 	src = make_ea() + make_bf();
 }
@@ -4167,7 +3907,7 @@ OP_DEF(bfclr)
 // %1110_110111_mmmrrr	BFFFO <ea>{#o:#w},Dn
 OP_DEF(bfffo)
 {
-	fetch16();
+	fetch2();
 	name = "bfffo";
 	src = make_ea() + make_bf();
 	dst = make_dn(ir[1] >> 12);
@@ -4176,7 +3916,7 @@ OP_DEF(bfffo)
 // %1110_111011_mmmrrr	BFSET <ea>{#o:#w}
 OP_DEF(bfset)
 {
-	fetch16();
+	fetch2();
 	name = "bfset";
 	src = make_ea() + make_bf();
 }
@@ -4184,7 +3924,7 @@ OP_DEF(bfset)
 // %1110_111111_mmmrrr	BFINS Dn,<ea>{#o:#w}
 OP_DEF(bfins)
 {
-	fetch16();
+	fetch2();
 	name = "bfins";
 	dst = make_ea() + make_bf();
 	src = make_dn(ir[1] >> 12);
@@ -4212,7 +3952,7 @@ m680x0disasm::ops_pmove(Reg reg, m680x0d
 // %1111_000nnn_nnnnnn	MMU_OP
 OP_DEF(mmuop)
 {
-	uint16 ext = fetch16();
+	uint16 ext = fetch2();
 	switch (ext >> 8) {
 	 case 0x08:	// PMOVE.L   <ea>,TT0
 	 case 0x09:	// PMOVEFD.L <ea>,TT0
@@ -4265,7 +4005,7 @@ OP_DEF(mmuop)
 		FALLTHROUGH;
 	 case 0x30:	// PFLUSH <fc>,#<mask>
 		name = "pflush";
-		src = make_fc() + string_format(",#%d", (ir[1] >> 5) & 7);
+		src = make_fc() + string_format(",#%u", (ir[1] >> 5) & 7);
 		break;
 
 	 case 0x81:	// PTESTW <fc>,<ea>,#0,An
@@ -4308,7 +4048,7 @@ OP_DEF(mmuop)
 			name = "ptestr";
 		}
 		src = make_fc() + "," + make_ea()
-		    + string_format(",#%d", (ext >> 10) & 7);
+		    + string_format(",#%u", (ext >> 10) & 7);
 		break;
 
 	 default:
@@ -4320,7 +4060,7 @@ OP_DEF(mmuop)
 // %1111_001000_nnnnnn	FPGEN
 OP_DEF(fpgen)
 {
-	uint16 ext = fetch16();
+	uint16 ext = fetch2();
 
 	switch (ext >> 13) {
 	 case 0:
@@ -4476,7 +4216,7 @@ m680x0disasm::ops_fmovem_ea_ctl()
 	if ((ir[0] & 0x3f) == 0x3c && n > 1) {
 		for (int i = 1; i < n; i++) {
 			src += "/";
-			src += imm32();
+			src += imm4();
 		}
 	}
 }
@@ -4533,7 +4273,7 @@ OP_DEF(fxcc)
 {
 	uint n = ir[0] & 0x3f;
 
-	fetch16();
+	fetch2();
 	switch (n) {
 	 case 0x00 ... 0x07:	// FScc
 	 case 0x10 ... 0x39:
@@ -4544,17 +4284,17 @@ OP_DEF(fxcc)
 	 case 0x08 ... 0x0f:	// FDBcc
 		name = "fdb" + make_fpcc(ir[1]);
 		src = make_dn(ir[0]);
-		dst = addr32(pc0 + 2 + (int32)(int16)fetch16());
+		dst = addr4(pc0 + 2 + (int32)(int16)fetch2());
 		break;
 	 case 0x3a:				// FTRAPcc.W #<imm>
 		name = "ftrap" + make_fpcc(ir[1]);
 		size = Size::W;
-		src = imm16();
+		src = imm2();
 		break;
 	 case 0x3b:				// FTRAPcc.L #<imm>
 		name = "ftrap" + make_fpcc(ir[1]);
 		size = Size::L;
-		src = imm32();
+		src = imm4();
 		break;
 	 case 0x3c:				// FTRAPcc
 		name = "ftrap" + make_fpcc(ir[1]);
@@ -4568,7 +4308,7 @@ OP_DEF(fxcc)
 // %1111_001010_nnnnnn	FBcc.W <label>
 OP_DEF(fbcc_w)
 {
-	int32 disp = (int32)(int16)fetch16();
+	int32 disp = (int32)(int16)fetch2();
 
 	if ((ir[0] & 0x3f) == 0 && disp == 0) {
 		// FBF.W +$0000 のみ FNOP
@@ -4577,7 +4317,7 @@ OP_DEF(fbcc_w)
 	}
 	name = "fb" + make_fpcc(ir[0]);
 	size = Size::W;
-	src = addr32(pc0 + 2 + disp);
+	src = addr4(pc0 + 2 + disp);
 }
 
 // %1111_001011_nnnnnn	FBcc.L <label>
@@ -4585,17 +4325,17 @@ OP_DEF(fbcc_l)
 {
 	name = "fb" + make_fpcc(ir[0]);
 	size = Size::L;
-	src = addr32(pc0 + 2 + (int32)fetch32());
+	src = addr4(pc0 + 2 + (int32)fetch4());
 }
 
-// %1111_001100_nnnnnn	FSAVE <ea>
+// %1111_001100_mmmrrr	FSAVE <ea>
 OP_DEF(fsave)
 {
 	name = "fsave";
 	src = make_ea();
 }
 
-// %1111_001101_nnnnnn	FRESTORE <ea>
+// %1111_001101_mmmrrr	FRESTORE <ea>
 OP_DEF(frestore)
 {
 	name = "frestore";
@@ -4623,4 +4363,8 @@ OP_DEF(fline)
 OP_DEF(illegal)
 {
 	name = "<illegal instruction>";
+
+	// illegal とは関係ないけど、ほどよく置く場所がないのでここに置いておく。
+	// 変数宣言よりも後ろでクラス内でないと書けない。
+	static_assert(countof(reg_names) == MaxReg, "count of reg_names[]");
 }