--- nono/m680x0/m68030ea.cpp 2026/04/29 17:05:15 1.1.1.4 +++ nono/m680x0/m68030ea.cpp 2026/04/29 17:05:26 1.1.1.5 @@ -18,19 +18,23 @@ // また (An)+/-(An) を含まないため、サイズに関係なく1種類だけでよい。 // // CalcData はユーザーズマニュアルで「可変」と呼ばれているグループで、 -// デスティネーション側のため EA の計算のみ。B/W/L +// デスティネーション側のため EA の計算のみ。サイズは B/W/L。 +// (An)+/-(An) ならレジスタを保存する。 // // CalcMMU は対 MMU 用に勝手に用意したもの。 // // CalcFPU は対 FPU 用。ソースであっても CalcFPU を使用する。 // サイズは B/W/L/S/D/X/P。 +// (An)+/-(An) ならレジスタを保存する。 // フェッチサイクルは別途存在するはずだが不詳。 // // FetchData はユーザーズマニュアルで「データ(Data)」と呼ばれている -// グループで、ソース側のため EA 計算および値の取得。B/W/L +// グループで、ソース側のため EA 計算および値の取得。サイズは B/W/L。 +// (An)+/-(An) ならレジスタを保存する。 // // FetchAll はユーザーズマニュアルのここには記載がないグループで、 -// ソース側のため EA 計算および値の取得。B/W/L +// ソース側のため EA 計算および値の取得。サイズは B/W/L。 +// (An)+/-(An) ならレジスタを保存する。 // // CalcCtrl、CalcData でアドレッシングモードに D や A が含まれている場合は // その命令のデスティネーションに Dn、An が指定できるという意味であり、 @@ -107,64 +111,68 @@ // Calc EA // +// 個別 EA は (An)+/-(An) でもレジスタを保存しない。 +// 自動的に保存する cea_data() 等を介さずこれらを呼ぶ時は +// レジスタ保存のタイミングや回数に注意すること。 + uint32 -MPU680x0Device::cea_anin(int n) +MPU680x0Device::cea_anin(uint n) { CYCLE(2); return internal_ea_anin(n); } uint32 -MPU680x0Device::cea_anpi_8(int n) +MPU680x0Device::cea_anpi_1(uint n) { CYCLE(2); - return internal_ea_anpi_8(n); + return internal_ea_anpi_1(n); } uint32 -MPU680x0Device::cea_anpi_16(int n) +MPU680x0Device::cea_anpi_2(uint n) { CYCLE(2); - return internal_ea_anpi_16(n); + return internal_ea_anpi_2(n); } uint32 -MPU680x0Device::cea_anpi_32(int n) +MPU680x0Device::cea_anpi_4(uint n) { CYCLE(2); - return internal_ea_anpi_32(n); + return internal_ea_anpi_4(n); } uint32 -MPU680x0Device::cea_anpd_8(int n) +MPU680x0Device::cea_anpd_1(uint n) { CYCLE(2); - return internal_ea_anpd_8(n); + return internal_ea_anpd_1(n); } uint32 -MPU680x0Device::cea_anpd_16(int n) +MPU680x0Device::cea_anpd_2(uint n) { CYCLE(2); - return internal_ea_anpd_16(n); + return internal_ea_anpd_2(n); } uint32 -MPU680x0Device::cea_anpd_32(int n) +MPU680x0Device::cea_anpd_4(uint n) { CYCLE(2); - return internal_ea_anpd_32(n); + return internal_ea_anpd_4(n); } uint32 -MPU680x0Device::cea_andi(int n) +MPU680x0Device::cea_andi(uint n) { CYCLE(2); return internal_ea_andi(n); } uint32 -MPU680x0Device::cea_anix(int n) +MPU680x0Device::cea_anix(uint n) { CYCLE(10); // XXX 4,4-18,20 return internal_ea_anix(n); @@ -210,45 +218,45 @@ MPU680x0Device::fea_anin() } inline uint32 -MPU680x0Device::fea_anpi_8() +MPU680x0Device::fea_anpi_1() { CYCLE(3); - return internal_ea_anpi_8(eanum(ir)); + return internal_ea_anpi_1(eanum(ir)); } inline uint32 -MPU680x0Device::fea_anpi_16() +MPU680x0Device::fea_anpi_2() { CYCLE(3); - return internal_ea_anpi_16(eanum(ir)); + return internal_ea_anpi_2(eanum(ir)); } inline uint32 -MPU680x0Device::fea_anpi_32() +MPU680x0Device::fea_anpi_4() { CYCLE(3); - return internal_ea_anpi_32(eanum(ir)); + return internal_ea_anpi_4(eanum(ir)); } inline uint32 -MPU680x0Device::fea_anpd_8() +MPU680x0Device::fea_anpd_1() { CYCLE(4); - return internal_ea_anpd_8(eanum(ir)); + return internal_ea_anpd_1(eanum(ir)); } inline uint32 -MPU680x0Device::fea_anpd_16() +MPU680x0Device::fea_anpd_2() { CYCLE(4); - return internal_ea_anpd_16(eanum(ir)); + return internal_ea_anpd_2(eanum(ir)); } inline uint32 -MPU680x0Device::fea_anpd_32() +MPU680x0Device::fea_anpd_4() { CYCLE(4); - return internal_ea_anpd_32(eanum(ir)); + return internal_ea_anpd_4(eanum(ir)); } inline uint32 @@ -294,13 +302,13 @@ MPU680x0Device::fea_pcix() } inline void -MPU680x0Device::fea_imm_16() +MPU680x0Device::fea_imm_2() { CYCLE(2); } inline void -MPU680x0Device::fea_imm_32() +MPU680x0Device::fea_imm_4() { CYCLE(4); } @@ -312,10 +320,10 @@ MPU680x0Device::fea_imm_32() uint32 MPU680x0Device::internal_ea_ix(uint32 anpc) { - uint16 ext = fetch_16(); - int rn = (ext >> 12) & 15; + uint16 ext = fetch_2(); + uint rn = (ext >> 12) & 15; bool idx_long = (ext & 0x0800); - int scale = (ext >> 9) & 3; + uint scale = (ext >> 9) & 3; if ((ext & 0x0100) == 0) { // Brief extension @@ -364,8 +372,8 @@ MPU680x0Device::internal_ea_ix(uint32 an bool bs = (ext & 0x0080); bool is = (ext & 0x0040); - int bdsize = (ext >> 4) & 3; - int iis = (ext & 7); + uint bdsize = (ext >> 4) & 3; + uint iis = (ext & 7); // ベースレジスタ if (bs) { @@ -381,11 +389,11 @@ MPU680x0Device::internal_ea_ix(uint32 an case 1: // ベースはヌル break; case 2: // ベース.W - base = (int32)(int16)fetch_16(); + base = (int32)(int16)fetch_2(); CYCLE2(2, 3); break; case 3: // ベース.L - base = fetch_32(); + base = fetch_4(); CYCLE2(4, 6); break; default: @@ -410,30 +418,30 @@ MPU680x0Device::internal_ea_ix(uint32 an case 1: // indirect pre-index with null outer CYCLE(10); - return read_32(anpc + base + idx); + return read_4(anpc + base + idx); case 2: // indirect pre-index with word outer CYCLE2(10+2, 10+3); - outer = (int32)(int16)fetch_16(); - return read_32(anpc + base + idx) + outer; + outer = (int32)(int16)fetch_2(); + return read_4(anpc + base + idx) + outer; case 3: // indirect pre-index with long outer CYCLE2(10+2, 10+3); - outer = fetch_32(); - return read_32(anpc + base + idx) + outer; + outer = fetch_4(); + return read_4(anpc + base + idx) + outer; case 4: PANIC("iis==4 reserved"); case 5: // indirect post-index with null outer CYCLE(10); - return read_32(anpc + base) + idx; + return read_4(anpc + base) + idx; case 6: // indirect post-index with word outer CYCLE2(10+2, 10+3); - outer = (int32)(int16)fetch_16(); - return read_32(anpc + base) + idx + outer; + outer = (int32)(int16)fetch_2(); + return read_4(anpc + base) + idx + outer; case 7: // indirect post-index with long outer CYCLE2(10+2, 10+3); - outer = fetch_32(); - return read_32(anpc + base) + idx + outer; + outer = fetch_4(); + return read_4(anpc + base) + idx + outer; default: __unreachable(); } @@ -445,15 +453,15 @@ MPU680x0Device::internal_ea_ix(uint32 an case 1: // memory indirect with null outer CYCLE(10); - return read_32(anpc + base); + return read_4(anpc + base); case 2: // memory indirect with word outer CYCLE2(10+2, 10+3); - outer = (int32)(int16)fetch_16(); - return read_32(anpc + base) + outer; + outer = (int32)(int16)fetch_2(); + return read_4(anpc + base) + outer; case 3: // memory indirect with long outer CYCLE2(10+2, 10+3); - outer = fetch_32(); - return read_32(anpc + base) + outer; + outer = fetch_4(); + return read_4(anpc + base) + outer; default: PANIC("is==1 && iis>3 reserved"); } @@ -495,15 +503,17 @@ MPU680x0Device::cea_ctrl() } uint32 -MPU680x0Device::cea_data_8() +MPU680x0Device::cea_data_1() { switch (eamode(ir)) { case 2: // (An) return cea_anin(eanum(ir)); case 3: // (An)+ - return cea_anpi_8(eanum(ir)); + save_reg_pi(eanum(ir)); + return cea_anpi_1(eanum(ir)); case 4: // -(An) - return cea_anpd_8(eanum(ir)); + save_reg_pd(eanum(ir)); + return cea_anpd_1(eanum(ir)); case 5: // d16(An) return cea_andi(eanum(ir)); case 6: // (An,IX) @@ -524,15 +534,17 @@ MPU680x0Device::cea_data_8() } uint32 -MPU680x0Device::cea_data_16() +MPU680x0Device::cea_data_2() { switch (eamode(ir)) { case 2: // (An) return cea_anin(eanum(ir)); case 3: // (An)+ - return cea_anpi_16(eanum(ir)); + save_reg_pi(eanum(ir)); + return cea_anpi_2(eanum(ir)); case 4: // -(An) - return cea_anpd_16(eanum(ir)); + save_reg_pd(eanum(ir)); + return cea_anpd_2(eanum(ir)); case 5: // d16(An) return cea_andi(eanum(ir)); case 6: // (An,IX) @@ -553,15 +565,17 @@ MPU680x0Device::cea_data_16() } uint32 -MPU680x0Device::cea_data_32() +MPU680x0Device::cea_data_4() { switch (eamode(ir)) { case 2: // (An) return cea_anin(eanum(ir)); case 3: // (An)+ - return cea_anpi_32(eanum(ir)); + save_reg_pi(eanum(ir)); + return cea_anpi_4(eanum(ir)); case 4: // -(An) - return cea_anpd_32(eanum(ir)); + save_reg_pd(eanum(ir)); + return cea_anpd_4(eanum(ir)); case 5: // d16(An) return cea_andi(eanum(ir)); case 6: // (An,IX) @@ -617,7 +631,7 @@ MPU680x0Device::cea_copro() // uint32 -MPU680x0Device::fea_data_8() +MPU680x0Device::fea_data_1() { uint32 ea; @@ -626,36 +640,38 @@ MPU680x0Device::fea_data_8() return reg.D[eanum(ir)] & 0xff; case 2: // (An) ea = fea_anin(); - return read_8(ea); + return read_1(ea); case 3: // (An)+ - ea = fea_anpi_8(); - return read_8(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_1(); + return read_1(ea); case 4: // -(An) - ea = fea_anpd_8(); - return read_8(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_1(); + return read_1(ea); case 5: // d16(An) ea = fea_andi(); - return read_8(ea); + return read_1(ea); case 6: // (An,IX) ea = fea_anix(); - return read_8(ea); + return read_1(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_8(ea); + return read_1(ea); case 1: // Abs.L ea = fea_absl(); - return read_8(ea); + return read_1(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_8(ea); + return read_1(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_8(ea); + return read_1(ea); case 4: // #imm - fea_imm_16(); - return fetch_16() & 0xff; + fea_imm_2(); + return fetch_2() & 0xff; default: break; } @@ -668,7 +684,7 @@ MPU680x0Device::fea_data_8() } uint32 -MPU680x0Device::fea_data_16() +MPU680x0Device::fea_data_2() { uint32 ea; @@ -677,36 +693,38 @@ MPU680x0Device::fea_data_16() return reg.D[eanum(ir)] & 0xffff; case 2: // (An) ea = fea_anin(); - return read_16(ea); + return read_2(ea); case 3: // (An)+ - ea = fea_anpi_16(); - return read_16(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_2(); + return read_2(ea); case 4: // -(An) - ea = fea_anpd_16(); - return read_16(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_2(); + return read_2(ea); case 5: // d16(An) ea = fea_andi(); - return read_16(ea); + return read_2(ea); case 6: // (An,IX) ea = fea_anix(); - return read_16(ea); + return read_2(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_16(ea); + return read_2(ea); case 1: // Abs.L ea = fea_absl(); - return read_16(ea); + return read_2(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_16(ea); + return read_2(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_16(ea); + return read_2(ea); case 4: // #imm - fea_imm_16(); - return fetch_16(); + fea_imm_2(); + return fetch_2(); default: break; } @@ -719,7 +737,7 @@ MPU680x0Device::fea_data_16() } uint32 -MPU680x0Device::fea_data_32() +MPU680x0Device::fea_data_4() { uint32 ea; @@ -728,36 +746,38 @@ MPU680x0Device::fea_data_32() return reg.D[eanum(ir)]; case 2: // (An) ea = fea_anin(); - return read_32(ea); + return read_4(ea); case 3: // (An)+ - ea = fea_anpi_32(); - return read_32(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_4(); + return read_4(ea); case 4: // -(An) - ea = fea_anpd_32(); - return read_32(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_4(); + return read_4(ea); case 5: // d16(An) ea = fea_andi(); - return read_32(ea); + return read_4(ea); case 6: // (An,IX) ea = fea_anix(); - return read_32(ea); + return read_4(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_32(ea); + return read_4(ea); case 1: // Abs.L ea = fea_absl(); - return read_32(ea); + return read_4(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_32(ea); + return read_4(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_32(ea); + return read_4(ea); case 4: // #imm - fea_imm_32(); - return fetch_32(); + fea_imm_4(); + return fetch_4(); default: break; } @@ -770,7 +790,7 @@ MPU680x0Device::fea_data_32() } uint32 -MPU680x0Device::fea_all_8() +MPU680x0Device::fea_all_1() { uint32 ea; @@ -782,36 +802,38 @@ MPU680x0Device::fea_all_8() break; case 2: // (An) ea = fea_anin(); - return read_8(ea); + return read_1(ea); case 3: // (An)+ - ea = fea_anpi_8(); - return read_8(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_1(); + return read_1(ea); case 4: // -(An) - ea = fea_anpd_8(); - return read_8(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_1(); + return read_1(ea); case 5: // d16(An) ea = fea_andi(); - return read_8(ea); + return read_1(ea); case 6: // (An,IX) ea = fea_anix(); - return read_8(ea); + return read_1(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_8(ea); + return read_1(ea); case 1: // Abs.L ea = fea_absl(); - return read_8(ea); + return read_1(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_8(ea); + return read_1(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_8(ea); + return read_1(ea); case 4: // #imm - fea_imm_16(); - return fetch_16() & 0xff; + fea_imm_2(); + return fetch_2() & 0xff; default: break; } @@ -824,7 +846,7 @@ MPU680x0Device::fea_all_8() } uint32 -MPU680x0Device::fea_all_16() +MPU680x0Device::fea_all_2() { uint32 ea; @@ -834,36 +856,38 @@ MPU680x0Device::fea_all_16() return reg.R[ir & 15] & 0xffff; case 2: // (An) ea = fea_anin(); - return read_16(ea); + return read_2(ea); case 3: // (An)+ - ea = fea_anpi_16(); - return read_16(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_2(); + return read_2(ea); case 4: // -(An) - ea = fea_anpd_16(); - return read_16(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_2(); + return read_2(ea); case 5: // d16(An) ea = fea_andi(); - return read_16(ea); + return read_2(ea); case 6: // (An,IX) ea = fea_anix(); - return read_16(ea); + return read_2(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_16(ea); + return read_2(ea); case 1: // Abs.L ea = fea_absl(); - return read_16(ea); + return read_2(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_16(ea); + return read_2(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_16(ea); + return read_2(ea); case 4: // #imm - fea_imm_16(); - return fetch_16(); + fea_imm_2(); + return fetch_2(); default: break; } @@ -876,7 +900,7 @@ MPU680x0Device::fea_all_16() } uint32 -MPU680x0Device::fea_all_32() +MPU680x0Device::fea_all_4() { uint32 ea; @@ -886,36 +910,38 @@ MPU680x0Device::fea_all_32() return reg.R[ir & 15]; case 2: // (An) ea = fea_anin(); - return read_32(ea); + return read_4(ea); case 3: // (An)+ - ea = fea_anpi_32(); - return read_32(ea); + save_reg_pi(eanum(ir)); + ea = fea_anpi_4(); + return read_4(ea); case 4: // -(An) - ea = fea_anpd_32(); - return read_32(ea); + save_reg_pd(eanum(ir)); + ea = fea_anpd_4(); + return read_4(ea); case 5: // d16(An) ea = fea_andi(); - return read_32(ea); + return read_4(ea); case 6: // (An,IX) ea = fea_anix(); - return read_32(ea); + return read_4(ea); case 7: switch (eanum(ir)) { case 0: // Abs.W ea = fea_absw(); - return read_32(ea); + return read_4(ea); case 1: // Abs.L ea = fea_absl(); - return read_32(ea); + return read_4(ea); case 2: // d16(PC) ea = fea_pcdi(); - return read_32(ea); + return read_4(ea); case 3: // (PC,IX) ea = fea_pcix(); - return read_32(ea); + return read_4(ea); case 4: // #imm - fea_imm_32(); - return fetch_32(); + fea_imm_4(); + return fetch_4(); default: break; }