--- nono/m680x0/m68030ops.cpp	2026/04/29 17:05:15	1.1.1.5
+++ nono/m680x0/m68030ops.cpp	2026/04/29 17:05:22	1.1.1.7
@@ -939,7 +939,8 @@ OP_DEF(moves_b)
 	if ((ir2 & 0x0800) == 0) {
 		// <ea>,Rn
 		CYCLE(7);
-		data = read_8_fc(ea);
+		busaddr addr(ea, reg.sfc);
+		data = read_8_fc(addr);
 		if (n < 8) {	// Dn
 			reg.D[n] = (reg.D[n] & 0xffffff00) | data;
 		} else {		// An
@@ -948,8 +949,9 @@ OP_DEF(moves_b)
 	} else {
 		// Rn,<ea>
 		CYCLE2(5, 6);
+		busaddr addr(ea, reg.dfc);
 		data = reg.R[n] & 0xff;
-		write_8_fc(ea, data);
+		write_8_fc(addr, data);
 	}
 }
 
@@ -973,7 +975,8 @@ OP_DEF(moves_w)
 	if ((ir2 & 0x0800) == 0) {
 		// <ea>,Rn
 		CYCLE(7);
-		data = read_16_fc(ea);
+		busaddr addr(ea, reg.sfc);
+		data = read_16_fc(addr);
 		if (n < 8) {	// Dn
 			reg.D[n] = (reg.D[n] & 0xffff0000) | data;
 		} else {		// An
@@ -982,8 +985,9 @@ OP_DEF(moves_w)
 	} else {
 		// Rn,<ea>
 		CYCLE2(5, 6);
+		busaddr addr(ea, reg.dfc);
 		data = reg.R[n] & 0xffff;
-		write_16_fc(ea, data);
+		write_16_fc(addr, data);
 	}
 }
 
@@ -1007,13 +1011,15 @@ OP_DEF(moves_l)
 	if ((ir2 & 0x0800) == 0) {
 		// <ea>,Rn
 		CYCLE(7);
-		data = read_32_fc(ea);
+		busaddr addr(ea, reg.sfc);
+		data = read_32_fc(addr);
 		reg.R[n] = data;
 	} else {
 		// Rn,<ea>
 		CYCLE2(5, 6);
+		busaddr addr(ea, reg.dfc);
 		data = reg.R[n];
-		write_32_fc(ea, data);
+		write_32_fc(addr, data);
 	}
 }
 
@@ -2331,10 +2337,10 @@ MPU680x0Device::ops_movec_rc_rn()
 	int c = ir2 & 0xfff;
 	switch (c) {
 	 case 0x000:
-		reg.R[n] = reg.sfc;
+		reg.R[n] = reg.GetSFC();
 		return;
 	 case 0x001:
-		reg.R[n] = reg.dfc;
+		reg.R[n] = reg.GetDFC();
 		return;
 	 case 0x002:
 		reg.R[n] = reg.cacr;
@@ -2380,15 +2386,15 @@ MPU680x0Device::ops_movec_rn_rc()
 	switch (c) {
 	 case 0x000:
 		CYCLE(12);
-		reg.sfc = reg.R[n];
+		reg.sfc = busaddr::FC(reg.R[n] & 7) | busaddr::R;
 		return;
 	 case 0x001:
 		CYCLE(12);
-		reg.dfc = reg.R[n];
+		reg.dfc = busaddr::FC(reg.R[n] & 7) | busaddr::W;
 		return;
 	 case 0x002:
 		CYCLE(12);
-		reg.cacr = reg.R[n];
+		SetCACR(reg.R[n]);
 		return;
 	 case 0x800:
 		CYCLE(6);
@@ -2445,12 +2451,18 @@ OP_DEF(trap)
 	int32 imm;
 
 	switch (n) {
-	 case 0x00 ... 0x0f:// TRAP #<vector>
+	 case 0x00 ... 0x0e:// TRAP #<vector>
 		CYCLE2(18, 20);
 		// TRAP#N 例外
 		Exception(M68K::EXCEP_TRAP0 + n);
 		return;
 
+	 case 0x0f:			// TRAP #15
+		CYCLE2(18, 20);
+		// TRAP#15 例外 (IOCS コール表示のためこれだけ別処理)
+		ExceptionTrap15();
+		return;
+
 	 case 0x10:
 	 case 0x11:
 	 case 0x12: