![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to m68030ops.cpp CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Isaki's NoNo m68k/m88k emulator] / nono / m680x0|
Return to m68030ops.cpp CVS log | Up to [Isaki's NoNo m68k/m88k emulator] / nono / m680x0 |
1.1 root 1: //
2: // nono
1.1.1.2 ! root 3: // Copyright (C) 2020 nono project
! 4: // Licensed under nono-license.txt
1.1 root 5: //
6:
7: // %0000_000000_mmmrrr ORI.B #<imm>,<ea>
8: // %0000_000000_111100 ORI.B #<imm>,CCR
9: OP_DEF(ori_b)
10: {
11: uint n = RegIR & 0x3f;
12:
13: uint32 src = m68030_fetch_16(cpu) & 0xff;
14: if (n < 8) {
15: // ORI.B #<imm>,Dn
16: CYCLE(2);
17: uint32 dst = (RegD(n) & 0xff) | src;
18: acc_move_8(cpu, dst);
19: RegD(n) = (RegD(n) & 0xffffff00) | dst;
20: } else if (n == 0b111100) {
21: // ORI.B #<imm>,SR
22: CYCLE2(12, 14);
23: CCR.Set(CCR.Get() | src);
24: } else {
25: // ORI.B #<imm>,<ea>
26: CYCLE2(3, 4);
27: uint32 ea = cea_data_8(cpu);
28: uint32 dst = m68030_read_8(cpu, ea);
29: dst |= src;
30: acc_move_8(cpu, dst);
31: m68030_write_8(cpu, ea, dst);
32: }
33: }
34:
35: // %0000_000001_mmmrrr ORI.W #<imm>,<ea>
36: // %0000_000001_111100 ORI.W #<imm>,SR
37: OP_DEF(ori_w)
38: {
39: uint n = RegIR & 0x3f;
40:
41: if (n < 8) {
42: // ORI.W #<imm>,Dn
43: CYCLE(2);
44: uint32 src = m68030_fetch_16(cpu);
45: uint32 dst = (RegD(n) & 0xffff) | src;
46: acc_move_16(cpu, dst);
47: RegD(n) = (RegD(n) & 0xffff0000) | dst;
48: } else if (n == 0b111100) {
49: // ORI.W #<imm>,SR
50: SUPERVISOR_OP;
51: CYCLE2(12, 14);
52: uint32 src = m68030_fetch_16(cpu);
53: m68030_set_sr(cpu, RegSR | src);
54: } else {
55: // ORI.W #<imm>,<ea>
56: CYCLE2(3, 4);
57: uint32 src = m68030_fetch_16(cpu);
58: uint32 ea = cea_data_16(cpu);
59: uint32 dst = m68030_read_16(cpu, ea);
60: dst |= src;
61: acc_move_16(cpu, dst);
62: m68030_write_16(cpu, ea, dst);
63: }
64: }
65:
66: // %0000_000010_mmmrrr ORI.L #<imm>,<ea>
67: OP_DEF(ori_l)
68: {
69: uint n = RegIR & 0x3f;
70:
71: uint32 src = m68030_fetch_32(cpu);
72: if (n < 8) {
73: // ORI.L #<imm>,Dn
74: CYCLE(2);
75: RegD(n) |= src;
76: acc_move_32(cpu, RegD(n));
77: } else {
78: // ORI.L #<imm>,<ea>
79: CYCLE2(3, 4);
80: uint32 ea = cea_data_32(cpu);
81: uint32 dst = m68030_read_32(cpu, ea);
82: dst |= src;
83: acc_move_32(cpu, dst);
84: m68030_write_32(cpu, ea, dst);
85: }
86: }
87:
88: // %0000_000011_mmmrrr CMP2/CHK2.B <ea>,Rn
89: OP_DEF(cmp2chk2_b)
90: {
91: RegIR2 = m68030_fetch_16(cpu);
92: uint32 compare;
93: uint32 ea = cea_ctrl(cpu);
94: uint32 lower;
95: uint32 upper;
96:
97: if ((RegIR2 & 0x8000) == 0) {
98: // compare が Dn
99: compare = (int32)(int8)(RegR(RegIR2 >> 12) & 0xff);
100: } else {
101: // compare が An
102: compare = RegR(RegIR2 >> 12);
103: }
104:
105: // 本当は PC 相対ならプログラム空間アクセス、
106: // それ以外はデータ空間アクセスだが、ここでは区別しない。
107: lower = (int32)(int8)m68030_read_8(cpu, ea);
108: upper = (int32)(int8)m68030_read_8(cpu, ea + 1);
109:
110: acc_chk2cmp2_32(cpu, compare, lower, upper);
111:
112: // サイクル数はこれは実際には全部最大値
113: if ((RegIR2 & 0x0800)) {
114: // CHK2 で条件を満たしていれば例外
115: if (RegCondCS) {
116: CYCLE2(40, 42);
117: m68030_exception(cpu, M68K_EXCEP_CHK);
118: } else {
119: CYCLE(18);
120: }
121: } else {
122: // CMP2
123: CYCLE(20);
124: }
125: }
126:
127: // MOVEP.[WL] (d,Ay),Dx と
128: // MOVEP.[WL] Dx,(d,Ay) の共通部分。
1.1.1.2 ! root 129: static void
1.1 root 130: ops_movep(m68kcpu *cpu)
131: {
132: uint32 disp = (int32)(int16)m68030_fetch_16(cpu);
133: uint32 ea = RegAY + disp;
134: bool size_long = ((RegIR & 0x40) != 0);
135: bool reg2mem = ((RegIR & 0x80) != 0);
136:
137: CYCLE(14);
138:
139: if (reg2mem) {
140: // Dx -> memory
141: uint32 dx = RegDX;
142: if (size_long) {
143: m68030_write_8(cpu, ea, (dx >> 24));
144: ea += 2;
145: m68030_write_8(cpu, ea, (dx >> 16) & 0xff);
146: ea += 2;
147: }
148: m68030_write_8(cpu, ea, (dx >> 8) & 0xff);
149: ea += 2;
150: m68030_write_8(cpu, ea, (dx & 0xff));
151: } else {
152: // memory -> Dx
153: uint32 dx = 0;
154: if (size_long) {
155: dx = m68030_read_8(cpu, ea);
156: dx <<= 8;
157: ea += 2;
158: dx |= m68030_read_8(cpu, ea);
159: dx <<= 8;
160: ea += 2;
161: }
162: // word
163: dx |= m68030_read_8(cpu, ea);
164: dx <<= 8;
165: ea += 2;
166: dx |= m68030_read_8(cpu, ea);
167:
168: if (size_long) {
169: RegDX = dx;
170: } else {
171: RegDX = (RegDX & 0xffff0000) | (dx & 0xffff);
172: }
173: }
174: }
175:
176: // %0000_xxx100_000yyy BTST.L Dx,Dy
177: // %0000_xxx100_001yyy MOVEP.W (d,Ay),Dx
178: // %0000_xxx100_mmmrrr BTST.B Dx,<ea>
179: OP_DEF(btst_dn_ea)
180: {
181: uint n = RegIR & 0x3f;
182:
183: if (n < 8) {
184: // BTST.L Dx,Dy
185: CYCLE(4);
186: uint bit = (RegDX & 31);
187: acc_btst(cpu, RegDY, bit);
188: } else if (n < 16) {
189: // MOVEP.W (d,Ay),Dx
190: ops_movep(cpu);
191: } else {
192: // BTST.B Dx,<ea>
193: CYCLE(4);
194: uint bit = (RegDX & 7);
195: uint32 data = fea_data_8(cpu);
196: acc_btst(cpu, data, bit);
197: }
198: }
199:
200: // %0000_xxx101_000yyy BCHG.L Dx,Dy
201: // %0000_xxx101_001yyy MOVEP.L (d,Ay),Dx
202: // %0000_xxx101_mmmrrr BCHG.B Dx,<ea>
203: OP_DEF(bchg_dn_ea)
204: {
205: uint n = RegIR & 0x3f;
206:
207: if (n < 8) {
208: // BCHG.L Dx,Dy
209: CYCLE(6);
210: uint bit = (RegDX & 31);
211: RegDY = acc_bchg(cpu, RegDY, bit);
212: } else if (n < 16) {
213: // MOVEP.L (d,Ay),Dx
214: ops_movep(cpu);
215: } else {
216: // BCHG.B Dx,<ea>
217: CYCLE(6);
218: uint bit = (RegDX & 7);
219: uint32 ea = cea_data_8(cpu);
220: uint32 data = m68030_read_8(cpu, ea);
221: data = acc_bchg(cpu, data, bit);
222: m68030_write_8(cpu, ea, data);
223: }
224: }
225:
226: // %0000_xxx110_000yyy BCLR.L Dx,Dy
227: // %0000_xxx110_001yyy MOVEP.W Dx,(d,Ay)
228: // %0000_xxx110_mmmrrr BCLR.B Dx,<ea>
229: OP_DEF(bclr_dn_ea)
230: {
231: uint n = RegIR & 0x3f;
232:
233: if (n < 8) {
234: // BCLR.L Dx,Dy
235: CYCLE(6);
236: uint bit = (RegDX & 31);
237: RegDY = acc_bclr(cpu, RegDY, bit);
238: } else if (n < 16) {
239: // MOVEP.W Dx,(d,Ay)
240: ops_movep(cpu);
241: } else {
242: // BCLR.B Dx,<ea>
243: CYCLE(6);
244: uint bit = (RegDX & 7);
245: uint32 ea = cea_data_8(cpu);
246: uint32 data = m68030_read_8(cpu, ea);
247: data = acc_bclr(cpu, data, bit);
248: m68030_write_8(cpu, ea, data);
249: }
250: }
251:
252: // %0000_xxx111_000yyy BSET.L Dx,Dy
253: // %0000_xxx111_001yyy MOVEP.L Dx,(d,Ay)
254: // %0000_xxx111_mmmrrr BSET.B Dx,<ea>
255: OP_DEF(bset_dn_ea)
256: {
257: uint n = RegIR & 0x3f;
258:
259: if (n < 8) {
260: // BSET.L Dx,Dy
261: CYCLE(6);
262: uint bit = (RegDX & 31);
263: RegDY = acc_bset(cpu, RegDY, bit);
264: } else if (n < 16) {
265: // MOVEP.L Dx,(d,Ay)
266: ops_movep(cpu);
267: } else {
268: // BSET.B Dx,<ea>
269: CYCLE(6);
270: uint bit = (RegDX & 7);
271: uint32 ea = cea_data_8(cpu);
272: uint32 data = m68030_read_8(cpu, ea);
273: data = acc_bset(cpu, data, bit);
274: m68030_write_8(cpu, ea, data);
275: }
276: }
277:
278: // %0000_001000_mmmrrr ANDI.B #<imm>,<ea>
279: // %0000_001000_111100 ANDI.B #<imm>,CCR
280: OP_DEF(andi_b)
281: {
282: uint n = RegIR & 0x3f;
283:
284: uint32 src = m68030_fetch_16(cpu) & 0xff;
285: if (n < 8) {
286: // ANDI.B #<imm>,Dn
287: CYCLE(2);
288: uint32 dst = RegD(n) & 0xff;
289: dst &= src;
290: acc_move_8(cpu, dst);
291: RegD(n) = (RegD(n) & 0xffffff00) | dst;
292: } else if (n == 0b111100) {
293: // ANDI.B #<imm>,CCR
294: CYCLE2(12, 14);
295: CCR.Set(CCR.Get() & src);
296: } else {
297: // ANDI.B #<imm>,<ea>
298: CYCLE2(3, 4);
299: uint32 ea = cea_data_8(cpu);
300: uint32 dst = m68030_read_8(cpu, ea);
301: dst &= src;
302: acc_move_8(cpu, dst);
303: m68030_write_8(cpu, ea, dst);
304: }
305: }
306:
307: // %0000_001001_mmmrrr ANDI.W #<imm>,<ea>
308: // %0000_001001_111100 ANDI.W #<imm>,SR
309: OP_DEF(andi_w)
310: {
311: uint n = RegIR & 0x3f;
312:
313: if (n < 8) {
314: // ANDI.W #<imm>,Dn
315: CYCLE(2);
316: uint32 src = m68030_fetch_16(cpu);
317: uint32 dst = RegD(n) & 0xffff;
318: dst &= src;
319: acc_move_16(cpu, dst);
320: RegD(n) = (RegD(n) & 0xffff0000) | dst;
321: } else if (n == 0b111100) {
322: // ANDI.W #<imm>,SR
323: SUPERVISOR_OP;
324: CYCLE2(12, 14);
325: uint32 src = m68030_fetch_16(cpu);
326: m68030_set_sr(cpu, RegSR & src);
327: } else {
328: // ANDI.W #<imm>,<ea>
329: CYCLE2(3, 4);
330: uint32 src = m68030_fetch_16(cpu);
331: uint32 ea = cea_data_16(cpu);
332: uint32 dst = m68030_read_16(cpu, ea);
333: dst &= src;
334: acc_move_16(cpu, dst);
335: m68030_write_16(cpu, ea, dst);
336: }
337: }
338:
339: // %0000_001010_mmmrrr ANDI.L #<imm>,<ea>
340: OP_DEF(andi_l)
341: {
342: uint n = RegIR & 0x3f;
343:
344: uint32 src = m68030_fetch_32(cpu);
345: if (n < 8) {
346: // ANDI.L #<imm>,Dn
347: CYCLE(2);
348: RegD(n) &= src;
349: acc_move_32(cpu, RegD(n));
350: } else {
351: // ANDI.L #<imm>,<ea>
352: CYCLE2(3, 4);
353: uint32 ea = cea_data_32(cpu);
354: uint32 dst = m68030_read_32(cpu, ea);
355: dst &= src;
356: acc_move_32(cpu, dst);
357: m68030_write_32(cpu, ea, dst);
358: }
359: }
360:
361: // %0000_001011_mmmrrr CMP2/CHK2.W <ea>,Rn
362: OP_DEF(cmp2chk2_w)
363: {
364: RegIR2 = m68030_fetch_16(cpu);
365: uint32 compare;
366: uint32 ea = cea_ctrl(cpu);
367: uint32 lower;
368: uint32 upper;
369:
370: if ((RegIR2 & 0x8000) == 0) {
371: // compare が Dn
372: compare = (int32)(int16)(RegR(RegIR2 >> 12) & 0xffff);
373: } else {
374: // compare が An
375: compare = RegR(RegIR2 >> 12);
376: }
377:
378: // 本当は PC 相対ならプログラム空間アクセス、
379: // それ以外はデータ空間アクセスだが、ここでは区別しない。
380: lower = (int32)(int16)m68030_read_16(cpu, ea);
381: upper = (int32)(int16)m68030_read_16(cpu, ea + 2);
382:
383: acc_chk2cmp2_32(cpu, compare, lower, upper);
384:
385: // サイクル数はこれは実際には全部最大値
386: if ((RegIR2 & 0x0800)) {
387: // CHK2 で条件を満たしていれば例外
388: if (RegCondCS) {
389: CYCLE2(40, 42);
390: m68030_exception(cpu, M68K_EXCEP_CHK);
391: } else {
392: CYCLE(18);
393: }
394: } else {
395: // CMP2
396: CYCLE(20);
397: }
398: }
399:
400: // %0000_010000_mmmrrr SUBI.B #<imm>,<ea>
401: OP_DEF(subi_b)
402: {
403: uint n = RegIR & 0x3f;
404:
405: uint32 src = m68030_fetch_16(cpu) & 0xff;
406: if (n < 8) {
407: // SUBI.B #<imm>,Dn
408: CYCLE(2);
409: uint32 dst = RegD(n) & 0xff;
410: dst = acc_sub_8(cpu, src, dst);
411: RegD(n) = (RegD(n) & 0xffffff00) | dst;
412: } else {
413: // SUBI.B #<imm>,<ea>
414: CYCLE2(3, 4);
415: uint32 ea = cea_data_8(cpu);
416: uint32 dst = m68030_read_8(cpu, ea);
417: dst = acc_sub_8(cpu, src, dst);
418: m68030_write_8(cpu, ea, dst);
419: }
420: }
421:
422: // %0000_010001_mmmrrr SUBI.W #<imm>,<ea>
423: OP_DEF(subi_w)
424: {
425: uint n = RegIR & 0x3f;
426:
427: uint32 src = m68030_fetch_16(cpu);
428: if (n < 8) {
429: // SUBI.W #<imm>,Dn
430: CYCLE(2);
431: uint32 dst = RegD(n) & 0xffff;
432: dst = acc_sub_16(cpu, src, dst);
433: RegD(n) = (RegD(n) & 0xffff0000) | dst;
434: } else {
435: // SUBI.W #<imm>,<ea>
436: CYCLE2(3, 4);
437: uint32 ea = cea_data_16(cpu);
438: uint32 dst = m68030_read_16(cpu, ea);
439: dst = acc_sub_16(cpu, src, dst);
440: m68030_write_16(cpu, ea, dst);
441: }
442: }
443:
444: // %0000_010010_mmmrrr SUBI.L #<imm>,<ea>
445: OP_DEF(subi_l)
446: {
447: uint n = RegIR & 0x3f;
448:
449: uint32 src = m68030_fetch_32(cpu);
450: if (n < 8) {
451: // SUBI.L #<imm>,Dn
452: CYCLE(2);
453: RegD(n) = acc_sub_32(cpu, src, RegD(n));
454: } else {
455: // SUBI.L #<imm>,<ea>
456: CYCLE2(3, 4);
457: uint32 ea = cea_data_32(cpu);
458: uint32 dst = m68030_read_32(cpu, ea);
459: dst = acc_sub_32(cpu, src, dst);
460: m68030_write_32(cpu, ea, dst);
461: }
462: }
463:
464: // %0000_010011_mmmrrr CMP2/CHK2.L <ea>,Rn
465: OP_DEF(cmp2chk2_l)
466: {
467: RegIR2 = m68030_fetch_16(cpu);
468: uint32 compare = RegR(RegIR2 >> 12);
469: uint32 ea = cea_ctrl(cpu);
470: uint32 lower;
471: uint32 upper;
472:
473: // 本当は PC 相対ならプログラム空間アクセス、
474: // それ以外はデータ空間アクセスだが、ここでは区別しない。
475: lower = m68030_read_32(cpu, ea);
476: upper = m68030_read_32(cpu, ea + 4);
477:
478: acc_chk2cmp2_32(cpu, compare, lower, upper);
479:
480: // サイクル数はこれは実際には全部最大値
481: if ((RegIR2 & 0x0800)) {
482: // CHK2 で条件を満たしていれば例外
483: if (RegCondCS) {
484: CYCLE2(40, 42);
485: m68030_exception(cpu, M68K_EXCEP_CHK);
486: } else {
487: CYCLE(18);
488: }
489: } else {
490: // CMP2
491: CYCLE(20);
492: }
493: }
494:
495: // %0000_011000_mmmrrr ADDI.B #<imm>,<ea>
496: OP_DEF(addi_b)
497: {
498: uint n = RegIR & 0x3f;
499:
500: uint32 src = m68030_fetch_16(cpu) & 0xff;
501: if (n < 8) {
502: // ADDI.B #<imm>,Dn
503: CYCLE(2);
504: uint32 dst = RegD(n) & 0xff;
505: dst = acc_add_8(cpu, src, dst);
506: RegD(n) = (RegD(n) & 0xffffff00) | dst;
507: } else {
508: // ADDI.B #<imm>,<ea>
509: CYCLE2(3, 4);
510: uint32 ea = cea_data_8(cpu);
511: uint32 dst = m68030_read_8(cpu, ea);
512: dst = acc_add_8(cpu, src, dst);
513: m68030_write_8(cpu, ea, dst);
514: }
515: }
516:
517: // %0000_011001_mmmrrr ADDI.W #<imm>,<ea>
518: OP_DEF(addi_w)
519: {
520: uint n = RegIR & 0x3f;
521:
522: uint32 src = m68030_fetch_16(cpu);
523: if (n < 8) {
524: // ADDI.W #<imm>,Dn
525: CYCLE(2);
526: uint32 dst = RegD(n) & 0xffff;
527: dst = acc_add_16(cpu, src, dst);
528: RegD(n) = (RegD(n) & 0xffff0000) | dst;
529: } else {
530: // ADDI.W #<imm>,<ea>
531: CYCLE2(3, 4);
532: uint32 ea = cea_data_16(cpu);
533: uint32 dst = m68030_read_16(cpu, ea);
534: dst = acc_add_16(cpu, src, dst);
535: m68030_write_16(cpu, ea, dst);
536: }
537: }
538:
539: // %0000_011010_mmmrrr ADDI.L #<imm>,<ea>
540: OP_DEF(addi_l)
541: {
542: uint n = RegIR & 0x3f;
543:
544: uint32 src = m68030_fetch_32(cpu);
545: if (n < 8) {
546: // ADDI.L #<imm>,Dn
547: CYCLE(2);
548: RegD(n) = acc_add_32(cpu, src, RegD(n));
549: } else {
550: // ADDI.L #<imm>,<ea>
551: CYCLE2(3, 4);
552: uint32 ea = cea_data_32(cpu);
553: uint32 dst = m68030_read_32(cpu, ea);
554: dst = acc_add_32(cpu, src, dst);
555: m68030_write_32(cpu, ea, dst);
556: }
557: }
558:
559: // %0000_100000_000yyy BTST.L #<imm>,Dy
560: // %0000_100000_mmmrrr BTST.B #<imm>,<ea>
561: OP_DEF(btst_imm_ea)
562: {
563: uint n = RegIR & 0x3f;
564:
565: if (n < 8) {
566: // BTST.L #<imm>,Dy
567: CYCLE(4);
568: uint bit = m68030_fetch_16(cpu) & 31;
569: acc_btst(cpu, RegDY, bit);
570: } else if (n == 0x3c) {
571: // BTST.B #<imm>,<ea> の <ea> には #imm はない
572: op_illegal(cpu);
573: } else {
574: // BTST.B #<imm>,<ea>
575: CYCLE(4);
576: uint bit = m68030_fetch_16(cpu) & 7;
577: uint32 data = fea_data_8(cpu);
578: acc_btst(cpu, data, bit);
579: }
580: }
581:
582: // %0000_100001_000yyy BCHG.L #<imm>,Dy
583: // %0000_100001_mmmrrr BCHG.B #<imm>,<ea>
584: OP_DEF(bchg_imm_ea)
585: {
586: uint n = RegIR & 0x3f;
587:
588: if (n < 8) {
589: // BCHG.L #<imm>,Dy
590: CYCLE(6);
591: uint bit = m68030_fetch_16(cpu) & 31;
592: RegDY = acc_bchg(cpu, RegDY, bit);
593: } else if (n == 0x3c) {
594: // BCHG.B #<imm>,<ea> の <ea> には #imm はない
595: op_illegal(cpu);
596: } else {
597: // BCHG.B #<imm>,<ea>
598: CYCLE(6);
599: uint bit = m68030_fetch_16(cpu) & 7;
600: uint32 ea = cea_data_8(cpu);
601: uint32 data = m68030_read_8(cpu, ea);
602: data = acc_bchg(cpu, data, bit);
603: m68030_write_8(cpu, ea, data);
604: }
605: }
606:
607: // %0000_100010_000yyy BCLR.L #<imm>,Dy
608: // %0000_100010_mmmrrr BCLR.B #<imm>,<ea>
609: OP_DEF(bclr_imm_ea)
610: {
611: uint n = RegIR & 0x3f;
612:
613: if (n < 8) {
614: // BCLR.L #<imm>,Dy
615: CYCLE(6);
616: uint bit = m68030_fetch_16(cpu) & 31;
617: RegDY = acc_bclr(cpu, RegDY, bit);
618: } else if (n == 0x3c) {
619: // BCLR.B #<imm>,<ea> の <ea> には #imm はない
620: op_illegal(cpu);
621: } else {
622: // BCLR.B #<imm>,<ea>
623: CYCLE(6);
624: uint bit = m68030_fetch_16(cpu) & 7;
625: uint32 ea = cea_data_8(cpu);
626: uint32 data = m68030_read_8(cpu, ea);
627: data = acc_bclr(cpu, data, bit);
628: m68030_write_8(cpu, ea, data);
629: }
630: }
631:
632: // %0000_100011_000yyy BSET.L #<imm>,Dy
633: // %0000_100011_mmmrrr BSET.B #<imm>,<ea>
634: OP_DEF(bset_imm_ea)
635: {
636: uint n = RegIR & 0x3f;
637:
638: if (n < 8) {
639: // BSET.L #<imm>,Dy
640: CYCLE(6);
641: uint bit = m68030_fetch_16(cpu) & 31;
642: RegDY = acc_bset(cpu, RegDY, bit);
643: } else if (n == 0x3c) {
644: // BSET.B #<imm>,<ea> の <ea> には #imm はない
645: op_illegal(cpu);
646: } else {
647: // BSET.B #<imm>,<ea>
648: CYCLE(6);
649: uint bit = m68030_fetch_16(cpu) & 7;
650: uint32 ea = cea_data_8(cpu);
651: uint32 data = m68030_read_8(cpu, ea);
652: data = acc_bset(cpu, data, bit);
653: m68030_write_8(cpu, ea, data);
654: }
655: }
656:
657: // %0000_101000_mmmrrr EORI.B #<imm>,<ea>
658: // %0000_101000_111100 EORI.B #<imm>,CCR
659: OP_DEF(eori_b)
660: {
661: uint n = RegIR & 0x3f;
662:
663: uint32 src = m68030_fetch_16(cpu) & 0xff;
664: if (n < 8) {
665: // EORI.B #<imm>,Dn
666: CYCLE(2);
667: uint32 dst = (RegD(n) & 0xff) ^ src;
668: acc_move_8(cpu, dst);
669: RegD(n) = (RegD(n) & 0xffffff00) | dst;
670: } else if (n == 0b111100) {
671: // EORI.B #<imm>,SR
672: CYCLE2(12, 14);
673: CCR.Set(CCR.Get() ^ src);
674: } else {
675: // EORI.B #<imm>,<ea>
676: CYCLE2(3, 4);
677: uint32 ea = cea_data_8(cpu);
678: uint32 dst = m68030_read_8(cpu, ea);
679: dst ^= src;
680: acc_move_8(cpu, dst);
681: m68030_write_8(cpu, ea, dst);
682: }
683: }
684:
685: // %0000_101001_mmmrrr EORI.W #<imm>,<ea>
686: // %0000_101001_111100 EORI.W #<imm>,SR
687: OP_DEF(eori_w)
688: {
689: uint n = RegIR & 0x3f;
690:
691: if (n < 8) {
692: // EORI.W #<imm>,Dn
693: CYCLE(2);
694: uint32 src = m68030_fetch_16(cpu);
695: uint32 dst = (RegD(n) & 0xffff) ^ src;
696: acc_move_16(cpu, dst);
697: RegD(n) = (RegD(n) & 0xffff0000) | dst;
698: } else if (n == 0b111100) {
699: // EORI.W #<imm>,SR
700: SUPERVISOR_OP;
701: CYCLE2(12, 14);
702: uint32 src = m68030_fetch_16(cpu);
703: m68030_set_sr(cpu, RegSR ^ src);
704: } else {
705: // EORI.W #<imm>,<ea>
706: CYCLE2(3, 4);
707: uint32 src = m68030_fetch_16(cpu);
708: uint32 ea = cea_data_16(cpu);
709: uint32 dst = m68030_read_16(cpu, ea);
710: dst ^= src;
711: acc_move_16(cpu, dst);
712: m68030_write_16(cpu, ea, dst);
713: }
714: }
715:
716: // %0000_101010_mmmrrr EORI.L #<imm>,<ea>
717: OP_DEF(eori_l)
718: {
719: uint n = RegIR & 0x3f;
720:
721: uint32 src = m68030_fetch_32(cpu);
722: if (n < 8) {
723: // EORI.L #<imm>,Dn
724: CYCLE(2);
725: RegD(n) ^= src;
726: acc_move_32(cpu, RegD(n));
727: } else {
728: // EORI.L #<imm>,<ea>
729: CYCLE2(3, 4);
730: uint32 ea = cea_data_32(cpu);
731: uint32 dst = m68030_read_32(cpu, ea);
732: dst ^= src;
733: acc_move_32(cpu, dst);
734: m68030_write_32(cpu, ea, dst);
735: }
736: }
737:
738: // %0000_101011_mmmrrr CAS.B Dc,Du,<ea>
739: OP_DEF(cas_b)
740: {
741: RegIR2 = m68030_fetch_16(cpu);
742: uint c = RegIR2 & 7;
743: uint u = (RegIR2 >> 6) & 7;
744: uint32 dc = RegD(c) & 0xff;
745: uint32 du = RegD(u) & 0xff;
746: uint ea = cea_data_8(cpu);
747: uint32 dst = m68030_read_8(cpu, ea);
748:
749: acc_cmp_8(cpu, dc, dst);
750: if (CCR.IsZ()) {
751: // 等しければ、Du -> dst
752: CYCLE(13);
753: m68030_write_8(cpu, ea, du);
754: } else {
755: // そうでなければ、dst -> Dc
756: CYCLE(11);
757: RegD(c) = (RegD(c) & 0xffffff00) | dst;
758: }
759: }
760:
761: // %0000_110000_mmmrrr CMPI.B #<imm>,<ea>
762: OP_DEF(cmpi_b)
763: {
764: uint n = RegIR & 0x3f;
765:
766: // CMPI はデータアドレッシングだが #imm がないことに注意
767: if (n == 0x3c) {
768: op_illegal(cpu);
769: return;
770: }
771: CYCLE(2);
772: uint32 src = m68030_fetch_16(cpu) & 0xff;
773: uint32 dst = fea_data_8(cpu);
774: acc_cmp_8(cpu, src, dst);
775: }
776:
777: // %0000_110001_mmmrrr CMPI.W #<imm>,<ea>
778: OP_DEF(cmpi_w)
779: {
780: uint n = RegIR & 0x3f;
781:
782: // CMPI はデータアドレッシングだが #imm がないことに注意
783: if (n == 0x3c) {
784: op_illegal(cpu);
785: return;
786: }
787: CYCLE(2);
788: uint32 src = m68030_fetch_16(cpu);
789: uint32 dst = fea_data_16(cpu);
790: acc_cmp_16(cpu, src, dst);
791: }
792:
793: // %0000_110010_mmmrrr CMPI.L #<imm>,<ea>
794: OP_DEF(cmpi_l)
795: {
796: uint n = RegIR & 0x3f;
797:
798: // CMPI はデータアドレッシングだが #imm がないことに注意
799: if (n == 0x3c) {
800: op_illegal(cpu);
801: return;
802: }
803: CYCLE(2);
804: uint32 src = m68030_fetch_32(cpu);
805: uint32 dst = fea_data_32(cpu);
806: acc_cmp_32(cpu, src, dst);
807: }
808:
809: // %0000_110011_mmmrrr CAS.W Dc,Du,<ea>
810: // %0000_110011_111100 CAS2.W Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
811: OP_DEF(cas_w)
812: {
813: uint n = RegIR & 0x3f;
814:
815: if (n == 0x3c) {
816: // CAS2.W Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
817: RegIR2 = m68030_fetch_16(cpu);
818: uint32 ir3 = m68030_fetch_16(cpu);
819: uint c1 = RegIR2 & 7;
820: uint u1 = (RegIR2 >> 6) & 7;
821: uint r1 = RegIR2 >> 12;
822: uint c2 = ir3 & 7;
823: uint u2 = (ir3 >> 6) & 7;
824: uint r2 = ir3 >> 12;
825: uint32 dc1 = RegD(c1) & 0xffff;
826: uint32 du1 = RegD(u1) & 0xffff;
827: uint32 ea1 = RegR(r1);
828: uint32 dc2 = RegD(c2) & 0xffff;
829: uint32 du2 = RegD(u2) & 0xffff;
830: uint32 ea2 = RegR(r2);
831:
832: uint32 dst1 = m68030_read_16(cpu, ea1);
833: uint32 dst2 = m68030_read_16(cpu, ea2);
834: acc_cmp_16(cpu, dc1, dst1);
835: if (CCR.IsZ()) {
836: acc_cmp_16(cpu, dc2, dst2);
837: if (CCR.IsZ()) {
838: // 更新オペランド -> デスティネーション
839: CYCLE2(0, 2); // これは成功時の追加分
840: m68030_write_16(cpu, ea1, du1);
841: m68030_write_16(cpu, ea2, du2);
842: }
843: }
844: // デスティネーション -> 比較オペランド
845: CYCLE(24); // 本当はこれは最大値
846: RegD(c1) = (RegD(c1) & 0xffff0000) | dst1;
847: RegD(c2) = (RegD(c2) & 0xffff0000) | dst2;
848: } else {
849: // CAS.W Dc,Du,<ea>
850: RegIR2 = m68030_fetch_16(cpu);
851: uint c = RegIR2 & 7;
852: uint u = (RegIR2 >> 6) & 7;
853: uint32 dc = RegD(c) & 0xffff;
854: uint32 du = RegD(u) & 0xffff;
855: uint ea = cea_data_16(cpu);
856: uint32 dst = m68030_read_16(cpu, ea);
857:
858: acc_cmp_16(cpu, dc, dst);
859: if (CCR.IsZ()) {
860: // 等しければ、Du -> dst
861: CYCLE(13);
862: m68030_write_16(cpu, ea, du);
863: } else {
864: // そうでなければ、dst -> Dc
865: CYCLE(11);
866: RegD(c) = (RegD(c) & 0xffff0000) | dst;
867: }
868: }
869: }
870:
871: // %0000_111000_mmmrrr MOVES.B <ea>,Rn
872: // %0000_111000_mmmrrr MOVES.B Rn,<ea>
873: OP_DEF(moves_b)
874: {
875: SUPERVISOR_OP;
876:
877: RegIR2 = m68030_fetch_16(cpu);
878: uint n = RegIR2 >> 12;
879: uint ea;
880: uint32 data;
881:
882: if ((RegIR & 0x3f) < 16) {
883: op_illegal(cpu);
884: return;
885: }
886:
887: ea = cea_data_8(cpu);
888: if ((RegIR2 & 0x0800) == 0) {
889: // <ea>,Rn
890: CYCLE(7);
891: data = m68030_read_8_fc(cpu, ea);
892: if (n < 8) { // Dn
893: RegD(n) = (RegD(n) & 0xffffff00) | data;
894: } else { // An
895: RegR(n) = (int32)(int8)data;
896: }
897: } else {
898: // Rn,<ea>
899: CYCLE2(5, 6);
900: data = RegR(n) & 0xff;
901: m68030_write_8_fc(cpu, ea, data);
902: }
903: }
904:
905: // %0000_111001_mmmrrr MOVES.W <ea>,Rn
906: // %0000_111001_mmmrrr MOVES.W Rn,<ea>
907: OP_DEF(moves_w)
908: {
909: SUPERVISOR_OP;
910:
911: RegIR2 = m68030_fetch_16(cpu);
912: uint n = RegIR2 >> 12;
913: uint ea;
914: uint32 data;
915:
916: if ((RegIR & 0x3f) < 16) {
917: op_illegal(cpu);
918: return;
919: }
920:
921: ea = cea_data_16(cpu);
922: if ((RegIR2 & 0x0800) == 0) {
923: // <ea>,Rn
924: CYCLE(7);
925: data = m68030_read_16_fc(cpu, ea);
926: if (n < 8) { // Dn
927: RegD(n) = (RegD(n) & 0xffff0000) | data;
928: } else { // An
929: RegR(n) = (int32)(int16)data;
930: }
931: } else {
932: // Rn,<ea>
933: CYCLE2(5, 6);
934: data = RegR(n) & 0xffff;
935: m68030_write_16_fc(cpu, ea, data);
936: }
937: }
938:
939: // %0000_111010_mmmrrr MOVES.L <ea>,Rn
940: // %0000_111010_mmmrrr MOVES.L Rn,<ea>
941: OP_DEF(moves_l)
942: {
943: SUPERVISOR_OP;
944:
945: RegIR2 = m68030_fetch_16(cpu);
946: uint n = RegIR2 >> 12;
947: uint ea;
948: uint32 data;
949:
950: if ((RegIR & 0x3f) < 16) {
951: op_illegal(cpu);
952: return;
953: }
954:
955: ea = cea_data_32(cpu);
956: if ((RegIR2 & 0x0800) == 0) {
957: // <ea>,Rn
958: CYCLE(7);
959: data = m68030_read_32_fc(cpu, ea);
960: RegR(n) = data;
961: } else {
962: // Rn,<ea>
963: CYCLE2(5, 6);
964: data = RegR(n);
965: m68030_write_32_fc(cpu, ea, data);
966: }
967: }
968:
969: // %0000_111011_mmmrrr CAS.L Dc,Du,<ea>
970: // %0000_111011_111100 CAS2.L Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
971: OP_DEF(cas_l)
972: {
973: uint n = RegIR & 0x3f;
974:
975: if (n == 0x3c) {
976: // CAS2.L Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
977: RegIR2 = m68030_fetch_16(cpu);
978: uint32 ir3 = m68030_fetch_16(cpu);
979: uint c1 = RegIR2 & 7;
980: uint u1 = (RegIR2 >> 6) & 7;
981: uint r1 = RegIR2 >> 12;
982: uint c2 = ir3 & 7;
983: uint u2 = (ir3 >> 6) & 7;
984: uint r2 = ir3 >> 12;
985: uint32 dc1 = RegD(c1);
986: uint32 du1 = RegD(u1);
987: uint32 ea1 = RegR(r1);
988: uint32 dc2 = RegD(c2);
989: uint32 du2 = RegD(u2);
990: uint32 ea2 = RegR(r2);
991:
992: uint32 dst1 = m68030_read_32(cpu, ea1);
993: uint32 dst2 = m68030_read_32(cpu, ea2);
994: acc_cmp_32(cpu, dc1, dst1);
995: if (CCR.IsZ()) {
996: acc_cmp_32(cpu, dc2, dst2);
997: if (CCR.IsZ()) {
998: // 更新オペランド -> デスティネーション
999: CYCLE2(0, 2); // これは成功時の追加分
1000: m68030_write_32(cpu, ea1, du1);
1001: m68030_write_32(cpu, ea2, du2);
1002: }
1003: }
1004: // デスティネーション -> 比較オペランド
1005: CYCLE(24); // 本当はこれは最大値
1006: RegD(c1) = dst1;
1007: RegD(c2) = dst2;
1008: } else {
1009: // CAS.L Dc,Du,<ea>
1010: RegIR2 = m68030_fetch_16(cpu);
1011: uint c = RegIR2 & 7;
1012: uint u = (RegIR2 >> 6) & 7;
1013: uint32 dc = RegD(c);
1014: uint32 du = RegD(u);
1015: uint ea = cea_data_32(cpu);
1016: uint32 dst = m68030_read_32(cpu, ea);
1017:
1018: acc_cmp_32(cpu, dc, dst);
1019: if (CCR.IsZ()) {
1020: // 等しければ、Du -> dst
1021: CYCLE(13);
1022: m68030_write_32(cpu, ea, du);
1023: } else {
1024: // そうでなければ、dst -> Dc
1025: CYCLE(11);
1026: RegD(c) = dst;
1027: }
1028: }
1029: }
1030:
1031: // %0001_xxx000_mmmrrr MOVE.B <ea>,Dx
1032: OP_DEF(move_b_ea_dn)
1033: {
1034: CYCLE(2);
1035: uint32 data = fea_all_8(cpu);
1036: acc_move_8(cpu, data);
1037: RegDX = (RegDX & 0xffffff00) | data;
1038: }
1039:
1040: // %0001_xxx010_mmmrrr MOVE.B <ea>,(Ax)
1041: OP_DEF(move_b_ea_anin)
1042: {
1043: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1044: CYCLE2(4, 5);
1045: uint32 data = fea_all_8(cpu);
1046: uint32 ea = cea_anin(cpu, RegIRX);
1047: acc_move_8(cpu, data);
1048: m68030_write_8(cpu, ea, data);
1049: }
1050:
1051: // %0001_xxx011_mmmrrr MOVE.B <ea>,(Ax)+
1052: OP_DEF(move_b_ea_anpi)
1053: {
1054: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1055: CYCLE2(4, 5);
1056: uint32 data = fea_all_8(cpu);
1057: uint32 ea = cea_anpi_8(cpu, RegIRX);
1058: acc_move_8(cpu, data);
1059: m68030_write_8(cpu, ea, data);
1060: }
1061:
1062: // %0001_xxx100_mmmrrr MOVE.B <ea>,-(Ax)
1063: OP_DEF(move_b_ea_anpd)
1064: {
1065: // 実際にはソースがレジスタなら (4, 4)、メモリなら (4, 5)
1066: CYCLE2(4, 5);
1067: uint32 data = fea_all_8(cpu);
1068: uint32 ea = cea_anpd_8(cpu, RegIRX);
1069: acc_move_8(cpu, data);
1070: m68030_write_8(cpu, ea, data);
1071: }
1072:
1073: // %0001_xxx101_mmmrrr MOVE.B <ea>,d16(Ax)
1074: OP_DEF(move_b_ea_andi)
1075: {
1076: CYCLE2(4, 5);
1077: uint32 data = fea_all_8(cpu);
1078: uint32 ea = cea_andi(cpu, RegIRX);
1079: acc_move_8(cpu, data);
1080: m68030_write_8(cpu, ea, data);
1081: }
1082:
1083: // %0001_xxx110_mmmrrr MOVE.B <ea>,(Ax,IX)
1084: OP_DEF(move_b_ea_anix)
1085: {
1086: // XXX 実際にはdstのフォーマットによって(8,9)-(20,23)
1087: CYCLE2(16, 18);
1088: uint32 data = fea_all_8(cpu);
1089: uint32 ea = cea_anix(cpu, RegIRX);
1090: acc_move_8(cpu, data);
1091: m68030_write_8(cpu, ea, data);
1092: }
1093:
1094: // %0001_000111_mmmrrr MOVE.B <ea>,Abs.W
1095: OP_DEF(move_b_ea_absw)
1096: {
1097: CYCLE2(4, 5);
1098: uint32 data = fea_all_8(cpu);
1099: uint32 ea = cea_absw(cpu);
1100: acc_move_8(cpu, data);
1101: m68030_write_8(cpu, ea, data);
1102: }
1103:
1104: // %0001_001111_mmmrrr MOVE.B <ea>,Abs.L
1105: OP_DEF(move_b_ea_absl)
1106: {
1107: CYCLE2(6, 7);
1108: uint32 data = fea_all_8(cpu);
1109: uint32 ea = cea_absl(cpu);
1110: acc_move_8(cpu, data);
1111: m68030_write_8(cpu, ea, data);
1112: }
1113:
1114: // %0010_xxx000_mmmrrr MOVE.L <ea>,Dx
1115: OP_DEF(move_l_ea_dn)
1116: {
1117: CYCLE(2);
1118: uint32 data = fea_all_32(cpu);
1119: acc_move_32(cpu, data);
1120: RegDX = data;
1121: }
1122:
1123: // %0010_xxx001_mmmrrr MOVEA.L <ea>,Ax
1124: OP_DEF(movea_l)
1125: {
1126: CYCLE(2);
1127: uint32 data = fea_all_32(cpu);
1128: RegAX = data;
1129: }
1130:
1131: // %0010_xxx010_mmmrrr MOVE.L <ea>,(Ax)
1132: OP_DEF(move_l_ea_anin)
1133: {
1134: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1135: CYCLE2(4, 5);
1136: uint32 data = fea_all_32(cpu);
1137: uint32 ea = cea_anin(cpu, RegIRX);
1138: acc_move_32(cpu, data);
1139: m68030_write_32(cpu, ea, data);
1140: }
1141:
1142: // %0010_xxx011_mmmrrr MOVE.L <ea>,(Ax)+
1143: OP_DEF(move_l_ea_anpi)
1144: {
1145: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1146: CYCLE2(4, 5);
1147: uint32 data = fea_all_32(cpu);
1148: uint32 ea = cea_anpi_32(cpu, RegIRX);
1149: acc_move_32(cpu, data);
1150: m68030_write_32(cpu, ea, data);
1151: }
1152:
1153: // %0010_xxx100_mmmrrr MOVE.L <ea>,-(Ax)
1154: OP_DEF(move_l_ea_anpd)
1155: {
1156: // 実際にはソースがレジスタなら (4, 4)、メモリなら (4, 5)
1157: CYCLE2(4, 5);
1158: uint32 data = fea_all_32(cpu);
1159: uint32 ea = cea_anpd_32(cpu, RegIRX);
1160: acc_move_32(cpu, data);
1161: m68030_write_32(cpu, ea, data);
1162: }
1163:
1164: // %0010_xxx101_mmmrrr MOVE.L <ea>,d16(Ax)
1165: OP_DEF(move_l_ea_andi)
1166: {
1167: CYCLE2(4, 5);
1168: uint32 data = fea_all_32(cpu);
1169: uint32 ea = cea_andi(cpu, RegIRX);
1170: acc_move_32(cpu, data);
1171: m68030_write_32(cpu, ea, data);
1172: }
1173:
1174: // %0010_xxx110_mmmrrr MOVE.L <ea>,(Ax,IX)
1175: OP_DEF(move_l_ea_anix)
1176: {
1177: // XXX 実際にはdstのフォーマットによって(8,9)-(20,23)
1178: CYCLE2(16, 18);
1179: uint32 data = fea_all_32(cpu);
1180: uint32 ea = cea_anix(cpu, RegIRX);
1181: acc_move_32(cpu, data);
1182: m68030_write_32(cpu, ea, data);
1183: }
1184:
1185: // %0010_000111_mmmrrr MOVE.L <ea>,Abs.W
1186: OP_DEF(move_l_ea_absw)
1187: {
1188: CYCLE2(4, 5);
1189: uint32 data = fea_all_32(cpu);
1190: uint32 ea = cea_absw(cpu);
1191: acc_move_32(cpu, data);
1192: m68030_write_32(cpu, ea, data);
1193: }
1194:
1195: // %0010_001111_mmmrrr MOVE.L <ea>,Abs.L
1196: OP_DEF(move_l_ea_absl)
1197: {
1198: CYCLE2(6, 7);
1199: uint32 data = fea_all_32(cpu);
1200: uint32 ea = cea_absl(cpu);
1201: acc_move_32(cpu, data);
1202: m68030_write_32(cpu, ea, data);
1203: }
1204:
1205: // %0011_xxx000_mmmrrr MOVE.W <ea>,Dx
1206: OP_DEF(move_w_ea_dn)
1207: {
1208: CYCLE(2);
1209: uint32 data = fea_all_16(cpu);
1210: acc_move_16(cpu, data);
1211: RegDX = (RegDX & 0xffff0000) | data;
1212: }
1213:
1214: // %0011_xxx001_mmmrrr MOVEA.W <ea>,Ax
1215: OP_DEF(movea_w)
1216: {
1217: CYCLE(2);
1218: uint32 data = (int32)(int16)fea_all_16(cpu);
1219: RegAX = data;
1220: }
1221:
1222: // %0011_xxx010_mmmrrr MOVE.W <ea>,(Ax)
1223: OP_DEF(move_w_ea_anin)
1224: {
1225: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1226: CYCLE2(4, 5);
1227: uint32 data = fea_all_16(cpu);
1228: uint32 ea = cea_anin(cpu, RegIRX);
1229: acc_move_16(cpu, data);
1230: m68030_write_16(cpu, ea, data);
1231: }
1232:
1233: // %0011_xxx011_mmmrrr MOVE.W <ea>,(Ax)+
1234: OP_DEF(move_w_ea_anpi)
1235: {
1236: // 実際にはソースがレジスタなら (3, 4)、メモリなら (4, 5)
1237: CYCLE2(4, 5);
1238: uint32 data = fea_all_16(cpu);
1239: uint32 ea = cea_anpi_16(cpu, RegIRX);
1240: acc_move_16(cpu, data);
1241: m68030_write_16(cpu, ea, data);
1242: }
1243:
1244: // %0011_xxx100_mmmrrr MOVE.W <ea>,-(Ax)
1245: OP_DEF(move_w_ea_anpd)
1246: {
1247: // 実際にはソースがレジスタなら (4, 4)、メモリなら (4, 5)
1248: CYCLE2(4, 5);
1249: uint32 data = fea_all_16(cpu);
1250: uint32 ea = cea_anpd_16(cpu, RegIRX);
1251: acc_move_16(cpu, data);
1252: m68030_write_16(cpu, ea, data);
1253: }
1254:
1255: // %0011_xxx101_mmmrrr MOVE.W <ea>,d16(Ax)
1256: OP_DEF(move_w_ea_andi)
1257: {
1258: CYCLE2(4, 5);
1259: uint32 data = fea_all_16(cpu);
1260: uint32 ea = cea_andi(cpu, RegIRX);
1261: acc_move_16(cpu, data);
1262: m68030_write_16(cpu, ea, data);
1263: }
1264:
1265: // %0011_xxx110_mmmrrr MOVE.W <ea>,(Ax,IX)
1266: OP_DEF(move_w_ea_anix)
1267: {
1268: // XXX 実際にはdstのフォーマットによって(8,9)-(20,23)
1269: CYCLE2(16, 18);
1270: uint32 data = fea_all_16(cpu);
1271: uint32 ea = cea_anix(cpu, RegIRX);
1272: acc_move_16(cpu, data);
1273: m68030_write_16(cpu, ea, data);
1274: }
1275:
1276: // %0011_000111_mmmrrr MOVE.W <ea>,Abs.W
1277: OP_DEF(move_w_ea_absw)
1278: {
1279: CYCLE2(4, 5);
1280: uint32 data = fea_all_16(cpu);
1281: uint32 ea = cea_absw(cpu);
1282: acc_move_16(cpu, data);
1283: m68030_write_16(cpu, ea, data);
1284: }
1285:
1286: // %0011_001111_mmmrrr MOVE.W <ea>,Abs.L
1287: OP_DEF(move_w_ea_absl)
1288: {
1289: CYCLE2(6, 7);
1290: uint32 data = fea_all_16(cpu);
1291: uint32 ea = cea_absl(cpu);
1292: acc_move_16(cpu, data);
1293: m68030_write_16(cpu, ea, data);
1294: }
1295:
1296: // %0100_000000_mmmrrr NEGX.B <ea>
1297: OP_DEF(negx_b)
1298: {
1299: uint n = RegIR & 0x3f;
1300:
1301: if (n < 8) {
1302: // NEGX.B Dn
1303: CYCLE(2);
1304: uint32 data = RegD(n) & 0xff;
1305: data = acc_subx_8(cpu, data, 0);
1306: RegD(n) = (RegD(n) & 0xffffff00) | data;
1307: } else if (n < 16) {
1308: op_illegal(cpu);
1309: } else {
1310: // NEGX.B <ea>
1311: CYCLE2(3, 4);
1312: uint32 ea = cea_data_8(cpu);
1313: uint32 data = m68030_read_8(cpu, ea);
1314: data = acc_subx_8(cpu, data, 0);
1315: m68030_write_8(cpu, ea, data);
1316: }
1317: }
1318:
1319: // %0100_000001_mmmrrr NEGX.W <ea>
1320: OP_DEF(negx_w)
1321: {
1322: uint n = RegIR & 0x3f;
1323:
1324: if (n < 8) {
1325: // NEGX.W Dn
1326: CYCLE(2);
1327: uint32 data = RegD(n) & 0xffff;
1328: data = acc_subx_16(cpu, data, 0);
1329: RegD(n) = (RegD(n) & 0xffff0000) | data;
1330: } else if (n < 16) {
1331: op_illegal(cpu);
1332: } else {
1333: // NEGX.W <ea>
1334: CYCLE2(3, 4);
1335: uint32 ea = cea_data_16(cpu);
1336: uint32 data = m68030_read_16(cpu, ea);
1337: data = acc_subx_16(cpu, data, 0);
1338: m68030_write_16(cpu, ea, data);
1339: }
1340: }
1341:
1342: // %0100_000010_mmmrrr NEGX.L <ea>
1343: OP_DEF(negx_l)
1344: {
1345: uint n = RegIR & 0x3f;
1346:
1347: if (n < 8) {
1348: // NEGX.L Dn
1349: CYCLE(2);
1350: RegD(n) = acc_subx_32(cpu, RegD(n), 0);
1351: } else if (n < 16) {
1352: op_illegal(cpu);
1353: } else {
1354: // NEGX.L <ea>
1355: CYCLE2(3, 4);
1356: uint32 ea = cea_data_32(cpu);
1357: uint32 data = m68030_read_32(cpu, ea);
1358: data = acc_subx_32(cpu, data, 0);
1359: m68030_write_32(cpu, ea, data);
1360: }
1361: }
1362:
1363: // %0100_000011_mmmrrr MOVE.W SR,<ea>
1364: OP_DEF(move_sr_ea)
1365: {
1366: SUPERVISOR_OP;
1367:
1368: uint n = RegIR & 0x3f;
1369: if (n < 8) {
1370: // MOVE.W SR,Dn
1371: CYCLE(4);
1372: RegD(n) = (RegD(n) & 0xffff0000) | RegSR;
1373: } else {
1374: // MOVE.W SR,<ea>
1375: CYCLE2(4, 5);
1376: uint32 ea = cea_data_16(cpu);
1377: m68030_write_16(cpu, ea, RegSR);
1378: }
1379: }
1380:
1381: // %0100_xxx100_mmmrrr CHK.L <ea>,Dx
1382: OP_DEF(chk_l)
1383: {
1384: uint32 dst = RegDX;
1385: acc_move_32(cpu, dst);
1386: if (CCR.IsN()) {
1387: // これは最大値で次の条件式が成立した時の値なので、
1388: // 実際にはこれより小さい確定した値のはずだけど。
1389: CYCLE2(28, 30);
1390: m68030_exception(cpu, M68K_EXCEP_CHK);
1391: return;
1392: }
1393: // 本当はこうじゃないけど、とりあえず
1394: uint32 src = fea_data_32(cpu);
1395: if ((int32)dst > (int32)src) {
1396: CYCLE2(28, 30);
1397: CCR.ClrN();
1398: m68030_exception(cpu, M68K_EXCEP_CHK);
1399: return;
1400: }
1401: CYCLE(8);
1402: }
1403:
1404: // %0100_xxx110_mmmrrr CHK.W <ea>,Dx
1405: OP_DEF(chk_w)
1406: {
1407: uint32 dst = RegDX & 0xffff;
1408: acc_move_16(cpu, dst);
1409: if (CCR.IsN()) {
1410: // これは最大値で次の条件式が成立した時の値なので、
1411: // 実際にはこれより小さい確定した値のはずだけど。
1412: CYCLE2(28, 30);
1413: m68030_exception(cpu, M68K_EXCEP_CHK);
1414: return;
1415: }
1416: // 本当はこうじゃないけど、とりあえず
1417: uint32 src = fea_data_16(cpu);
1418: if ((int16)dst > (int16)src) {
1419: CYCLE2(28, 30);
1420: CCR.ClrN();
1421: m68030_exception(cpu, M68K_EXCEP_CHK);
1422: return;
1423: }
1424: CYCLE(8);
1425: }
1426:
1427: // %0100_xxx111_mmmrrr LEA.L <ea>,Ax
1428: // %0100_100111_000yyy EXTB.L Dy
1429: OP_DEF(lea)
1430: {
1431: uint n = RegIR & 0x3f;
1432:
1433: if (n < 8) {
1434: // EXTB.L Dy
1435: CYCLE(4);
1436: RegDY = (int32)(int8)(RegDY & 0xff);
1437: acc_move_32(cpu, RegDY);
1438: } else {
1439: // LEA.L <ea>,Ax
1440: CYCLE(2);
1441: RegAX = cea_ctrl(cpu);
1442: }
1443: }
1444:
1445: // %0100_001000_mmmrrr CLR.B <ea>
1446: OP_DEF(clr_b)
1447: {
1448: uint n = RegIR & 0x3f;
1449:
1450: if (n < 8) {
1451: // CLR.B Dn
1452: CYCLE(2);
1453: RegDY &= 0xffffff00;
1454: acc_move_8(cpu, 0);
1455: } else {
1456: // CLR.B <ea>
1457: CYCLE2(3, 4);
1458: uint32 ea = cea_data_8(cpu);
1459: acc_move_8(cpu, 0);
1460: m68030_write_8(cpu, ea, 0);
1461: }
1462: }
1463:
1464: // %0100_001001_mmmrrr CLR.W <ea>
1465: OP_DEF(clr_w)
1466: {
1467: uint n = RegIR & 0x3f;
1468:
1469: if (n < 8) {
1470: // CLR.W Dn
1471: CYCLE(2);
1472: RegDY &= 0xffff0000;
1473: acc_move_16(cpu, 0);
1474: } else {
1475: // CLR.W <ea>
1476: CYCLE2(3, 4);
1477: uint32 ea = cea_data_16(cpu);
1478: acc_move_16(cpu, 0);
1479: m68030_write_16(cpu, ea, 0);
1480: }
1481: }
1482:
1483: // %0100_001010_mmmrrr CLR.L <ea>
1484: OP_DEF(clr_l)
1485: {
1486: uint n = RegIR & 0x3f;
1487:
1488: if (n < 8) {
1489: // CLR.L Dn
1490: CYCLE(2);
1491: RegDY = 0;
1492: acc_move_32(cpu, 0);
1493: } else {
1494: // CLR.L <ea>
1495: CYCLE2(3, 4);
1496: uint32 ea = cea_data_32(cpu);
1497: acc_move_32(cpu, 0);
1498: m68030_write_32(cpu, ea, 0);
1499: }
1500: }
1501:
1502: // %0100_001011_mmmrrr MOVE.W CCR,<ea>
1503: OP_DEF(move_ccr_ea)
1504: {
1505: uint n = RegIR & 0x3f;
1506:
1507: // 転送は16ビットで行われ、上位バイトと未実装ビットは %0 になる。
1508: if (n < 8) {
1509: // MOVE.W CCR,Dn
1510: CYCLE(4);
1511: RegD(n) = (RegD(n) & 0xffff0000) | CCR.Get();
1512: } else if (n < 16) {
1513: // MOVE.W CCR,An はない
1514: op_illegal(cpu);
1515: } else {
1516: // MOVE.W CCR,<ea>
1517: CYCLE2(4, 5);
1518: uint32 ea = cea_data_16(cpu);
1519: m68030_write_16(cpu, ea, CCR.Get());
1520: }
1521: }
1522:
1523: // %0100_010000_mmmrrr NEG.B <ea>
1524: OP_DEF(neg_b)
1525: {
1526: uint n = RegIR & 0x3f;
1527:
1528: if (n < 8) {
1529: // NEG.B Dn
1530: CYCLE(2);
1531: uint32 data = acc_sub_8(cpu, RegD(n) & 0xff, 0);
1532: RegD(n) = (RegD(n) & 0xffffff00) | data;
1533: } else {
1534: // NEG.B <ea>
1535: CYCLE2(3, 4);
1536: uint32 ea = cea_data_8(cpu);
1537: uint32 data = m68030_read_8(cpu, ea);
1538: data = acc_sub_8(cpu, data, 0);
1539: m68030_write_8(cpu, ea, data);
1540: }
1541: }
1542:
1543: // %0100_010001_mmmrrr NEG.W <ea>
1544: OP_DEF(neg_w)
1545: {
1546: uint n = RegIR & 0x3f;
1547:
1548: if (n < 8) {
1549: // NEG.W Dn
1550: CYCLE(2);
1551: uint32 data = acc_sub_16(cpu, RegD(n) & 0xffff, 0);
1552: RegD(n) = (RegD(n) & 0xffff0000) | data;
1553: } else {
1554: // NEG.W <ea>
1555: CYCLE2(3, 4);
1556: uint32 ea = cea_data_16(cpu);
1557: uint32 data = m68030_read_16(cpu, ea);
1558: data = acc_sub_16(cpu, data, 0);
1559: m68030_write_16(cpu, ea, data);
1560: }
1561: }
1562:
1563: // %0100_010010_mmmrrr NEG.L <ea>
1564: OP_DEF(neg_l)
1565: {
1566: uint n = RegIR & 0x3f;
1567:
1568: if (n < 8) {
1569: // NEG.L Dn
1570: CYCLE(2);
1571: RegD(n) = acc_sub_32(cpu, RegD(n), 0);
1572: } else {
1573: // NEG.L <ea>
1574: CYCLE2(3, 4);
1575: uint32 ea = cea_data_32(cpu);
1576: uint32 data = m68030_read_32(cpu, ea);
1577: data = acc_sub_32(cpu, data, 0);
1578: m68030_write_32(cpu, ea, data);
1579: }
1580: }
1581:
1582: // %0100_010011_mmmrrr MOVE.W <ea>,CCR
1583: OP_DEF(move_ea_ccr)
1584: {
1585: uint n = RegIR & 0x3f;
1586:
1587: if (n < 8) {
1588: // MOVE.W Dn,CCR
1589: CYCLE(4);
1590: uint32 data = RegD(n) & 0xff;
1591: CCR.Set(data);
1592: } else if (n < 16) {
1593: // MOVE.W An,CCR はない
1594: op_illegal(cpu);
1595: } else {
1596: // MOVE.W <ea>,CCR
1597: CYCLE(4);
1598: uint32 data = fea_data_16(cpu);
1599: CCR.Set(data);
1600: }
1601: }
1602:
1603: // %0100_011000_mmmrrr NOT.B <ea>
1604: OP_DEF(not_b)
1605: {
1606: uint n = RegIR & 0x3f;
1607:
1608: if (n < 8) {
1609: // NOT.B Dn
1610: CYCLE(2);
1611: uint32 data = (~RegD(n)) & 0xff;
1612: acc_move_8(cpu, data);
1613: RegD(n) = (RegD(n) & 0xffffff00) | data;
1614: } else {
1615: // NOT.B <ea>
1616: CYCLE2(3, 4);
1617: uint32 ea = cea_data_8(cpu);
1618: uint32 data = m68030_read_8(cpu, ea);
1619: data = (~data) & 0xff;
1620: acc_move_8(cpu, data);
1621: m68030_write_8(cpu, ea, data);
1622: }
1623: }
1624:
1625: // %0100_011001_mmmrrr NOT.W <ea>
1626: OP_DEF(not_w)
1627: {
1628: uint n = RegIR & 0x3f;
1629:
1630: if (n < 8) {
1631: // NOT.W Dn
1632: CYCLE(2);
1633: uint32 data = (~RegD(n)) & 0xffff;
1634: acc_move_16(cpu, data);
1635: RegD(n) = (RegD(n) & 0xffff0000) | data;
1636: } else {
1637: // NOT.W <ea>
1638: CYCLE2(3, 4);
1639: uint32 ea = cea_data_16(cpu);
1640: uint32 data = m68030_read_16(cpu, ea);
1641: data = (~data) & 0xffff;
1642: acc_move_16(cpu, data);
1643: m68030_write_16(cpu, ea, data);
1644: }
1645: }
1646:
1647: // %0100_011010_mmmrrr NOT.L <ea>
1648: OP_DEF(not_l)
1649: {
1650: uint n = RegIR & 0x3f;
1651:
1652: if (n < 8) {
1653: // NOT.L Dn
1654: CYCLE(2);
1655: RegD(n) = ~RegD(n);
1656: acc_move_32(cpu, RegD(n));
1657: } else {
1658: // NOT.L <ea>
1659: CYCLE2(3, 4);
1660: uint32 ea = cea_data_32(cpu);
1661: uint32 data = m68030_read_32(cpu, ea);
1662: data = ~data;
1663: acc_move_32(cpu, data);
1664: m68030_write_32(cpu, ea, data);
1665: }
1666: }
1667:
1668: // %0100_011011_mmmrrr MOVE.W <ea>,SR
1669: OP_DEF(move_ea_sr)
1670: {
1671: CYCLE2(8, 10);
1672: uint16 data = fea_data_16(cpu);
1673: m68030_set_sr(cpu, data);
1674: }
1675:
1676: // %0100_100000_mmmrrr NBCD.B <ea>
1677: // %0100_100000_001yyy LINK.L Ay,#<imm>
1678: OP_DEF(nbcd)
1679: {
1680: uint n = RegIR & 0x3f;
1681: int32 imm;
1682:
1683: if (n < 8) {
1684: // NBCD.B Dn
1685: CYCLE(6);
1686: uint32 dst = RegDY & 0xff;
1687: dst = acc_sbcd_8(cpu, dst, 0);
1688: RegDY = (RegDY & 0xffffff00) | dst;
1689: } else if (n == 0x0e) {
1690: // LINK.L A6,#<imm>
1691: CYCLE2(6, 7);
1692: // レジスタやスタックを変更する前にフェッチしないと、
1693: // ページフォルトで再実行できなくなる
1694: imm = m68030_fetch_32(cpu);
1695: // ページフォルトに備えて保存する
1696: m68030_save_reg_pd(cpu, 7);
1697: m68030_push_32(cpu, RegA(6));
1698: RegA(6) = RegA(7);
1699: RegA(7) += imm;
1700: } else if (n < 16) {
1701: // LINK.L An,#<imm>
1702: CYCLE2(6, 7);
1703: // レジスタやスタックを変更する前にフェッチしないと、
1704: // ページフォルトで再実行できなくなる
1705: imm = m68030_fetch_32(cpu);
1706: // ページフォルトに備えて保存する
1707: m68030_save_reg_pd(cpu, 7);
1708: m68030_push_32(cpu, RegAY);
1709: RegAY = RegA(7);
1710: RegA(7) += imm;
1711: } else {
1712: // NBCD.B <ea>
1713: CYCLE(6);
1714: uint32 ea = cea_data_8(cpu);
1715: uint32 dst = m68030_read_8(cpu, ea);
1716: dst = acc_sbcd_8(cpu, dst, 0);
1717: m68030_write_8(cpu, ea, dst);
1718: }
1719: }
1720:
1721: // %0100_100001_000yyy SWAP.W Dy
1722: // %0100_100001_001nnn BKPT #<imm>
1723: // %0100_100001_mmmrrr PEA.L <ea>
1724: OP_DEF(pea)
1725: {
1726: uint n = RegIR & 0x3f;
1727:
1728: if (n < 8) {
1729: // SWAP.W Dy
1730: CYCLE(4);
1731: RegD(n) = (RegD(n) << 16) | (RegD(n) >> 16);
1732: acc_move_32(cpu, RegD(n));
1733: } else if (n < 16) {
1734: // BKPT #<imm>
1735: // ブレークポイント・アクノリッジサイクルに応答するデバイスはないので
1736: // 常に不当命令にする。
1737: CYCLE(9); // ?
1738: op_illegal(cpu);
1739: } else {
1740: // PEA.L <ea>
1741: CYCLE(4);
1742: uint32 ea = cea_ctrl(cpu);
1743: // ページフォルトに備えて保存する
1744: m68030_save_reg_pd(cpu, 7);
1745: m68030_push_32(cpu, ea);
1746: }
1747: }
1748:
1749: // MOVEM.[WL] <list>,<ea> の共通部分。
1750: // bytesize は1レジスタ分のサイズ、.Wなら2、.Lなら4。
1751: template<int bytesize> void
1752: ops_movem_list_ea(m68kcpu *cpu)
1753: {
1754: uint32 ea;
1755: int regcount;
1756:
1757: // 不当な第1ワードを弾く
1758: #define INVALID(x) (0xffULL << (56 - ((x) * 8)))
1759: const uint64 valid =
1760: INVALID(0) // Dn
1761: | INVALID(1) // An
1762: | INVALID(3) // (An)+
1763: | 0x3fL; // (PC)...
1764: if ((int64)(valid << (RegIR & 0x3f)) < 0) {
1765: op_illegal(cpu);
1766: return;
1767: }
1768:
1769: // 第2ワードは EA が正当な場合のみ EA より先にフェッチ
1770: RegIR2 = m68030_fetch_16(cpu);
1771:
1772: // EA 取得。MOVEM だけ別対応
1773: // | M -WXZ | MOVEM list,<ea>
1774: // だが、不当 EA はすでに弾いてあるので cea_data でいい
1775: if (bytesize == 2) {
1776: ea = cea_data_16(cpu);
1777: } else {
1778: ea = cea_data_32(cpu);
1779: }
1780:
1781: regcount = 0;
1782: uint list = RegIR2;
1783: if (eamode(RegIR) == 4/*-(An)*/) {
1784: // -(An) の場合 reglist の格納順が逆(転送順は LSB から)
1785: // bit15 bit0
1786: // D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7
1787: while (list) {
1788: int ctz = __builtin_ctz(list);
1789: if (bytesize == 2) {
1790: m68030_write_16(cpu, ea, RegR(15 - ctz) & 0xffff);
1791: } else {
1792: m68030_write_32(cpu, ea, RegR(15 - ctz));
1793: }
1794: ea -= bytesize;
1795: regcount++;
1796: // 処理した最下位ビットを落とす
1797: list &= list - 1;
1798: }
1799: // ea は一つ行き過ぎるので補正
1800: RegAY = ea + bytesize;
1801: } else {
1802: // LSB 側から転送
1803: // bit15 bit0
1804: // A7 A6 A5 A4 A4 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1805: while (list) {
1806: int ctz = __builtin_ctz(list);
1807: if (bytesize == 2) {
1808: m68030_write_16(cpu, ea, RegR(ctz) & 0xffff);
1809: } else {
1810: m68030_write_32(cpu, ea, RegR(ctz));
1811: }
1812: ea += bytesize;
1813: regcount++;
1814: // 処理した最下位ビットを落とす
1815: list &= list - 1;
1816: }
1817: }
1818:
1819: CYCLE(4 + 2 * regcount);
1820: }
1821:
1822: // %0100_100010_000yyy EXT.W Dy
1823: // %0100_100010_mmmrrr MOVEM.W <list>,<ea>
1824: OP_DEF(movem_w_mem)
1825: {
1826: uint n = RegIR & 0x3f;
1827:
1828: if (n < 8) {
1829: // EXT.W Dy
1830: CYCLE(4);
1831: uint16 data = (int16)(int8)(RegDY & 0xff);
1832: acc_move_16(cpu, data);
1833: RegDY = (RegDY & 0xffff0000) | data;
1834: } else {
1835: // MOVEM.W <list>,<ea>
1836: ops_movem_list_ea<2>(cpu);
1837: }
1838: }
1839:
1840: // %0100_100011_000yyy EXT.L Dy
1841: // %0100_100011_mmmrrr MOVEM.L <list>,<ea>
1842: OP_DEF(movem_l_mem)
1843: {
1844: uint n = RegIR & 0x3f;
1845:
1846: if (n < 8) {
1847: // EXT.L Dy
1848: CYCLE(4);
1849: RegDY = (int32)(int16)(RegDY & 0x0000ffff);
1850: acc_move_32(cpu, RegDY);
1851: } else {
1852: // MOVEM.L <list>,<ea>
1853: ops_movem_list_ea<4>(cpu);
1854: }
1855: }
1856:
1857: // %0100_101000_mmmrrr TST.B <ea>
1858: OP_DEF(tst_b)
1859: {
1860: CYCLE(2);
1861: uint32 data = fea_all_8(cpu);
1862: acc_move_8(cpu, data);
1863: }
1864:
1865: // %0100_101001_mmmrrr TST.W <ea>
1866: OP_DEF(tst_w)
1867: {
1868: CYCLE(2);
1869: uint32 data = fea_all_16(cpu);
1870: acc_move_16(cpu, data);
1871: }
1872:
1873: // %0100_101010_mmmrrr TST.L <ea>
1874: OP_DEF(tst_l)
1875: {
1876: CYCLE(2);
1877: uint32 data = fea_all_32(cpu);
1878: acc_move_32(cpu, data);
1879: }
1880:
1881: // %0100_101011_mmmrrr TAS.B <ea>
1882: // %0100_101011_111100 ILLEGAL
1883: OP_DEF(tas)
1884: {
1885: uint n = RegIR & 0x3f;
1886:
1887: if (n < 8) {
1888: // TAS.B Dn
1889: // リード・モディファイ・ライトという概念はない
1890: CYCLE(4);
1891: uint32 data = RegD(n);
1892: acc_move_8(cpu, data);
1893: RegD(n) |= 0x80;
1894: } else if (n == 0x3c) {
1895: // ILLEGAL
1896: op_illegal(cpu);
1897: } else {
1898: // TAS.B <ea>
1899: // リード・モディファイ・ライトという概念はない
1900: CYCLE(12);
1901: uint32 ea = cea_data_8(cpu);
1902: uint32 data = m68030_read_8(cpu, ea);
1903: acc_move_8(cpu, data);
1904: m68030_write_8(cpu, ea, (data | 0x80));
1905: }
1906: }
1907:
1908: // %0100_110000_mmmrrr MUL{U,S}.L <ea>,Dl
1909: OP_DEF(mul)
1910: {
1911: // 2ワード目
1912: // %0LLL_Ss0000_000HHH
1913: // +++ || +++- Dh
1914: // | |+------------ %1:64bit, %0:32bit
1915: // | +------------- %1:MULS, %0:MULU
1916: // +---------------- Dl
1917: RegIR2 = m68030_fetch_16(cpu);
1918: int h = RegIR2 & 7;
1919: int l = (RegIR2 >> 12) & 7;
1920:
1921: CYCLE(44); // XXX これは本当は最大値だけど
1922: switch ((RegIR2 >> 10) & 3) {
1923: case 0:
1924: {
1925: // MULU.L <ea>,Dl
1926: uint32 src = fea_data_32(cpu);
1927: uint32 dst = RegD(l);
1928: RegD(l) = acc_mulu_32(cpu, src, dst);
1929: break;
1930: }
1931:
1932: case 1:
1933: {
1934: // MULU.L <ea>,Dh:Dl
1935: uint32 src = fea_data_32(cpu);
1936: uint32 dst = RegD(l);
1937: uint64 res = acc_mulu_64(cpu, src, dst);
1938: // h == l の時は未定義なので考えない。
1939: RegD(h) = res >> 32;
1940: RegD(l) = res;
1941: break;
1942: }
1943:
1944: case 2:
1945: {
1946: // MULS.L <ea>,Dl
1947: uint32 src = fea_data_32(cpu);
1948: uint32 dst = RegD(l);
1949: RegD(l) = acc_muls_32(cpu, src, dst);
1950: break;
1951: }
1952:
1953: case 3:
1954: {
1955: // MULS.L <ea>,Dh:Dl
1956: uint32 src = fea_data_32(cpu);
1957: uint32 dst = RegD(l);
1958: uint64 res = acc_muls_64(cpu, src, dst);
1959: // h == l の時は未定義なので考えない。
1960: RegD(h) = res >> 32;
1961: RegD(l) = res;
1962: break;
1963: }
1964:
1965: default:
1966: __unreachable();
1967: }
1968: }
1969:
1970: // %0100_110001_mmmrrr DIVU.L <ea>,Dq
1971: // %0100_110001_mmmrrr DIVU.L <ea>,Dr:Dq
1972: // %0100_110001_mmmrrr DIVUL.L <ea>,Dr:Dq
1973: // %0100_110001_mmmrrr DIVS.L <ea>,Dq
1974: // %0100_110001_mmmrrr DIVS.L <ea>,Dr:Dq
1975: // %0100_110001_mmmrrr DIVSL.L <ea>,Dr:Dq
1976: OP_DEF(div)
1977: {
1978: // 2ワード目
1979: // %0QQQ_Ss0000_000RRR
1980: // +++ || +++- Dr
1981: // | |+------------ %1:64bit, %0:32bit
1982: // | +------------- %1:DIVS, %0:DIVU
1983: // +---------------- Dq
1984: RegIR2 = m68030_fetch_16(cpu);
1985: int r = RegIR2 & 7;
1986: int q = (RegIR2 >> 12) & 7;
1987:
1988: switch ((RegIR2 >> 10) & 3) {
1989: case 0:
1990: {
1991: // DIVU.L <ea>,Dq
1992: // DIVUL.L <ea>,Dr:Dq
1993: CYCLE(78); // XXX これは本当は最大値だけど
1994: uint32 src = fea_data_32(cpu);
1995: uint32 dst = RegD(q);
1996: uint32 quo;
1997: uint32 rem;
1998: if (acc_divu_32_32(cpu, src, dst, &quo, &rem)) {
1999: // r == q の場合 quo が残るので、rem を先に書く
2000: RegD(r) = rem;
2001: RegD(q) = quo;
2002: }
2003: break;
2004: }
2005:
2006: case 1: // DIVU.L <ea>,Dr:Dq
2007: {
2008: CYCLE(78); // XXX これは本当は最大値だけど
2009: uint32 src = fea_data_32(cpu);
2010: uint64 dst = (((uint64)RegD(r)) << 32) | RegD(q);
2011: uint32 quo;
2012: uint32 rem;
2013: if (acc_divu_64_32(cpu, src, dst, &quo, &rem)) {
2014: RegD(r) = rem;
2015: RegD(q) = quo;
2016: }
2017: break;
2018: }
2019:
2020: case 2:
2021: {
2022: // DIVS.L <ea>,Dq
2023: // DIVSL.L <ea>,Dr:Dq
2024: CYCLE(90); // XXX これは本当は最大値だけど
2025: uint32 src = fea_data_32(cpu);
2026: uint32 dst = RegD(q);
2027: uint32 quo;
2028: uint32 rem;
2029: if (acc_divs_32_32(cpu, src, dst, &quo, &rem)) {
2030: // r == q の場合 quo が残るので、rem を先に書く
2031: RegD(r) = rem;
2032: RegD(q) = quo;
2033: }
2034: break;
2035: }
2036:
2037: case 3: // DIVSL.L
2038: {
2039: CYCLE(90); // XXX これは本当は最大値だけど
2040: uint32 src = fea_data_32(cpu);
2041: uint64 dst = (((uint64)RegD(r)) << 32) | RegD(q);
2042: uint32 quo;
2043: uint32 rem;
2044: if (acc_divs_64_32(cpu, src, dst, &quo, &rem)) {
2045: RegD(r) = rem;
2046: RegD(q) = quo;
2047: }
2048: break;
2049: }
2050:
2051: default:
2052: __unreachable();
2053: }
2054: }
2055:
2056: template<int bytesize> void
2057: ops_movem_ea_list(m68kcpu *cpu)
2058: {
2059: uint32 ea;
2060: int regcount;
2061: bool anpi = false;
2062:
2063: RegIR2 = m68030_fetch_16(cpu);
2064:
2065: // EA 取得。MOVEM だけ別対応
2066: // | M+ WXZP | MOVEM <ea>,list
2067: switch (eamode(RegIR)) {
2068: case 2: // (An)
2069: ea = cea_anin(cpu, eanum(RegIR));
2070: break;
2071: case 3: // (An)+
2072: if (bytesize == 2) {
2073: ea = cea_anpi_16(cpu, eanum(RegIR));
2074: } else {
2075: ea = cea_anpi_32(cpu, eanum(RegIR));
2076: }
2077: anpi = true;
2078: break;
2079: case 5: // d16(An)
2080: ea = cea_andi(cpu, eanum(RegIR));
2081: break;
2082: case 6: // (An,IX)
2083: ea = cea_anix(cpu, eanum(RegIR));
2084: break;
2085: case 7:
2086: switch (eanum(RegIR)) {
2087: case 0: // Abs.W
2088: ea = cea_absw(cpu);
2089: break;
2090: case 1: // Abs.L
2091: ea = cea_absl(cpu);
2092: break;
2093: case 2: // d16(PC)
2094: ea = cea_pcdi(cpu);
2095: break;
2096: case 3: // (PC,IX)
2097: ea = cea_pcix(cpu);
2098: break;
2099: default:
2100: op_illegal(cpu);
2101: return;
2102: }
2103: break;
2104: default:
2105: op_illegal(cpu);
2106: return;
2107: }
2108:
2109: // XXX レジスタリストに表れて、ea オペランドに出てくる
2110: // レジスタはデータレジスタIX も含めて全部保存しておく必要がある。
2111:
2112: regcount = 0;
2113: uint list = RegIR2;
2114: while (list) {
2115: uint32 data;
2116: if (bytesize == 2) {
2117: data = (int32)(int16)m68030_read_16(cpu, ea);
2118: } else {
2119: data = m68030_read_32(cpu, ea);
2120: }
2121: ea += bytesize;
2122: regcount++;
2123: int ctz = __builtin_ctz(list);
2124: RegR(ctz) = data;
2125: // clear LSB bits
2126: list &= ((~1U) << ctz);
2127: }
2128: // (An)+ なら An を更新
2129: if (anpi) {
2130: RegAY = ea;
2131: }
2132:
2133: CYCLE(8 + 4 * regcount);
2134: }
2135:
2136: // %0100_110010_mmmrrr MOVEM.W <ea>,<list>
2137: OP_DEF(movem_w)
2138: {
2139: ops_movem_ea_list<2>(cpu);
2140: }
2141:
2142: // %0100_110011_mmmrrr MOVEM.L <ea>,<list>
2143: OP_DEF(movem_l)
2144: {
2145: ops_movem_ea_list<4>(cpu);
2146: }
2147:
1.1.1.2 ! root 2148: static void
1.1 root 2149: ops_rte(m68kcpu *cpu)
2150: {
2151: SUPERVISOR_OP;
2152:
2153: // subr.cpp
2154: m68030_rte(cpu);
2155: }
2156:
2157: // MOVEC.L Rc,Rn
1.1.1.2 ! root 2158: static void
1.1 root 2159: ops_movec_rc_rn(m68kcpu *cpu)
2160: {
2161: SUPERVISOR_OP;
2162:
2163: CYCLE(6);
2164: RegIR2 = m68030_fetch_16(cpu);
2165: int n = RegIR2 >> 12;
2166: int c = RegIR2 & 0xfff;
2167: switch (c) {
2168: case 0x000:
2169: RegR(n) = RegSFC;
2170: return;
2171: case 0x001:
2172: RegR(n) = RegDFC;
2173: return;
2174: case 0x002:
2175: RegR(n) = RegCACR;
2176: return;
2177: case 0x800:
2178: RegR(n) = RegUSP;
2179: return;
2180: case 0x801:
2181: RegR(n) = RegVBR;
2182: return;
2183: case 0x802:
2184: RegR(n) = RegCAAR;
2185: return;
2186: case 0x803:
2187: if (cpu->reg.m) {
2188: RegR(n) = RegA(7);
2189: } else {
2190: RegR(n) = RegMSP;
2191: }
2192: return;
2193: case 0x804:
2194: if (cpu->reg.m) {
2195: RegR(n) = RegISP;
2196: } else {
2197: RegR(n) = RegA(7);
2198: }
2199: return;
2200: default:
2201: break;
2202: }
2203: op_illegal(cpu);
2204: }
2205:
2206: // MOVEC.L Rn,Rc
1.1.1.2 ! root 2207: static void
1.1 root 2208: ops_movec_rn_rc(m68kcpu *cpu)
2209: {
2210: SUPERVISOR_OP;
2211:
2212: RegIR2 = m68030_fetch_16(cpu);
2213: int n = RegIR2 >> 12;
2214: int c = RegIR2 & 0xfff;
2215: switch (c) {
2216: case 0x000:
2217: CYCLE(12);
2218: RegSFC = RegR(n);
2219: return;
2220: case 0x001:
2221: CYCLE(12);
2222: RegDFC = RegR(n);
2223: return;
2224: case 0x002:
2225: CYCLE(12);
2226: RegCACR = RegR(n);
2227: return;
2228: case 0x800:
2229: CYCLE(6);
2230: RegUSP = RegR(n);
2231: return;
2232: case 0x801:
2233: CYCLE(6);
2234: RegVBR = RegR(n);
2235: return;
2236: case 0x802:
2237: CYCLE(6);
2238: RegCAAR = RegR(n);
2239: return;
2240: case 0x803:
2241: CYCLE(6);
2242: if (cpu->reg.m) {
2243: RegA(7) = RegR(n);
2244: } else {
2245: RegMSP = RegR(n);
2246: }
2247: return;
2248: case 0x804:
2249: CYCLE(6);
2250: if (cpu->reg.m) {
2251: RegISP = RegR(n);
2252: } else {
2253: RegA(7) = RegR(n);
2254: }
2255: return;
2256: default:
2257: break;
2258: }
2259: op_illegal(cpu);
2260: }
2261:
2262: // %0100_111001_00nnnn TRAP #<vector>
2263: // %0100_111001_010yyy LINK.W Ay,#<imm>
2264: // %0100_111001_011yyy UNLK Ay
2265: // %0100_111001_100yyy MOVE.L Ay,USP
2266: // %0100_111001_101yyy MOVE.L USP,Ay
2267: // %0100_111001_110000 RESET
2268: // %0100_111001_110001 NOP
2269: // %0100_111001_110010 STOP #<imm>
2270: // %0100_111001_110011 RTE
2271: // %0100_111001_110100 RTD #<imm>
2272: // %0100_111001_110101 RTS
2273: // %0100_111001_110110 TRAPV
2274: // %0100_111001_110111 RTR
2275: // %0100_111001_111010 MOVEC.L Rc,Rn
2276: // %0100_111001_111011 MOVEC.L Rn,Rc
2277: OP_DEF(trap)
2278: {
2279: uint n = RegIR & 0x3f;
2280: int32 imm;
2281:
2282: switch (n) {
2283: case 0x00 ... 0x0f:// TRAP #<vector>
2284: CYCLE2(18, 20);
2285: // TRAP#N 例外
2286: m68030_exception(cpu, M68K_EXCEP_TRAP0 + n);
2287: return;
2288:
2289: case 0x10:
2290: case 0x11:
2291: case 0x12:
2292: case 0x13:
2293: case 0x14:
2294: case 0x15:
2295: case 0x17: // LINK.W Ay,#<imm>
2296: CYCLE2(4, 5);
2297: // レジスタやスタックを変更する前にフェッチとセーブをしないと、
2298: // ページフォルトで再実行できなくなる
2299: imm = (int32)(int16)m68030_fetch_16(cpu);
2300: m68030_save_reg_pd(cpu, 7);
2301: m68030_push_32(cpu, RegAY);
2302: RegAY = RegA(7);
2303: RegA(7) += imm;
2304: return;
2305: case 0x16: // LINK.W A6,#<imm>
2306: // LINK はほぼ A6 なのでこいつだけ展開してみる
2307: CYCLE2(4, 5);
2308: // レジスタやスタックを変更する前にフェッチとセーブをしないと、
2309: // ページフォルトで再実行できなくなる
2310: imm = (int32)(int16)m68030_fetch_16(cpu);
2311: m68030_save_reg_pd(cpu, 7);
2312: m68030_push_32(cpu, RegA(6));
2313: RegA(6) = RegA(7);
2314: RegA(7) += imm;
2315: return;
2316:
2317: case 0x18:
2318: case 0x19:
2319: case 0x1a:
2320: case 0x1b:
2321: case 0x1c:
2322: case 0x1d:
2323: case 0x1f: // UNLK Ay
2324: CYCLE(5);
2325: // ページフォルトに備えて保存する
2326: m68030_save_reg_pi(cpu, 7);
2327: RegA(7) = RegAY;
2328: RegAY = m68030_pop_32(cpu);
2329: return;
2330: case 0x1e: // UNLK A6
2331: // UNLK はほぼ A6 なのでこいつだけ展開してみる
2332: CYCLE(5);
2333: // ページフォルトに備えて保存する
2334: m68030_save_reg_pi(cpu, 7);
2335: RegA(7) = RegA(6);
2336: RegA(6) = m68030_pop_32(cpu);
2337: return;
2338:
2339: case 0x20:
2340: case 0x21:
2341: case 0x22:
2342: case 0x23:
2343: case 0x24:
2344: case 0x25:
2345: case 0x26:
2346: case 0x27: // MOVE.L Ay,USP
2347: SUPERVISOR_OP;
2348: CYCLE(4);
2349: RegUSP = RegAY;
2350: return;
2351:
2352: case 0x28:
2353: case 0x29:
2354: case 0x2a:
2355: case 0x2b:
2356: case 0x2c:
2357: case 0x2d:
2358: case 0x2e:
2359: case 0x2f: // MOVE.L USP,Ay
2360: SUPERVISOR_OP;
2361: CYCLE(4);
2362: RegAY = RegUSP;
2363: return;
2364:
2365: case 0x30: // RESET
2366: CYCLE(518);
2367: m68030_reset_inst(cpu);
2368: return;
2369:
2370: case 0x31: // NOP
2371: CYCLE(2);
2372: // XXX ほんとは何かするらしいけど
2373: return;
2374:
2375: case 0x32: // STOP #<imm>
2376: {
2377: SUPERVISOR_OP;
2378: CYCLE(8);
2379: uint32 data = m68030_fetch_16(cpu);
2380: m68030_set_sr(cpu, data);
2381: cpu->atomic_reqflag |= CPU_REQ_RELEASE | CPU_REQ_STOP;
2382: return;
2383: }
2384:
2385: case 0x33: // RTE
2386: ops_rte(cpu);
2387: return;
2388:
2389: case 0x34: // RTD #<imm>
2390: {
2391: CYCLE2(10, 12);
2392: // ページフォルトに備えて保存する
2393: m68030_save_reg_pi(cpu, 7);
2394: uint32 disp = m68030_fetch_16(cpu);
2395: m68030_jump(cpu, m68030_pop_32(cpu));
2396: RegA(7) += (int32)(int16)disp;
2397: return;
2398: }
2399:
2400: case 0x35: // RTS
2401: CYCLE2(9, 11);
2402: // ページフォルトに備えて保存する
2403: m68030_save_reg_pi(cpu, 7);
2404: m68030_jump(cpu, m68030_pop_32(cpu));
2405: return;
2406:
2407: case 0x36: // TRAPV
2408: if (CCR.IsV()) {
2409: CYCLE2(22, 24);
2410: m68030_exception(cpu, M68K_EXCEP_TRAPV);
2411: } else {
2412: CYCLE(4);
2413: }
2414: return;
2415:
2416: case 0x37: // RTR
2417: CYCLE2(12, 14);
2418: // ページフォルトに備えて保存する
2419: m68030_save_reg_pi(cpu, 7);
2420: CCR.Set(m68030_pop_16(cpu));
2421: m68030_jump(cpu, m68030_pop_32(cpu));
2422: return;
2423:
2424: case 0x3a: // MOVEC.L Rc,Rn
2425: ops_movec_rc_rn(cpu);
2426: return;
2427:
2428: case 0x3b: // MOVEC.L Rn,Rc
2429: ops_movec_rn_rc(cpu);
2430: return;
2431:
2432: default:
2433: op_illegal(cpu);
2434: return;
2435: }
2436: }
2437:
2438: // %0100_111010_mmmrrr JSR <ea>
2439: OP_DEF(jsr)
2440: {
2441: CYCLE2(4, 7);
2442: uint32 ea = cea_ctrl(cpu);
2443: // ページフォルトに備えて保存する
2444: m68030_save_reg_pd(cpu, 7);
2445: m68030_push_32(cpu, RegPC);
2446: m68030_jump(cpu, ea);
2447: }
2448:
2449: // %0100_111011_mmmrrr JMP <ea>
2450: OP_DEF(jmp)
2451: {
2452: CYCLE2(4, 6);
2453: // 実際には CEA ではなく JEA の実行時間を足すんだがまあいいか
2454: uint32 ea = cea_ctrl(cpu);
2455: m68030_jump(cpu, ea);
2456: }
2457:
2458: // %0101_qqq000_mmmrrr ADDQ.B #qqq,<ea>
2459: OP_DEF(addq_b)
2460: {
2461: uint n = RegIR & 0x3f;
2462:
2463: uint32 src = RegIRX;
2464: src = (src == 0) ? 8 : src;
2465: if (n < 8) {
2466: // ADDQ.B #qqq,Dn
2467: CYCLE(2);
2468: uint32 data = acc_add_8(cpu, src, RegD(n) & 0xff);
2469: RegD(n) = (RegD(n) & 0xffffff00) | data;
2470: } else {
2471: // ADDQ.B #qqq,<ea>
2472: CYCLE2(3, 4);
2473: uint32 ea = cea_data_8(cpu);
2474: uint32 data = m68030_read_8(cpu, ea);
2475: data = acc_add_8(cpu, src, data);
2476: m68030_write_8(cpu, ea, data);
2477: }
2478: }
2479:
2480: // %0101_qqq001_mmmrrr ADDQ.W #qqq,<ea>
2481: // %0101_qqq001_001yyy ADDQ.W #qqq,Ay (.Lと等価)
2482: OP_DEF(addq_w)
2483: {
2484: uint n = RegIR & 0x3f;
2485:
2486: uint32 src = RegIRX;
2487: src = (src == 0) ? 8 : src;
2488: if (n < 8) {
2489: // ADDQ.W #qqq,Dn
2490: CYCLE(2);
2491: uint32 data = acc_add_16(cpu, src, RegD(n) & 0xffff);
2492: RegD(n) = (RegD(n) & 0xffff0000) | data;
2493: } else if (n < 16) {
2494: // ADDQ.W #qqq,An は ADDQ.L と等価
2495: // フラグは変化しない
2496: CYCLE(2);
2497: RegR(n) += src;
2498: } else {
2499: // ADDQ.W #qqq,<ea>
2500: CYCLE2(3, 4);
2501: uint32 ea = cea_data_16(cpu);
2502: uint32 data = m68030_read_16(cpu, ea);
2503: data = acc_add_16(cpu, src, data);
2504: m68030_write_16(cpu, ea, data);
2505: }
2506: }
2507:
2508: // %0101_qqq010_mmmrrr ADDQ.L #qqq,<ea>
2509: // %0101_qqq010_001yyy ADDQ.L #qqq,Ay
2510: OP_DEF(addq_l)
2511: {
2512: uint n = RegIR & 0x3f;
2513:
2514: uint32 src = RegIRX;
2515: src = (src == 0) ? 8 : src;
2516: if (n < 8) {
2517: // ADDQ.L #qqq,Dn
2518: CYCLE(2);
2519: RegD(n) = acc_add_32(cpu, src, RegD(n));
2520: } else if (n < 16) {
2521: // ADDQ.L #qqq,An
2522: // フラグは変化しない
2523: CYCLE(2);
2524: RegR(n) += src;
2525: } else {
2526: // ADDQ.L #qqq,<ea>
2527: CYCLE2(3, 4);
2528: uint32 ea = cea_data_32(cpu);
2529: uint32 data = m68030_read_32(cpu, ea);
2530: data = acc_add_32(cpu, src, data);
2531: m68030_write_32(cpu, ea, data);
2532: }
2533: }
2534:
2535: // TRAPcc の共通部分。
2536: template<int cond>void
2537: ops_trapcc(m68kcpu *cpu)
2538: {
2539: // 条件成立すれば例外。成立しなければ何もしない。
2540: // いずれの場合もオペランドありの形態なら事前に読み飛ばしておくこと。
2541: if (cond_func(cpu, cond)) {
2542: CYCLE2(22, 24);
2543: m68030_exception(cpu, M68K_EXCEP_TRAPV);
2544: } else {
2545: // サイクルを消費するだけ
2546: CYCLE(4);
2547: }
2548: }
2549:
2550: // Scc ブロックの共通部分。
2551: template<int cond> void
2552: ops_scc(m68kcpu *cpu)
2553: {
2554: uint n = RegIR & 0x3f;
2555:
2556: switch (n) {
2557: case 0b000000 ... 0b000111: // Scc.B Dn
2558: CYCLE(4);
2559: if (cond_func(cpu, cond)) {
2560: RegDY |= 0xff;
2561: } else {
2562: RegDY &= ~0xff;
2563: }
2564: return;
2565:
2566: case 0b001000 ... 0b001111: // DBcc.W Dy,<label>
2567: if (cond_func(cpu, cond)) {
2568: // 真なら何もしない。disp を読み飛ばして次へ。
2569: CYCLE2(6, 8);
2570: m68030_fetch_16(cpu);
2571: } else {
2572: // 偽の場合
2573:
2574: // Dy.W を減算して(下位ワードに)書き戻し、Dy.W が -1 だったら
2575: // ループ終了。だが最適化のため、減算前の Dy.W が 0 の時は
2576: // 下位ワードを 0xffff にしてループ終了、そうでなければ Dy.L を
2577: // 減算するだけでいいはず。
2578:
2579: uint16 data = RegDY;
2580: if (data == 0) {
2581: // ループ終了。disp を読み飛ばす
2582: CYCLE2(10, 13);
2583: RegDY |= 0x0000ffff;
2584: m68030_fetch_16(cpu);
2585: } else {
2586: CYCLE2(6, 8);
2587: RegDY--;
2588: uint32 pc = RegPC;
2589: int32 disp = (int32)(int16)m68030_fetch_16(cpu);
2590: m68030_jump(cpu, pc + disp);
2591: }
2592: }
2593: return;
2594:
2595: case 0b010000 ... 0b010111: // Scc.B <ea>
2596: case 0b011000 ... 0b011111: // Scc.B <ea>
2597: case 0b100000 ... 0b100111: // Scc.B <ea>
2598: case 0b101000 ... 0b101111: // Scc.B <ea>
2599: case 0b110000 ... 0b110111: // Scc.B <ea>
2600: case 0b111000: // Scc.B <ea>
2601: case 0b111001: // Scc.B <ea>
2602: {
2603: CYCLE(5);
2604: // 条件成立可否に関わらず EA は取得しないといけない
2605: uint32 ea = cea_data_8(cpu);
2606: uint32 data;
2607: if (cond_func(cpu, cond)) {
2608: data = 0xff;
2609: } else {
2610: data = 0;
2611: }
2612: m68030_write_8(cpu, ea, data);
2613: return;
2614: }
2615:
2616: case 0b111010: // TRAPcc.W #<imm>
2617: // オペランドなしTRAPccに比べてすべてのケースで2サイクル多い
2618: CYCLE(2);
2619: m68030_fetch_16(cpu);
2620: ops_trapcc<cond>(cpu);
2621: return;
2622:
2623: case 0b111011: // TRAPcc.L #<imm>
2624: // オペランドなしTRAPccに比べてすべてのケースで4サイクル多い
2625: CYCLE(4);
2626: m68030_fetch_32(cpu);
2627: ops_trapcc<cond>(cpu);
2628: return;
2629:
2630: case 0b111100: // TRAPcc
2631: ops_trapcc<cond>(cpu);
2632: return;
2633:
2634: default:
2635: OP_FUNC(illegal);
2636: return;
2637: }
2638: }
2639:
2640: // %0101_000011_mmmrrr ST.B <ea>
2641: // %0101_000011_001yyy DBT.W Dy,<label>
2642: // %0101_000011_111010 TRAPT.W #<imm>
2643: // %0101_000011_111011 TRAPT.L #<imm>
2644: // %0101_000011_111100 TRAPT
2645: OP_DEF(st)
2646: {
2647: ops_scc<0>(cpu);
2648: }
2649:
2650: // %0101_qqq100_mmmrrr SUBQ.B #qqq,<ea>
2651: OP_DEF(subq_b)
2652: {
2653: uint n = RegIR & 0x3f;
2654:
2655: uint32 src = RegIRX;
2656: src = (src == 0) ? 8 : src;
2657: if (n < 8) {
2658: // SUBQ.B #qqq,Dn
2659: CYCLE(2);
2660: uint32 data = acc_sub_8(cpu, src, RegD(n) & 0xff);
2661: RegD(n) = (RegD(n) & 0xffffff00) | data;
2662: } else {
2663: // SUBQ.B #qqq,<ea>
2664: CYCLE2(3, 4);
2665: uint32 ea = cea_data_8(cpu);
2666: uint32 data = m68030_read_8(cpu, ea);
2667: data = acc_sub_8(cpu, src, data);
2668: m68030_write_8(cpu, ea, data);
2669: }
2670: }
2671:
2672: // %0101_qqq101_mmmrrr SUBQ.W #qqq,<ea>
2673: // %0101_qqq101_001yyy SUBQ.W #qqq,Ay (.Lと等価)
2674: OP_DEF(subq_w)
2675: {
2676: uint n = RegIR & 0x3f;
2677:
2678: uint32 src = RegIRX;
2679: src = (src == 0) ? 8 : src;
2680: if (n < 8) {
2681: // SUBQ.W #qqq,Dn
2682: CYCLE(2);
2683: uint32 data = acc_sub_16(cpu, src, RegD(n) & 0xffff);
2684: RegD(n) = (RegD(n) & 0xffff0000) | data;
2685: } else if (n < 16) {
2686: // SUBQ.W #qqq,An は SUBQ.L と等価
2687: // フラグは変化しない
2688: CYCLE(2);
2689: RegR(n) -= src;
2690: } else {
2691: // SUBQ.W #qqq,<ea>
2692: CYCLE2(3, 4);
2693: uint32 ea = cea_data_16(cpu);
2694: uint32 data = m68030_read_16(cpu, ea);
2695: data = acc_sub_16(cpu, src, data);
2696: m68030_write_16(cpu, ea, data);
2697: }
2698: }
2699:
2700: // %0101_qqq110_mmmrrr SUBQ.L #qqq,<ea>
2701: // %0101_qqq110_001yyy SUBQ.L #qqq,Ay
2702: OP_DEF(subq_l)
2703: {
2704: uint n = RegIR & 0x3f;
2705:
2706: uint32 src = RegIRX;
2707: src = (src == 0) ? 8 : src;
2708: if (n < 8) {
2709: // SUBQ.L #qqq,Dn
2710: CYCLE(2);
2711: RegD(n) = acc_sub_32(cpu, src, RegD(n));
2712: } else if (n < 16) {
2713: // SUBQ.L #qqq,An
2714: // フラグは変化しない
2715: CYCLE(2);
2716: RegR(n) -= src;
2717: } else {
2718: // SUBQ.L #qqq,<ea>
2719: CYCLE2(3, 4);
2720: uint32 ea = cea_data_32(cpu);
2721: uint32 data = m68030_read_32(cpu, ea);
2722: data = acc_sub_32(cpu, src, data);
2723: m68030_write_32(cpu, ea, data);
2724: }
2725: }
2726:
2727: // %0101_000111_mmmrrr SF.B <ea>
2728: // %0101_000111_001yyy DBRA.W Dy,<label>
2729: // %0101_000111_111010 TRAPF.W #<imm>
2730: // %0101_000111_111011 TRAPF.L #<imm>
2731: // %0101_000111_111100 TRAPF
2732: OP_DEF(sf)
2733: {
2734: ops_scc<1>(cpu);
2735: }
2736:
2737: // %0101_001011_mmmrrr SHI.B <ea>
2738: // %0101_001011_001yyy DBHI.W Dy,<label>
2739: // %0101_001011_111010 TRAPHI.W #<imm>
2740: // %0101_001011_111011 TRAPHI.L #<imm>
2741: // %0101_001011_111100 TRAPHI
2742: OP_DEF(shi)
2743: {
2744: ops_scc<2>(cpu);
2745: }
2746:
2747: // %0101_001111_mmmrrr SLS.B <ea>
2748: // %0101_001111_001yyy DBLS.W Dy,<label>
2749: // %0101_001111_111010 TRAPLS.W #<imm>
2750: // %0101_001111_111011 TRAPLS.L #<imm>
2751: // %0101_001111_111100 TRAPLS
2752: OP_DEF(sls)
2753: {
2754: ops_scc<3>(cpu);
2755: }
2756:
2757: // %0101_010011_mmmrrr SCC.B <ea>
2758: // %0101_010011_001yyy DBCC.W Dy,<label>
2759: // %0101_010011_111010 TRAPCC.W #<imm>
2760: // %0101_010011_111011 TRAPCC.L #<imm>
2761: // %0101_010011_111100 TRAPCC
2762: OP_DEF(scc)
2763: {
2764: ops_scc<4>(cpu);
2765: }
2766:
2767: // %0101_010111_mmmrrr SCS.B <ea>
2768: // %0101_010111_001yyy DBCS.W Dy,<label>
2769: // %0101_010111_111010 TRAPCS.W #<imm>
2770: // %0101_010111_111011 TRAPCS.L #<imm>
2771: // %0101_010111_111100 TRAPCS
2772: OP_DEF(scs)
2773: {
2774: ops_scc<5>(cpu);
2775: }
2776:
2777: // %0101_011011_mmmrrr SNE.B <ea>
2778: // %0101_011011_001yyy DBNE.W Dy,<label>
2779: // %0101_011011_111010 TRAPNE.W #<imm>
2780: // %0101_011011_111011 TRAPNE.L #<imm>
2781: // %0101_011011_111100 TRAPNE
2782: OP_DEF(sne)
2783: {
2784: ops_scc<6>(cpu);
2785: }
2786:
2787: // %0101_011111_mmmrrr SEQ.B <ea>
2788: // %0101_011111_001yyy DBEQ.W Dy,<label>
2789: // %0101_011111_111010 TRAPEQ.W #<imm>
2790: // %0101_011111_111011 TRAPEQ.L #<imm>
2791: // %0101_011111_111100 TRAPEQ
2792: OP_DEF(seq)
2793: {
2794: ops_scc<7>(cpu);
2795: }
2796:
2797: // %0101_100011_mmmrrr SVC.B <ea>
2798: // %0101_100011_001yyy DBVC.W Dy,<label>
2799: // %0101_100011_111010 TRAPVC.W #<imm>
2800: // %0101_100011_111011 TRAPVC.L #<imm>
2801: // %0101_100011_111100 TRAPVC
2802: OP_DEF(svc)
2803: {
2804: ops_scc<8>(cpu);
2805: }
2806:
2807: // %0101_100111_mmmrrr SVS.B <ea>
2808: // %0101_100111_001yyy DBVS.W Dy,<label>
2809: // %0101_100111_111010 TRAPVS.W #<imm>
2810: // %0101_100111_111011 TRAPVS.L #<imm>
2811: // %0101_100111_111100 TRAPVS
2812: OP_DEF(svs)
2813: {
2814: ops_scc<9>(cpu);
2815: }
2816:
2817: // %0101_101011_mmmrrr SPL.B <ea>
2818: // %0101_101011_001yyy DBPL.W Dy,<label>
2819: // %0101_101011_111010 TRAPPL.W #<imm>
2820: // %0101_101011_111011 TRAPPL.L #<imm>
2821: // %0101_101011_111100 TRAPPL
2822: OP_DEF(spl)
2823: {
2824: ops_scc<10>(cpu);
2825: }
2826:
2827: // %0101_101111_mmmrrr SMI.B <ea>
2828: // %0101_101111_001yyy DBMI.W Dy,<label>
2829: // %0101_101111_111010 TRAPMI.W #<imm>
2830: // %0101_101111_111011 TRAPMI.L #<imm>
2831: // %0101_101111_111100 TRAPMI
2832: OP_DEF(smi)
2833: {
2834: ops_scc<11>(cpu);
2835: }
2836:
2837: // %0101_110011_mmmrrr SGE.B <ea>
2838: // %0101_110011_001yyy DBGE.W Dy,<label>
2839: // %0101_110011_111010 TRAPGE.W #<imm>
2840: // %0101_110011_111011 TRAPGE.L #<imm>
2841: // %0101_110011_111100 TRAPGE
2842: OP_DEF(sge)
2843: {
2844: ops_scc<12>(cpu);
2845: }
2846:
2847: // %0101_110111_mmmrrr SLT.B <ea>
2848: // %0101_110111_001yyy DBLT.W Dy,<label>
2849: // %0101_110111_111010 TRAPLT.W #<imm>
2850: // %0101_110111_111011 TRAPLT.L #<imm>
2851: // %0101_110111_111100 TRAPLT
2852: OP_DEF(slt)
2853: {
2854: ops_scc<13>(cpu);
2855: }
2856:
2857: // %0101_111011_mmmrrr SGT.B <ea>
2858: // %0101_111011_001yyy DBGT.W Dy,<label>
2859: // %0101_111011_111010 TRAPGT.W #<imm>
2860: // %0101_111011_111011 TRAPGT.L #<imm>
2861: // %0101_111011_111100 TRAPGT
2862: OP_DEF(sgt)
2863: {
2864: ops_scc<14>(cpu);
2865: }
2866:
2867: // %0101_111111_mmmrrr SLE.B <ea>
2868: // %0101_111111_001yyy DBLE.W Dy,<label>
2869: // %0101_111111_111010 TRAPLE.W #<imm>
2870: // %0101_111111_111011 TRAPLE.L #<imm>
2871: // %0101_111111_111100 TRAPLE
2872: OP_DEF(sle)
2873: {
2874: ops_scc<15>(cpu);
2875: }
2876:
2877: // BRA/Bcc の共通部分
2878: template<int cond> void
2879: ops_bcc(m68kcpu *cpu)
2880: {
2881: int32 disp = (int32)(int8)(RegIR & 0xff);
2882: uint32 pc;
2883:
2884: // ブランチするかどうかでサイクルが変わるので先に条件を調べる
2885: if (cond_func(cpu, cond)) {
2886: // Bcc (taken)
2887: CYCLE2(6, 8);
2888: pc = RegPC;
2889: if (disp == -1) {
2890: // Bcc.L
2891: disp = (int32)m68030_fetch_32(cpu);
2892: } else if (disp == 0) {
2893: // Bcc.W
2894: disp = (int32)(int16)m68030_fetch_16(cpu);
2895: }
2896: m68030_jump(cpu, pc + disp);
2897: } else {
2898: if (disp == -1) {
2899: // Bcc.L (not taken)
2900: CYCLE(8);
2901: m68030_fetch_32(cpu);
2902: } else if (disp == 0) {
2903: // Bcc.W (not taken)
2904: CYCLE(6);
2905: m68030_fetch_16(cpu);
2906: } else {
2907: // Bcc.B (not taken)
2908: CYCLE(4);
2909: }
2910: }
2911: }
2912:
2913: // %0110_000000_000000 BRA.W <label>
2914: // %0110_0000nn_nnnnnn BRA.B <label>
2915: // %0110_000011_111111 BRA.L <label>
2916: OP_DEF(bra)
2917: {
2918: ops_bcc<0>(cpu);
2919: }
2920:
2921: // %0110_000100_000000 BSR.W <label>
2922: // %0110_0001nn_nnnnnn BSR.B <label>
2923: // %0110_000111_111111 BSR.L <label>
2924: OP_DEF(bsr)
2925: {
2926: CYCLE2(6, 9);
2927: uint32 pc = RegPC;
2928: int32 disp = (int32)(int8)(RegIR & 0xff);
2929: if (disp == -1) {
2930: // BSR.L <label>
2931: disp = (int32)m68030_fetch_32(cpu);
2932: } else if (disp == 0) {
2933: // BSR.W <label>
2934: disp = (int32)(int16)m68030_fetch_16(cpu);
2935: }
2936: // ページフォルトに備えて保存する
2937: m68030_save_reg_pd(cpu, 7);
2938: m68030_push_32(cpu, RegPC);
2939: m68030_jump(cpu, pc + disp);
2940: }
2941:
2942: // %0110_001000_000000 BHI.W <label>
2943: // %0110_0010nn_nnnnnn BHI.B <label>
2944: // %0110_001011_111111 BHI.L <label>
2945: OP_DEF(bhi)
2946: {
2947: ops_bcc<2>(cpu);
2948: }
2949:
2950: // %0110_001100_000000 BLS.W <label>
2951: // %0110_0011nn_nnnnnn BLS.B <label>
2952: // %0110_001111_111111 BLS.L <label>
2953: OP_DEF(bls)
2954: {
2955: ops_bcc<3>(cpu);
2956: }
2957:
2958: // %0110_010000_000000 BCC.W <label>
2959: // %0110_0100nn_nnnnnn BCC.B <label>
2960: // %0110_010011_111111 BCC.L <label>
2961: OP_DEF(bcc)
2962: {
2963: ops_bcc<4>(cpu);
2964: }
2965:
2966: // %0110_010100_000000 BCS.W <label>
2967: // %0110_0101nn_nnnnnn BCS.B <label>
2968: // %0110_010111_111111 BCS.L <label>
2969: OP_DEF(bcs)
2970: {
2971: ops_bcc<5>(cpu);
2972: }
2973:
2974: // %0110_011000_000000 BNE.W <label>
2975: // %0110_0110nn_nnnnnn BNE.B <label>
2976: // %0110_011011_111111 BNE.L <label>
2977: OP_DEF(bne)
2978: {
2979: ops_bcc<6>(cpu);
2980: }
2981:
2982: // %0110_011100_000000 BEQ.W <label>
2983: // %0110_0111nn_nnnnnn BEQ.B <label>
2984: // %0110_011111_111111 BEQ.L <label>
2985: OP_DEF(beq)
2986: {
2987: ops_bcc<7>(cpu);
2988: }
2989:
2990: // %0110_100000_000000 BVC.W <label>
2991: // %0110_1000nn_nnnnnn BVC.B <label>
2992: // %0110_100011_111111 BVC.L <label>
2993: OP_DEF(bvc)
2994: {
2995: ops_bcc<8>(cpu);
2996: }
2997:
2998: // %0110_100100_000000 BVS.W <label>
2999: // %0110_1001nn_nnnnnn BVS.B <label>
3000: // %0110_100111_111111 BVS.L <label>
3001: OP_DEF(bvs)
3002: {
3003: ops_bcc<9>(cpu);
3004: }
3005:
3006: // %0110_101000_000000 BPL.W <label>
3007: // %0110_1010nn_nnnnnn BPL.B <label>
3008: // %0110_101011_111111 BPL.L <label>
3009: OP_DEF(bpl)
3010: {
3011: ops_bcc<10>(cpu);
3012: }
3013:
3014: // %0110_101100_000000 BMI.W <label>
3015: // %0110_1011nn_nnnnnn BMI.B <label>
3016: // %0110_101111_111111 BMI.L <label>
3017: OP_DEF(bmi)
3018: {
3019: ops_bcc<11>(cpu);
3020: }
3021:
3022: // %0110_110000_000000 BGE.W <label>
3023: // %0110_1100nn_nnnnnn BGE.B <label>
3024: // %0110_110011_111111 BGE.L <label>
3025: OP_DEF(bge)
3026: {
3027: ops_bcc<12>(cpu);
3028: }
3029:
3030: // %0110_110100_000000 BLT.W <label>
3031: // %0110_1101nn_nnnnnn BLT.B <label>
3032: // %0110_110111_111111 BLT.L <label>
3033: OP_DEF(blt)
3034: {
3035: ops_bcc<13>(cpu);
3036: }
3037:
3038: // %0110_111000_000000 BGT.W <label>
3039: // %0110_1110nn_nnnnnn BGT.B <label>
3040: // %0110_111011_111111 BGT.L <label>
3041: OP_DEF(bgt)
3042: {
3043: ops_bcc<14>(cpu);
3044: }
3045:
3046: // %0110_111100_000000 BLE.W <label>
3047: // %0110_1111nn_nnnnnn BLE.B <label>
3048: // %0110_111111_111111 BLE.L <label>
3049: OP_DEF(ble)
3050: {
3051: ops_bcc<15>(cpu);
3052: }
3053:
3054: // %0111_xxx0nn_nnnnnn MOVEQ.L #<imm>,Dx
3055: OP_DEF(moveq)
3056: {
3057: CYCLE(2);
3058: RegDX = (int32)(int8)(RegIR & 0xff);
3059: acc_move_32(cpu, RegDX);
3060: }
3061:
3062: // %1000_xxx000_mmmrrr OR.B <ea>,Dx
3063: OP_DEF(or_b_ea_dn)
3064: {
3065: uint n = RegIR & 0x3f;
3066:
3067: CYCLE(2);
3068: int x = RegIRX;
3069: if (n < 8) {
3070: // OR.B Dn,Dx
3071: uint32 data = (RegD(x) | RegD(n)) & 0xff;
3072: acc_move_8(cpu, data);
3073: RegD(x) = (RegD(x) & 0xffffff00) | data;
3074: } else {
3075: // OR.B <ea>,Dx
3076: uint32 src = fea_data_8(cpu);
3077: uint32 data = (RegD(x) | src) & 0xff;
3078: acc_move_8(cpu, data);
3079: RegD(x) = (RegD(x) & 0xffffff00) | data;
3080: }
3081: }
3082:
3083: // %1000_xxx001_mmmrrr OR.W <ea>,Dx
3084: OP_DEF(or_w_ea_dn)
3085: {
3086: uint n = RegIR & 0x3f;
3087:
3088: CYCLE(2);
3089: int x = RegIRX;
3090: if (n < 8) {
3091: // OR.W Dn,Dx
3092: uint32 data = (RegD(x) | RegD(n)) & 0xffff;
3093: acc_move_16(cpu, data);
3094: RegD(x) = (RegD(x) & 0xffff0000) | data;
3095: } else {
3096: // OR.W <ea>,Dx
3097: uint32 src = fea_data_16(cpu);
3098: uint32 data = (RegD(x) | src) & 0xffff;
3099: acc_move_16(cpu, data);
3100: RegD(x) = (RegD(x) & 0xffff0000) | data;
3101: }
3102: }
3103:
3104: // %1000_xxx010_mmmrrr OR.L <ea>,Dx
3105: OP_DEF(or_l_ea_dn)
3106: {
3107: uint n = RegIR & 0x3f;
3108:
3109: CYCLE(2);
3110: int x = RegIRX;
3111: if (n < 8) {
3112: // OR.L Dn,Dx
3113: RegD(x) |= RegD(n);
3114: acc_move_32(cpu, RegD(x));
3115: } else {
3116: // OR.L <ea>,Dx
3117: uint32 src = fea_data_32(cpu);
3118: uint32 data = RegD(x) | src;
3119: acc_move_32(cpu, data);
3120: RegD(x) = data;
3121: }
3122: }
3123:
3124: // %1000_xxx011_mmmrrr DIVU.W <ea>,Dx
3125: OP_DEF(divu_w)
3126: {
3127: CYCLE(44); // XXX これは本当は最大値だけど
3128: uint16 src = fea_data_16(cpu);
3129: uint32 dst = RegDX;
3130: uint32 quo;
3131: uint32 rem;
3132: if (acc_divu_32_16(cpu, src, dst, &quo, &rem)) {
3133: RegDX = (rem << 16) | quo;
3134: }
3135: }
3136:
3137: // %1000_xxx100_000yyy SBCD.B Dy,Dx
3138: // %1000_xxx100_001yyy SBCD.B -(Ay),-(Ax)
3139: // %1000_xxx100_mmmrrr OR.B Dx,<ea>
3140: OP_DEF(or_b_dn_ea)
3141: {
3142: uint n = RegIR & 0x3f;
3143:
3144: if (n < 8) {
3145: // SBCD.B Dy,Dx
3146: CYCLE(4);
3147: uint32 src = RegDY & 0xff;
3148: uint32 dst = RegDX & 0xff;
3149: dst = acc_sbcd_8(cpu, src, dst);
3150: RegDX &= 0xffffff00;
3151: RegDX |= dst;
3152: } else if (n < 16) {
3153: // SBCD.B -(Ay),-(Ax)
3154: CYCLE2(13, 14);
3155: uint32 srcea = internal_ea_anpd_8(cpu, RegIRY);
3156: uint32 dstea = internal_ea_anpd_8(cpu, RegIRX);
3157: uint32 src = m68030_read_8(cpu, srcea);
3158: uint32 dst = m68030_read_8(cpu, dstea);
3159: dst = acc_sbcd_8(cpu, src, dst);
3160: m68030_write_8(cpu, dstea, dst);
3161: } else {
3162: // OR.B Dx,<ea>
3163: CYCLE2(3, 4);
3164: uint32 ea = cea_data_8(cpu);
3165: uint8 data = m68030_read_8(cpu, ea);
3166: data |= RegDX;
3167: acc_move_8(cpu, data);
3168: m68030_write_8(cpu, ea, data);
3169: }
3170: }
3171:
3172: // %1000_xxx101_000yyy PACK Dy,Dx,#<imm>
3173: // %1000_xxx101_001yyy PACK -(Ay),-(Ax),#<imm>
3174: // %1000_xxx101_mmmrrr OR.W Dx,<ea>
3175: OP_DEF(or_w_dn_ea)
3176: {
3177: uint n = RegIR & 0x3f;
3178:
3179: if (n < 8) {
3180: // PACK Dy,Dx,#<imm>
3181: CYCLE(6);
3182: uint32 imm = m68030_fetch_16(cpu);
3183: uint32 src = RegDY + imm;
3184: RegDX = (RegDX & 0xffffff00) | ((src >> 4) & 0x00f0) | (src & 0x000f);
3185: } else if (n < 16) {
3186: // PACK -(Ay),-(Ax),#<imm>
3187: CYCLE(11);
3188: uint32 imm = m68030_fetch_16(cpu);
3189: uint32 srcea;
3190: uint32 src;
3191: // -(Ay) を2回行う
3192: srcea = internal_ea_anpd_8(cpu, RegIRY);
3193: src = m68030_read_8(cpu, srcea);
3194: srcea = internal_ea_anpd_8(cpu, RegIRY);
3195: src |= (m68030_read_8(cpu, srcea) << 8);
3196: src += imm;
3197: uint32 dst = ((src >> 4) & 0x00f0) | (src & 0x000f);
3198: uint32 dstea = internal_ea_anpd_8(cpu, RegIRX);
3199: m68030_write_8(cpu, dstea, dst);
3200: } else {
3201: // OR.W Dx,<ea>
3202: CYCLE2(3, 4);
3203: uint32 ea = cea_data_16(cpu);
3204: uint16 data = m68030_read_16(cpu, ea);
3205: data |= RegDX;
3206: acc_move_16(cpu, data);
3207: m68030_write_16(cpu, ea, data);
3208: }
3209: }
3210:
3211: // %1000_xxx110_000yyy UNPK Dy,Dx,#<imm>
3212: // %1000_xxx110_001yyy UNPK -(Ay),-(Ax),#<imm>
3213: // %1000_xxx110_mmmrrr OR.L Dx,<ea>
3214: OP_DEF(or_l_dn_ea)
3215: {
3216: uint n = RegIR & 0x3f;
3217:
3218: if (n < 8) {
3219: // UNPK Dy,Dx,#<imm>
3220: CYCLE(8);
3221: uint32 imm = m68030_fetch_16(cpu);
3222: uint16 src = RegDY;
3223: src = ((src & 0x00f0) << 4) | (src & 0x000f);
3224: src += imm;
3225: RegDX = (RegDX & 0xffff0000) | src;
3226: } else if (n < 16) {
3227: // UNPK -(Ay),-(Ax),#<imm>
3228: CYCLE(11);
3229: uint32 imm = m68030_fetch_16(cpu);
3230: uint32 srcea = internal_ea_anpd_8(cpu, RegIRY);
3231: uint16 src = m68030_read_8(cpu, srcea);
3232: src = ((src & 0x00f0) << 4) | (src & 0x000f);
3233: src += imm;
3234: // -(Ax) を2回行う
3235: uint32 dstea;
3236: dstea = internal_ea_anpd_8(cpu, RegIRX);
3237: m68030_write_8(cpu, dstea, (src & 0xff));
3238: dstea = internal_ea_anpd_8(cpu, RegIRX);
3239: m68030_write_8(cpu, dstea, src >> 8);
3240: } else {
3241: // OR.L Dx,<ea>
3242: CYCLE2(3, 4);
3243: uint32 ea = cea_data_32(cpu);
3244: uint32 data = m68030_read_32(cpu, ea);
3245: data |= RegDX;
3246: acc_move_32(cpu, data);
3247: m68030_write_32(cpu, ea, data);
3248: }
3249: }
3250:
3251: // %1000_xxx111_mmmrrr DIVS.W <ea>,Dx
3252: OP_DEF(divs_w)
3253: {
3254: CYCLE(56); // XXX これは本当は最大値だけど
3255: uint16 src = fea_data_16(cpu);
3256: uint32 dst = RegDX;
3257: uint32 quo;
3258: uint32 rem;
3259: if (acc_divs_32_16(cpu, src, dst, &quo, &rem)) {
3260: RegDX = (rem << 16) | quo;
3261: }
3262: }
3263:
3264: // %1001_xxx000_mmmrrr SUB.B <ea>,Dx
3265: OP_DEF(sub_b_ea_dn)
3266: {
3267: CYCLE(2);
3268: uint32 src = fea_all_8(cpu);
3269: uint32 data = acc_sub_8(cpu, src, RegDX & 0xff);
3270: RegDX = (RegDX & 0xffffff00) | data;
3271: }
3272:
3273: // %1001_xxx001_mmmrrr SUB.W <ea>,Dx
3274: OP_DEF(sub_w_ea_dn)
3275: {
3276: CYCLE(2);
3277: uint32 src = fea_all_16(cpu);
3278: uint32 data = acc_sub_16(cpu, src, RegDX & 0xffff);
3279: RegDX = (RegDX & 0xffff0000) | data;
3280: }
3281:
3282: // %1001_xxx010_mmmrrr SUB.L <ea>,Dx
3283: OP_DEF(sub_l_ea_dn)
3284: {
3285: CYCLE(2);
3286: uint32 src = fea_all_32(cpu);
3287: RegDX = acc_sub_32(cpu, src, RegDX);
3288: }
3289:
3290: // %1001_xxx011_mmmrrr SUBA.W <ea>,Ax
3291: OP_DEF(suba_w)
3292: {
3293: CYCLE(4);
3294: uint32 src = (int32)(int16)fea_all_16(cpu);
3295: RegAX -= src;
3296: }
3297:
3298: // %1001_xxx100_000yyy SUBX.B Dy,Dx
3299: // %1001_xxx100_001yyy SUBX.B -(Ay),-(Ax)
3300: // %1001_xxx100_mmmrrr SUB.B Dx,<ea>
3301: OP_DEF(sub_b_dn_ea)
3302: {
3303: uint n = RegIR & 0x3f;
3304:
3305: if (n < 8) {
3306: // SUBX.B Dy,Dx
3307: CYCLE(2);
3308: uint32 src = RegDY & 0xff;
3309: uint32 dst = RegDX & 0xff;
3310: dst = acc_subx_8(cpu, src, dst);
3311: RegDX = (RegDX & 0xffffff00) | dst;
3312: } else if (n < 16) {
3313: // SUBX.B -(Ay),-(Ax)
3314: CYCLE2(9, 10);
3315: uint32 srcea = internal_ea_anpd_8(cpu, RegIRY);
3316: uint32 dstea = internal_ea_anpd_8(cpu, RegIRX);
3317: uint32 src = m68030_read_8(cpu, srcea);
3318: uint32 dst = m68030_read_8(cpu, dstea);
3319: dst = acc_subx_8(cpu, src, dst);
3320: m68030_write_8(cpu, dstea, dst);
3321: } else {
3322: // SUB.B Dx,<ea>
3323: CYCLE2(3, 4);
3324: uint32 ea = cea_data_8(cpu);
3325: uint32 data = m68030_read_8(cpu, ea);
3326: data = acc_sub_8(cpu, RegDX & 0xff, data);
3327: m68030_write_8(cpu, ea, data);
3328: }
3329: }
3330:
3331: // %1001_xxx101_000yyy SUBX.W Dy,Dx
3332: // %1001_xxx101_001yyy SUBX.W -(Ay),-(Ax)
3333: // %1001_xxx101_mmmrrr SUB.W Dx,<ea>
3334: OP_DEF(sub_w_dn_ea)
3335: {
3336: uint n = RegIR & 0x3f;
3337:
3338: if (n < 8) {
3339: // SUBX.W Dy,Dx
3340: CYCLE(2);
3341: uint32 src = RegDY & 0xffff;
3342: uint32 dst = RegDX & 0xffff;
3343: dst = acc_subx_16(cpu, src, dst);
3344: RegDX = (RegDX & 0xffff0000) | dst;
3345: } else if (n < 16) {
3346: // SUBX.W -(Ay),-(Ax)
3347: CYCLE2(9, 10);
3348: uint32 srcea = internal_ea_anpd_16(cpu, RegIRY);
3349: uint32 dstea = internal_ea_anpd_16(cpu, RegIRX);
3350: uint32 src = m68030_read_16(cpu, srcea);
3351: uint32 dst = m68030_read_16(cpu, dstea);
3352: dst = acc_subx_16(cpu, src, dst);
3353: m68030_write_16(cpu, dstea, dst);
3354: } else {
3355: // SUB.W Dx,<ea>
3356: CYCLE2(3, 4);
3357: uint32 ea = cea_data_16(cpu);
3358: uint32 data = m68030_read_16(cpu, ea);
3359: data = acc_sub_16(cpu, RegDX & 0xffff, data);
3360: m68030_write_16(cpu, ea, data);
3361: }
3362: }
3363:
3364: // %1001_xxx110_000yyy SUBX.L Dy,Dx
3365: // %1001_xxx110_001yyy SUBX.L -(Ay),-(Ax)
3366: // %1001_xxx110_mmmrrr SUB.L Dx,<ea>
3367: OP_DEF(sub_l_dn_ea)
3368: {
3369: uint n = RegIR & 0x3f;
3370:
3371: if (n < 8) {
3372: // SUBX.L Dy,Dx
3373: CYCLE(2);
3374: uint32 src = RegDY;
3375: uint32 dst = RegDX;
3376: RegDX = acc_subx_32(cpu, src, dst);
3377: } else if (n < 16) {
3378: // SUBX.L -(Ay),-(Ax)
3379: CYCLE2(9, 10);
3380: uint32 srcea = internal_ea_anpd_32(cpu, RegIRY);
3381: uint32 dstea = internal_ea_anpd_32(cpu, RegIRX);
3382: uint32 src = m68030_read_32(cpu, srcea);
3383: uint32 dst = m68030_read_32(cpu, dstea);
3384: dst = acc_subx_32(cpu, src, dst);
3385: m68030_write_32(cpu, dstea, dst);
3386: } else {
3387: // SUB.L Dx,<ea>
3388: CYCLE2(3, 4);
3389: uint32 ea = cea_data_32(cpu);
3390: uint32 data = m68030_read_32(cpu, ea);
3391: data = acc_sub_32(cpu, RegDX, data);
3392: m68030_write_32(cpu, ea, data);
3393: }
3394: }
3395:
3396: // %1001_xxx111_mmmrrr SUBA.L <ea>,Ax
3397: OP_DEF(suba_l)
3398: {
3399: CYCLE(2);
3400: uint32 src = fea_all_32(cpu);
3401: RegAX -= src;
3402: }
3403:
3404: // %1010_nnnnnn_nnnnnn A-Line
3405: OP_DEF(aline)
3406: {
3407: if (cpu->aline_callback) {
3408: if (cpu->aline_callback(cpu, cpu->aline_arg)) {
3409: return;
3410: }
3411: }
3412: // A系列命令例外
3413: m68030_exception(cpu, M68K_EXCEP_ALINE);
3414: }
3415:
3416: // %1011_xxx000_mmmrrr CMP.B <ea>,Dx
3417: OP_DEF(cmp_b)
3418: {
3419: CYCLE(2);
3420: uint32 src = fea_all_8(cpu);
3421: uint32 dst = RegDX & 0xff;
3422: acc_cmp_8(cpu, src, dst);
3423: }
3424:
3425: // %1011_xxx001_mmmrrr CMP.W <ea>,Dx
3426: OP_DEF(cmp_w)
3427: {
3428: CYCLE(2);
3429: uint32 src = fea_all_16(cpu);
3430: uint32 dst = RegDX & 0xffff;
3431: acc_cmp_16(cpu, src, dst);
3432: }
3433:
3434: // %1011_xxx010_mmmrrr CMP.L <ea>,Dx
3435: OP_DEF(cmp_l)
3436: {
3437: CYCLE(2);
3438: uint32 src = fea_all_32(cpu);
3439: acc_cmp_32(cpu, src, RegDX);
3440: }
3441:
3442: // %1011_xxx011_mmmrrr CMPA.W <ea>,Ax
3443: OP_DEF(cmpa_w)
3444: {
3445: CYCLE(4);
3446: uint32 src = (uint32)(int32)(int16)fea_all_16(cpu);
3447: acc_cmp_32(cpu, src, RegAX);
3448: }
3449:
3450: // %1011_xxx100_mmmrrr EOR.B Dx,<ea>
3451: // %1011_xxx100_001yyy CMPM.B (Ay)+,(Ax)+
3452: OP_DEF(eor_b)
3453: {
3454: uint n = RegIR & 0x3f;
3455:
3456: if (n < 8) {
3457: // EOR.B Dx,Dy
3458: CYCLE(2);
3459: uint32 data = (RegD(n) ^ RegDX) & 0xff;
3460: RegD(n) = (RegD(n) & 0xffffff00) | data;
3461: acc_move_8(cpu, data);
3462: } else if (n < 16) {
3463: // CMPM.B (Ay)+,(Ax)+
3464: CYCLE(8);
3465: uint32 srcea = internal_ea_anpi_8(cpu, RegIRY);
3466: uint32 dstea = internal_ea_anpi_8(cpu, RegIRX);
3467: uint32 src = m68030_read_8(cpu, srcea);
3468: uint32 dst = m68030_read_8(cpu, dstea);
3469: acc_cmp_8(cpu, src, dst);
3470: } else {
3471: // EOR.B Dx,<ea>
3472: CYCLE2(3, 4);
3473: uint32 ea = cea_data_8(cpu);
3474: uint32 data = m68030_read_8(cpu, ea);
3475: data ^= (RegDX & 0xff);
3476: m68030_write_8(cpu, ea, data);
3477: acc_move_8(cpu, data);
3478: }
3479: }
3480:
3481: // %1011_xxx101_mmmrrr EOR.W Dx,<ea>
3482: // %1011_xxx101_001yyy CMPM.W (Ay)+,(Ax)+
3483: OP_DEF(eor_w)
3484: {
3485: uint n = RegIR & 0x3f;
3486:
3487: if (n < 8) {
3488: // EOR.W Dx,Dy
3489: CYCLE(2);
3490: uint32 data = (RegD(n) ^ RegDX) & 0xffff;
3491: RegD(n) = (RegD(n) & 0xffff0000) | data;
3492: acc_move_16(cpu, data);
3493: } else if (n < 16) {
3494: // CMPM.W (Ay)+,(Ax)+
3495: CYCLE(8);
3496: uint32 srcea = internal_ea_anpi_16(cpu, RegIRY);
3497: uint32 dstea = internal_ea_anpi_16(cpu, RegIRX);
3498: uint32 src = m68030_read_16(cpu, srcea);
3499: uint32 dst = m68030_read_16(cpu, dstea);
3500: acc_cmp_16(cpu, src, dst);
3501: } else {
3502: // EOR.W Dx,<ea>
3503: CYCLE2(3, 4);
3504: uint32 ea = cea_data_16(cpu);
3505: uint32 data = m68030_read_16(cpu, ea);
3506: data ^= (RegDX & 0xffff);
3507: m68030_write_16(cpu, ea, data);
3508: acc_move_16(cpu, data);
3509: }
3510: }
3511:
3512: // %1011_xxx110_mmmrrr EOR.L Dx,<ea>
3513: // %1011_xxx110_001yyy CMPM.L (Ay)+,(Ax)+
3514: OP_DEF(eor_l)
3515: {
3516: uint n = RegIR & 0x3f;
3517:
3518: if (n < 8) {
3519: CYCLE(2);
3520: // EOR.L Dx,Dy
3521: RegD(n) ^= RegDX;
3522: acc_move_32(cpu, RegD(n));
3523: } else if (n < 16) {
3524: // CMPM.L (Ay)+,(Ax)+
3525: CYCLE(8);
3526: uint32 srcea = internal_ea_anpi_32(cpu, RegIRY);
3527: uint32 dstea = internal_ea_anpi_32(cpu, RegIRX);
3528: uint32 src = m68030_read_32(cpu, srcea);
3529: uint32 dst = m68030_read_32(cpu, dstea);
3530: acc_cmp_32(cpu, src, dst);
3531: } else {
3532: // EOR.L Dx,<ea>
3533: CYCLE2(3, 4);
3534: uint32 ea = cea_data_32(cpu);
3535: uint32 data = m68030_read_32(cpu, ea);
3536: data ^= RegDX;
3537: m68030_write_32(cpu, ea, data);
3538: acc_move_32(cpu, data);
3539: }
3540: }
3541:
3542: // %1011_xxx111_mmmrrr CMPA.L <ea>,Ax
3543: OP_DEF(cmpa_l)
3544: {
3545: CYCLE(4);
3546: uint32 src = fea_all_32(cpu);
3547: acc_cmp_32(cpu, src, RegAX);
3548: }
3549:
3550: // %1100_xxx000_mmmrrr AND.B <ea>,Dx
3551: OP_DEF(and_b_ea_dn)
3552: {
3553: CYCLE(2);
3554: uint32 src = fea_data_8(cpu);
3555: uint32 dst = (RegDX & 0x000000ff) & src;
3556: acc_move_8(cpu, dst);
3557: RegDX = (RegDX & 0xffffff00) | dst;
3558: }
3559:
3560: // %1100_xxx001_mmmrrr AND.W <ea>,Dx
3561: OP_DEF(and_w_ea_dn)
3562: {
3563: CYCLE(2);
3564: uint32 src = fea_data_16(cpu);
3565: uint32 dst = (RegDX & 0x0000ffff) & src;
3566: acc_move_16(cpu, dst);
3567: RegDX = (RegDX & 0xffff0000) | dst;
3568: }
3569:
3570: // %1100_xxx010_mmmrrr AND.L <ea>,Dx
3571: OP_DEF(and_l_ea_dn)
3572: {
3573: CYCLE(2);
3574: uint32 src = fea_data_32(cpu);
3575: RegDX = RegDX & src;
3576: acc_move_32(cpu, RegDX);
3577: }
3578:
3579: // %1100_xxx011_mmmrrr MULU.W <ea>,Dx
3580: OP_DEF(mulu_w)
3581: {
3582: CYCLE(28); // 実際にはこれは最大値
3583: uint32 src = fea_data_16(cpu);
3584: uint32 dst = RegDX & 0xffff;
3585: RegDX = acc_mulu_16(cpu, src, dst);
3586: }
3587:
3588: // %1100_xxx100_000yyy ABCD.B Dy,Dx
3589: // %1100_xxx100_001yyy ABCD.B -(Ay),-(Ax)
3590: // %1100_xxx100_mmmrrr AND.B Dx,<ea>
3591: OP_DEF(and_b_dn_ea)
3592: {
3593: uint n = RegIR & 0x3f;
3594:
3595: if (n < 8) {
3596: // ABCD.B Dy,Dx
3597: CYCLE(4);
3598: uint32 src = RegDY & 0xff;
3599: uint32 dst = RegDX & 0xff;
3600: dst = acc_abcd_8(cpu, src, dst);
3601: RegDX &= 0xffffff00;
3602: RegDX |= dst;
3603: return;
3604: } else if (n < 16) {
3605: // ABCD.B -(Ay),-(Ax)
3606: CYCLE2(13, 14);
3607: uint32 srcea = internal_ea_anpd_8(cpu, RegIRY);
3608: uint32 dstea = internal_ea_anpd_8(cpu, RegIRX);
3609: uint32 src = m68030_read_8(cpu, srcea);
3610: uint32 dst = m68030_read_8(cpu, dstea);
3611: dst = acc_abcd_8(cpu, src, dst);
3612: m68030_write_8(cpu, dstea, dst);
3613: return;
3614: } else {
3615: // AND.B Dx,<ea>
3616: CYCLE2(3, 4);
3617: uint32 ea = cea_data_8(cpu);
3618: uint32 dst = m68030_read_8(cpu, ea);
3619: dst &= RegDX & 0xff;
3620: acc_move_8(cpu, dst);
3621: m68030_write_8(cpu, ea, dst);
3622: }
3623: }
3624:
3625: // %1100_xxx101_000yyy EXG.L Dx,Dy
3626: // %1100_xxx101_001yyy EXG.L Ax,Ay
3627: // %1100_xxx101_mmmrrr AND.W Dx,<ea>
3628: OP_DEF(and_w_dn_ea)
3629: {
3630: uint n = RegIR & 0x3f;
3631:
3632: if (n < 8) {
3633: // EXG.L Dx,Dy
3634: CYCLE(4);
3635: int x = RegIRX;
3636: int y = n;
3637: uint32 tmp = RegD(x);
3638: RegD(x) = RegD(y);
3639: RegD(y) = tmp;
3640: return;
3641: } else if (n < 16) {
3642: // EXG.L Ax,Ay
3643: // ここでは x は 0..7 で A(x)、y は 8..15 で R(y)
3644: CYCLE(4);
3645: int x = RegIRX;
3646: int y = n;
3647: uint32 tmp = RegA(x);
3648: RegA(x) = RegR(y);
3649: RegR(y) = tmp;
3650: return;
3651: } else {
3652: // AND.W Dx,<ea>
3653: CYCLE2(3, 4);
3654: uint32 ea = cea_data_16(cpu);
3655: uint32 dst = m68030_read_16(cpu, ea);
3656: dst &= RegDX & 0xffff;
3657: acc_move_16(cpu, dst);
3658: m68030_write_16(cpu, ea, dst);
3659: }
3660: }
3661:
3662: // %1100_xxx110_001yyy EXG.L Dx,Ay
3663: // %1100_xxx110_mmmrrr AND.L Dx,<ea>
3664: OP_DEF(and_l_dn_ea)
3665: {
3666: uint n = RegIR & 0x3f;
3667:
3668: if (n < 8) {
3669: op_illegal(cpu);
3670: return;
3671: } else if (n < 16) {
3672: // EXG.L Dx,Ay
3673: // ここでは x は 0..7 で D(x)、y は 8..15 で R(y)
3674: CYCLE(4);
3675: int x = RegIRX;
3676: int y = n;
3677: uint32 tmp = RegD(x);
3678: RegD(x) = RegR(y);
3679: RegR(y) = tmp;
3680: return;
3681: } else {
3682: // AND.L Dx,<ea>
3683: CYCLE2(3, 4);
3684: uint32 ea = cea_data_32(cpu);
3685: uint32 dst = m68030_read_32(cpu, ea);
3686: dst &= RegDX;
3687: acc_move_32(cpu, dst);
3688: m68030_write_32(cpu, ea, dst);
3689: }
3690: }
3691:
3692: // %1100_xxx111_mmmrrr MULS.W <ea>,Dx
3693: OP_DEF(muls_w)
3694: {
3695: CYCLE(28); // 実際にはこれは最大値
3696: uint32 src = fea_data_16(cpu);
3697: uint32 dst = RegDX & 0xffff;
3698: RegDX = acc_muls_16(cpu, src, dst);
3699: }
3700:
3701: // %1101_xxx000_mmmrrr ADD.B <ea>,Dx
3702: OP_DEF(add_b_ea_dn)
3703: {
3704: CYCLE(2);
3705: uint32 src = fea_all_8(cpu);
3706: uint32 data = acc_add_8(cpu, src, RegDX & 0xff);
3707: RegDX = (RegDX & 0xffffff00) | data;
3708: }
3709:
3710: // %1101_xxx001_mmmrrr ADD.W <ea>,Dx
3711: OP_DEF(add_w_ea_dn)
3712: {
3713: CYCLE(2);
3714: uint32 src = fea_all_16(cpu);
3715: uint32 data = acc_add_16(cpu, src, RegDX & 0xffff);
3716: RegDX = (RegDX & 0xffff0000) | data;
3717: }
3718:
3719: // %1101_xxx010_mmmrrr ADD.L <ea>,Dx
3720: OP_DEF(add_l_ea_dn)
3721: {
3722: CYCLE(2);
3723: uint32 src = fea_all_32(cpu);
3724: RegDX = acc_add_32(cpu, src, RegDX);
3725: }
3726:
3727: // %1101_xxx011_mmmrrr ADDA.W <ea>,Ax
3728: OP_DEF(adda_w)
3729: {
3730: CYCLE(4);
3731: uint32 src = (int32)(int16)fea_all_16(cpu);
3732: RegAX += src;
3733: }
3734:
3735: // %1101_xxx100_000yyy ADDX.B Dy,Dx
3736: // %1101_xxx100_001yyy ADDX.B -(Ay),-(Ax)
3737: // %1101_xxx100_mmmrrr ADD.B Dx,<ea>
3738: OP_DEF(add_b_dn_ea)
3739: {
3740: uint n = RegIR & 0x3f;
3741:
3742: if (n < 8) {
3743: // ADDX.B Dy,Dx
3744: CYCLE(2);
3745: uint32 src = RegDY & 0xff;
3746: uint32 dst = RegDX & 0xff;
3747: dst = acc_addx_8(cpu, src, dst);
3748: RegDX = (RegDX & 0xffffff00) | dst;
3749: } else if (n < 16) {
3750: // ADDX.B -(Ay),-(Ax)
3751: CYCLE2(9, 10);
3752: uint32 srcea = internal_ea_anpd_8(cpu, RegIRY);
3753: uint32 dstea = internal_ea_anpd_8(cpu, RegIRX);
3754: uint32 src = m68030_read_8(cpu, srcea);
3755: uint32 dst = m68030_read_8(cpu, dstea);
3756: dst = acc_addx_8(cpu, src, dst);
3757: m68030_write_8(cpu, dstea, dst);
3758: } else {
3759: // ADD.B Dx,<ea>
3760: CYCLE2(3, 4);
3761: uint32 ea = cea_data_8(cpu);
3762: uint32 data = m68030_read_8(cpu, ea);
3763: data = acc_add_8(cpu, RegDX & 0xff, data);
3764: m68030_write_8(cpu, ea, data);
3765: }
3766: }
3767:
3768: // %1101_xxx101_000yyy ADDX.W Dy,Dx
3769: // %1101_xxx101_001yyy ADDX.W -(Ay),-(Ax)
3770: // %1101_xxx101_mmmrrr ADD.W Dx,<ea>
3771: OP_DEF(add_w_dn_ea)
3772: {
3773: uint n = RegIR & 0x3f;
3774:
3775: if (n < 8) {
3776: // ADDX.W Dy,Dx
3777: CYCLE(2);
3778: uint32 src = RegDY & 0xffff;
3779: uint32 dst = RegDX & 0xffff;
3780: dst = acc_addx_16(cpu, src, dst);
3781: RegDX = (RegDX & 0xffff0000) | dst;
3782: } else if (n < 16) {
3783: // ADDX.W -(Ay),-(Ax)
3784: CYCLE2(9, 10);
3785: uint32 srcea = internal_ea_anpd_16(cpu, RegIRY);
3786: uint32 dstea = internal_ea_anpd_16(cpu, RegIRX);
3787: uint32 src = m68030_read_16(cpu, srcea);
3788: uint32 dst = m68030_read_16(cpu, dstea);
3789: dst = acc_addx_16(cpu, src, dst);
3790: m68030_write_16(cpu, dstea, dst);
3791: } else {
3792: // ADD.W Dx,<ea>
3793: CYCLE2(3, 4);
3794: uint32 ea = cea_data_16(cpu);
3795: uint32 data = m68030_read_16(cpu, ea);
3796: data = acc_add_16(cpu, RegDX & 0xffff, data);
3797: m68030_write_16(cpu, ea, data);
3798: }
3799: }
3800:
3801: // %1101_xxx110_000yyy ADDX.L Dy,Dx
3802: // %1101_xxx110_001yyy ADDX.L -(Ay),-(Ax)
3803: // %1101_xxx110_mmmrrr ADD.L Dx,<ea>
3804: OP_DEF(add_l_dn_ea)
3805: {
3806: uint n = RegIR & 0x3f;
3807:
3808: if (n < 8) {
3809: // ADDX.L Dy,Dx
3810: CYCLE(2);
3811: uint32 src = RegDY;
3812: uint32 dst = RegDX;
3813: RegDX = acc_addx_32(cpu, src, dst);
3814: } else if (n < 16) {
3815: // ADDX.L -(Ay),-(Ax)
3816: CYCLE2(9, 10);
3817: uint32 srcea = internal_ea_anpd_32(cpu, RegIRY);
3818: uint32 dstea = internal_ea_anpd_32(cpu, RegIRX);
3819: uint32 src = m68030_read_32(cpu, srcea);
3820: uint32 dst = m68030_read_32(cpu, dstea);
3821: dst = acc_addx_32(cpu, src, dst);
3822: m68030_write_32(cpu, dstea, dst);
3823: } else {
3824: // ADD.L Dx,<ea>
3825: CYCLE2(3, 4);
3826: uint32 ea = cea_data_32(cpu);
3827: uint32 data = m68030_read_32(cpu, ea);
3828: data = acc_add_32(cpu, RegDX, data);
3829: m68030_write_32(cpu, ea, data);
3830: }
3831: }
3832:
3833: // %1101_xxx111_mmmrrr ADDA.L <ea>,Ax
3834: OP_DEF(adda_l)
3835: {
3836: CYCLE(2);
3837: uint32 src = fea_all_32(cpu);
3838: RegAX += src;
3839: }
3840:
3841: // %1110_qqq000_000yyy ASR.B #qqq,Dy
3842: // %1110_qqq000_001yyy LSR.B #qqq,Dy
3843: // %1110_qqq000_010yyy ROXR.B #qqq,Dy
3844: // %1110_qqq000_011yyy ROR.B #qqq,Dy
3845: // %1110_xxx000_100yyy ASR.B Dx,Dy
3846: // %1110_xxx000_101yyy LSR.B Dx,Dy
3847: // %1110_xxx000_110yyy ROXR.B Dx,Dy
3848: // %1110_xxx000_111yyy ROR.B Dx,Dy
3849: OP_DEF(asr_b_imm)
3850: {
3851: int count;
3852: uint32 data;
3853: switch (eamode(RegIR)) {
3854: case 0: // ASR.B #qqq,Dy
3855: CYCLE(4);
3856: count = RegIRX;
3857: count = (count == 0) ? 8 : count;
3858: __assume(1 <= count && count <= 8);
3859: data = acc_asr_8(cpu, RegDY & 0xff, count);
3860: RegDY = (RegDY & 0xffffff00) | data;
3861: return;
3862: case 1: // LSR.B #qqq,Dy
3863: CYCLE(4);
3864: count = RegIRX;
3865: count = (count == 0) ? 8 : count;
3866: __assume(1 <= count && count <= 8);
3867: data = acc_lsr_8(cpu, RegDY & 0xff, count);
3868: RegDY = (RegDY & 0xffffff00) | data;
3869: return;
3870: case 2: // ROXR.B #qqq,Dy
3871: CYCLE(12);
3872: count = RegIRX;
3873: count = (count == 0) ? 8 : count;
3874: __assume(1 <= count && count <= 8);
3875: data = acc_roxr_8(cpu, RegDY & 0xff, count);
3876: RegDY = (RegDY & 0xffffff00) | data;
3877: return;
3878: case 3: // ROR.B #qqq,Dy
3879: CYCLE(6);
3880: count = RegIRX;
3881: count = (count == 0) ? 8 : count;
3882: __assume(1 <= count && count <= 8);
3883: data = acc_ror_8(cpu, RegDY & 0xff, count);
3884: RegDY = (RegDY & 0xffffff00) | data;
3885: return;
3886: case 4: // ASR.B Dx,Dy
3887: count = RegDX & 63;
3888: // シフト数がデータサイズを越えるかどうかでサイクルが違う
3889: CYCLE(count <= 8 ? 6 : 10);
3890: __assume(0 <= count && count < 64);
3891: data = acc_asr_8(cpu, RegDY & 0xff, count);
3892: RegDY = (RegDY & 0xffffff00) | data;
3893: return;
3894: case 5: // LSR.B Dx,Dy
3895: count = RegDX & 63;
3896: // シフト数がデータサイズを越えるかどうかでサイクルが違う
3897: CYCLE(count <= 8 ? 6 : 8);
3898: __assume(0 <= count && count < 64);
3899: data = acc_lsr_8(cpu, RegDY & 0xff, count);
3900: RegDY = (RegDY & 0xffffff00) | data;
3901: return;
3902: case 6: // ROXR.B Dx,Dy
3903: CYCLE(12);
3904: count = RegDX & 63;
3905: __assume(0 <= count && count < 64);
3906: data = acc_roxr_8(cpu, RegDY & 0xff, count);
3907: RegDY = (RegDY & 0xffffff00) | data;
3908: return;
3909: case 7: // ROR.B Dx,Dy
3910: CYCLE(8);
3911: count = RegDX & 63;
3912: __assume(0 <= count && count < 64);
3913: data = acc_ror_8(cpu, RegDY & 0xff, count);
3914: RegDY = (RegDY & 0xffffff00) | data;
3915: return;
3916: }
3917: }
3918:
3919: // %1110_qqq001_000yyy ASR.W #qqq,Dy
3920: // %1110_qqq001_001yyy LSR.W #qqq,Dy
3921: // %1110_qqq001_010yyy ROXR.W #qqq,Dy
3922: // %1110_qqq001_011yyy ROR.W #qqq,Dy
3923: // %1110_xxx001_100yyy ASR.W Dx,Dy
3924: // %1110_xxx001_101yyy LSR.W Dx,Dy
3925: // %1110_xxx001_110yyy ROXR.W Dx,Dy
3926: // %1110_xxx001_111yyy ROR.W Dx,Dy
3927: OP_DEF(asr_w_imm)
3928: {
3929: int count;
3930: uint32 data;
3931: switch (eamode(RegIR)) {
3932: case 0: // ASR.W #qqq,Dy
3933: CYCLE(4);
3934: count = RegIRX;
3935: count = (count == 0) ? 8 : count;
3936: __assume(1 <= count && count <= 8);
3937: data = acc_asr_16(cpu, RegDY & 0xffff, count);
3938: RegDY = (RegDY & 0xffff0000) | data;
3939: return;
3940: case 1: // LSR.W #qqq,Dy
3941: CYCLE(4);
3942: count = RegIRX;
3943: count = (count == 0) ? 8 : count;
3944: __assume(1 <= count && count <= 8);
3945: data = acc_lsr_16(cpu, RegDY & 0xffff, count);
3946: RegDY = (RegDY & 0xffff0000) | data;
3947: return;
3948: case 2: // ROXR.W #qqq,Dy
3949: CYCLE(12);
3950: count = RegIRX;
3951: count = (count == 0) ? 8 : count;
3952: __assume(1 <= count && count <= 8);
3953: data = acc_roxr_16(cpu, RegDY & 0xffff, count);
3954: RegDY = (RegDY & 0xffff0000) | data;
3955: return;
3956: case 3: // ROR.W #qqq,Dy
3957: CYCLE(6);
3958: count = RegIRX;
3959: count = (count == 0) ? 8 : count;
3960: __assume(1 <= count && count <= 8);
3961: data = acc_ror_16(cpu, RegDY & 0xffff, count);
3962: RegDY = (RegDY & 0xffff0000) | data;
3963: return;
3964: case 4: // ASR.W Dx,Dy
3965: count = RegDX & 63;
3966: // シフト数がデータサイズを越えるかどうかでサイクルが違う
3967: CYCLE(count <= 16 ? 6 : 10);
3968: __assume(0 <= count && count < 64);
3969: data = acc_asr_16(cpu, RegDY & 0xffff, count);
3970: RegDY = (RegDY & 0xffff0000) | data;
3971: return;
3972: case 5: // LSR.W Dx,Dy
3973: count = RegDX & 63;
3974: // シフト数がデータサイズを越えるかどうかでサイクルが違う
3975: CYCLE(count <= 16 ? 6 : 8);
3976: __assume(0 <= count && count < 64);
3977: data = acc_lsr_16(cpu, RegDY & 0xffff, count);
3978: RegDY = (RegDY & 0xffff0000) | data;
3979: return;
3980: case 6: // ROXR.W Dx,Dy
3981: CYCLE(12);
3982: count = RegDX & 63;
3983: __assume(0 <= count && count < 64);
3984: data = acc_roxr_16(cpu, RegDY & 0xffff, count);
3985: RegDY = (RegDY & 0xffff0000) | data;
3986: return;
3987: case 7: // ROR.W Dx,Dy
3988: CYCLE(8);
3989: count = RegDX & 63;
3990: __assume(0 <= count && count < 64);
3991: data = acc_ror_16(cpu, RegDY & 0xffff, count);
3992: RegDY = (RegDY & 0xffff0000) | data;
3993: return;
3994: }
3995: }
3996:
3997: // %1110_qqq010_000yyy ASR.L #qqq,Dy
3998: // %1110_qqq010_001yyy LSR.L #qqq,Dy
3999: // %1110_qqq010_010yyy ROXR.L #qqq,Dy
4000: // %1110_qqq010_011yyy ROR.L #qqq,Dy
4001: // %1110_xxx010_100yyy ASR.L Dx,Dy
4002: // %1110_xxx010_101yyy LSR.L Dx,Dy
4003: // %1110_xxx010_110yyy ROXR.L Dx,Dy
4004: // %1110_xxx010_111yyy ROR.L Dx,Dy
4005: OP_DEF(asr_l_imm)
4006: {
4007: int count;
4008: switch (eamode(RegIR)) {
4009: case 0: // ASR.L #qqq,Dy
4010: CYCLE(4);
4011: count = RegIRX;
4012: count = (count == 0) ? 8 : count;
4013: __assume(1 <= count && count <= 8);
4014: RegDY = acc_asr_32(cpu, RegDY, count);
4015: return;
4016: case 1: // LSR.L #qqq,Dy
4017: CYCLE(4);
4018: count = RegIRX;
4019: count = (count == 0) ? 8 : count;
4020: __assume(1 <= count && count <= 8);
4021: RegDY = acc_lsr_32(cpu, RegDY, count);
4022: return;
4023: case 2: // ROXR.L #qqq,Dy
4024: CYCLE(12);
4025: count = RegIRX;
4026: count = (count == 0) ? 8 : count;
4027: __assume(1 <= count && count <= 8);
4028: RegDY = acc_roxr_32(cpu, RegDY, count);
4029: return;
4030: case 3: // ROR.L #qqq,Dy
4031: CYCLE(6);
4032: count = RegIRX;
4033: count = (count == 0) ? 8 : count;
4034: __assume(1 <= count && count <= 8);
4035: RegDY = acc_ror_32(cpu, RegDY, count);
4036: return;
4037: case 4: // ASR.L Dx,Dy
4038: count = RegDX & 63;
4039: // シフト数がデータサイズを越えるかどうかでサイクルが違う
4040: CYCLE(count <= 32 ? 6 : 10);
4041: __assume(0 <= count && count < 64);
4042: RegDY = acc_asr_32(cpu, RegDY, count);
4043: return;
4044: case 5: // LSR.L Dx,Dy
4045: count = RegDX & 63;
4046: // シフト数がデータサイズを越えるかどうかでサイクルが違う
4047: CYCLE(count <= 32 ? 6 : 8);
4048: __assume(0 <= count && count < 64);
4049: RegDY = acc_lsr_32(cpu, RegDY, count);
4050: return;
4051: case 6: // ROXR.L Dx,Dy
4052: CYCLE(12);
4053: count = RegDX & 63;
4054: __assume(0 <= count && count < 64);
4055: RegDY = acc_roxr_32(cpu, RegDY, count);
4056: return;
4057: case 7: // ROR.L Dx,Dy
4058: CYCLE(8);
4059: count = RegDX & 63;
4060: __assume(0 <= count && count < 64);
4061: RegDY = acc_ror_32(cpu, RegDY, count);
4062: return;
4063: }
4064: }
4065:
4066: // %1110_000011_mmmrrr ASR.W <ea>
4067: OP_DEF(asr_w)
4068: {
4069: CYCLE(4);
4070: uint32 ea = cea_data_16(cpu);
4071: uint32 data = m68030_read_16(cpu, ea);
4072: data = acc_asr_16(cpu, data, 1);
4073: m68030_write_16(cpu, ea, data);
4074: }
4075:
4076: // %1110_qqq100_000yyy ASL.B #qqq,Dy
4077: // %1110_qqq100_001yyy LSL.B #qqq,Dy
4078: // %1110_qqq100_010yyy ROXL.B #qqq,Dy
4079: // %1110_qqq100_011yyy ROL.B #qqq,Dy
4080: // %1110_xxx100_100yyy ASL.B Dx,Dy
4081: // %1110_xxx100_101yyy LSL.B Dx,Dy
4082: // %1110_xxx100_110yyy ROXL.B Dx,Dy
4083: // %1110_xxx100_111yyy ROL.B Dx,Dy
4084: OP_DEF(asl_b_imm)
4085: {
4086: int count;
4087: uint32 data;
4088: switch (eamode(RegIR)) {
4089: case 0: // ASL.B #qqq,Dy
4090: CYCLE(6);
4091: count = RegIRX;
4092: count = (count == 0) ? 8 : count;
4093: __assume(1 <= count && count <= 8);
4094: data = acc_asl_8(cpu, RegDY & 0xff, count);
4095: RegDY = (RegDY & 0xffffff00) | data;
4096: return;
4097: case 1: // LSL.B #qqq,Dy
4098: CYCLE(4);
4099: count = RegIRX;
4100: count = (count == 0) ? 8 : count;
4101: __assume(1 <= count && count <= 8);
4102: data = acc_lsl_8(cpu, RegDY & 0xff, count);
4103: RegDY = (RegDY & 0xffffff00) | data;
4104: return;
4105: case 2: // ROXL.B #qqq,Dy
4106: CYCLE(12);
4107: count = RegIRX;
4108: count = (count == 0) ? 8 : count;
4109: __assume(1 <= count && count <= 8);
4110: data = acc_roxl_8(cpu, RegDY & 0xff, count);
4111: RegDY = (RegDY & 0xffffff00) | data;
4112: return;
4113: case 3: // ROL.B #qqq,Dy
4114: CYCLE(6);
4115: count = RegIRX;
4116: count = (count == 0) ? 8 : count;
4117: __assume(1 <= count && count <= 8);
4118: data = acc_rol_8(cpu, RegDY & 0xff, count);
4119: RegDY = (RegDY & 0xffffff00) | data;
4120: return;
4121: case 4: // ASL.B Dx,Dy
4122: CYCLE(8);
4123: count = RegDX & 63;
4124: __assume(0 <= count && count < 64);
4125: data = acc_asl_8(cpu, RegDY & 0xff, count);
4126: RegDY = (RegDY & 0xffffff00) | data;
4127: return;
4128: case 5: // LSL.B Dx,Dy
4129: count = RegDX & 63;
4130: // シフト数がデータサイズを越えるかどうかでサイクルが違う
4131: CYCLE(count <= 8 ? 6 : 8);
4132: __assume(0 <= count && count < 64);
4133: data = acc_lsl_8(cpu, RegDY & 0xff, count);
4134: RegDY = (RegDY & 0xffffff00) | data;
4135: return;
4136: case 6: // ROXL.B Dx,Dy
4137: CYCLE(12);
4138: count = RegDX & 63;
4139: __assume(0 <= count && count < 64);
4140: data = acc_roxl_8(cpu, RegDY & 0xff, count);
4141: RegDY = (RegDY & 0xffffff00) | data;
4142: return;
4143: case 7: // ROL.B Dx,Dy
4144: CYCLE(8);
4145: count = RegDX & 63;
4146: __assume(0 <= count && count < 64);
4147: data = acc_rol_8(cpu, RegDY & 0xff, count);
4148: RegDY = (RegDY & 0xffffff00) | data;
4149: return;
4150: }
4151: }
4152:
4153: // %1110_qqq101_000yyy ASL.W #qqq,Dy
4154: // %1110_qqq101_001yyy LSL.W #qqq,Dy
4155: // %1110_qqq101_010yyy ROXL.W #qqq,Dy
4156: // %1110_qqq101_011yyy ROL.W #qqq,Dy
4157: // %1110_xxx101_100yyy ASL.W Dx,Dy
4158: // %1110_xxx101_101yyy LSL.W Dx,Dy
4159: // %1110_xxx101_110yyy ROXL.W Dx,Dy
4160: // %1110_xxx101_111yyy ROL.W Dx,Dy
4161: OP_DEF(asl_w_imm)
4162: {
4163: int count;
4164: uint32 data;
4165: switch (eamode(RegIR)) {
4166: case 0: // ASL.W #qqq,Dy
4167: CYCLE(6);
4168: count = RegIRX;
4169: count = (count == 0) ? 8 : count;
4170: __assume(1 <= count && count <= 8);
4171: data = acc_asl_16(cpu, RegDY & 0xffff, count);
4172: RegDY = (RegDY & 0xffff0000) | data;
4173: return;
4174: case 1: // LSL.W #qqq,Dy
4175: CYCLE(4);
4176: count = RegIRX;
4177: count = (count == 0) ? 8 : count;
4178: __assume(1 <= count && count <= 8);
4179: data = acc_lsl_16(cpu, RegDY & 0xffff, count);
4180: RegDY = (RegDY & 0xffff0000) | data;
4181: return;
4182: case 2: // ROXL.W #qqq,Dy
4183: CYCLE(12);
4184: count = RegIRX;
4185: count = (count == 0) ? 8 : count;
4186: __assume(1 <= count && count <= 8);
4187: data = acc_roxl_16(cpu, RegDY & 0xffff, count);
4188: RegDY = (RegDY & 0xffff0000) | data;
4189: return;
4190: case 3: // ROL.W #qqq,Dy
4191: CYCLE(6);
4192: count = RegIRX;
4193: count = (count == 0) ? 8 : count;
4194: __assume(1 <= count && count <= 8);
4195: data = acc_rol_16(cpu, RegDY & 0xffff, count);
4196: RegDY = (RegDY & 0xffff0000) | data;
4197: return;
4198: case 4: // ASL.W Dx,Dy
4199: CYCLE(8);
4200: count = RegDX & 63;
4201: __assume(0 <= count && count < 64);
4202: data = acc_asl_16(cpu, RegDY & 0xffff, count);
4203: RegDY = (RegDY & 0xffff0000) | data;
4204: return;
4205: case 5: // LSL.W Dx,Dy
4206: count = RegDX & 63;
4207: // シフト数がデータサイズを越えるかどうかでサイクルが違う
4208: CYCLE(count <= 16 ? 6 : 8);
4209: __assume(0 <= count && count < 64);
4210: data = acc_lsl_16(cpu, RegDY & 0xffff, count);
4211: RegDY = (RegDY & 0xffff0000) | data;
4212: return;
4213: case 6: // ROXL.W Dx,Dy
4214: CYCLE(12);
4215: count = RegDX & 63;
4216: __assume(0 <= count && count < 64);
4217: data = acc_roxl_16(cpu, RegDY & 0xffff, count);
4218: RegDY = (RegDY & 0xffff0000) | data;
4219: return;
4220: case 7: // ROL.W Dx,Dy
4221: CYCLE(8);
4222: count = RegDX & 63;
4223: __assume(0 <= count && count < 64);
4224: data = acc_rol_16(cpu, RegDY & 0xffff, count);
4225: RegDY = (RegDY & 0xffff0000) | data;
4226: return;
4227: }
4228: }
4229:
4230: // %1110_qqq110_000yyy ASL.L #qqq,Dy
4231: // %1110_qqq110_001yyy LSL.L #qqq,Dy
4232: // %1110_qqq110_010yyy ROXL.L #qqq,Dy
4233: // %1110_qqq110_011yyy ROL.L #qqq,Dy
4234: // %1110_xxx110_100yyy ASL.L Dx,Dy
4235: // %1110_xxx110_101yyy LSL.L Dx,Dy
4236: // %1110_xxx110_110yyy ROXL.L Dx,Dy
4237: // %1110_xxx110_111yyy ROL.L Dx,Dy
4238: OP_DEF(asl_l_imm)
4239: {
4240: int count;
4241: switch (eamode(RegIR)) {
4242: case 0: // ASL.L #qqq,Dy
4243: CYCLE(6);
4244: count = RegIRX;
4245: count = (count == 0) ? 8 : count;
4246: __assume(1 <= count && count <= 8);
4247: RegDY = acc_asl_32(cpu, RegDY, count);
4248: return;
4249: case 1: // LSL.L #qqq,Dy
4250: CYCLE(4);
4251: count = RegIRX;
4252: count = (count == 0) ? 8 : count;
4253: __assume(1 <= count && count <= 8);
4254: RegDY = acc_lsl_32(cpu, RegDY, count);
4255: return;
4256: case 2: // ROXL.L #qqq,Dy
4257: CYCLE(12);
4258: count = RegIRX;
4259: count = (count == 0) ? 8 : count;
4260: __assume(1 <= count && count <= 8);
4261: RegDY = acc_roxl_32(cpu, RegDY, count);
4262: return;
4263: case 3: // ROL.L #qqq,Dy
4264: CYCLE(6);
4265: count = RegIRX;
4266: count = (count == 0) ? 8 : count;
4267: __assume(1 <= count && count <= 8);
4268: RegDY = acc_rol_32(cpu, RegDY, count);
4269: return;
4270: case 4: // ASL.L Dx,Dy
4271: CYCLE(8);
4272: count = RegDX & 63;
4273: __assume(0 <= count && count < 64);
4274: RegDY = acc_asl_32(cpu, RegDY, count);
4275: return;
4276: case 5: // LSL.L Dx,Dy
4277: count = RegDX & 63;
4278: // シフト数がデータサイズを越えるかどうかでサイクルが違う
4279: CYCLE(count <= 32 ? 6 : 8);
4280: __assume(0 <= count && count < 64);
4281: RegDY = acc_lsl_32(cpu, RegDY, count);
4282: return;
4283: case 6: // ROXL.L Dx,Dy
4284: CYCLE(12);
4285: count = RegDX & 63;
4286: __assume(0 <= count && count < 64);
4287: RegDY = acc_roxl_32(cpu, RegDY, count);
4288: return;
4289: case 7: // ROL.L Dx,Dy
4290: CYCLE(8);
4291: count = RegDX & 63;
4292: __assume(0 <= count && count < 64);
4293: RegDY = acc_rol_32(cpu, RegDY, count);
4294: return;
4295: }
4296: }
4297:
4298: // %1110_000111_mmmrrr ASL.W <ea>
4299: OP_DEF(asl_w)
4300: {
4301: CYCLE(6);
4302: uint32 ea = cea_data_16(cpu);
4303: uint32 data = m68030_read_16(cpu, ea);
4304: data = acc_asl_16(cpu, data, 1);
4305: m68030_write_16(cpu, ea, data);
4306: }
4307:
4308: // %1110_001011_mmmrrr LSR.W <ea>
4309: OP_DEF(lsr_w)
4310: {
4311: CYCLE(4);
4312: uint32 ea = cea_data_16(cpu);
4313: uint32 data = m68030_read_16(cpu, ea);
4314: data = acc_lsr_16(cpu, data, 1);
4315: m68030_write_16(cpu, ea, data);
4316: }
4317:
4318: // %1110_001111_mmmrrr LSL.W <ea>
4319: OP_DEF(lsl_w)
4320: {
4321: CYCLE(4);
4322: uint32 ea = cea_data_16(cpu);
4323: uint32 data = m68030_read_16(cpu, ea);
4324: data = acc_lsl_16(cpu, data, 1);
4325: m68030_write_16(cpu, ea, data);
4326: }
4327:
4328: // %1110_010011_mmmrrr ROXR.W <ea>
4329: OP_DEF(roxr_w)
4330: {
4331: CYCLE(4);
4332: uint32 ea = cea_data_16(cpu);
4333: uint32 data = m68030_read_16(cpu, ea);
4334: data = acc_roxr_16(cpu, data, 1);
4335: m68030_write_16(cpu, ea, data);
4336: }
4337:
4338: // %1110_010111_mmmrrr ROXL.W <ea>
4339: OP_DEF(roxl_w)
4340: {
4341: CYCLE(4);
4342: uint32 ea = cea_data_16(cpu);
4343: uint32 data = m68030_read_16(cpu, ea);
4344: data = acc_roxl_16(cpu, data, 1);
4345: m68030_write_16(cpu, ea, data);
4346: }
4347:
4348: // %1110_011011_mmmrrr ROR.W <ea>
4349: OP_DEF(ror_w)
4350: {
4351: CYCLE(6);
4352: uint32 ea = cea_data_16(cpu);
4353: uint32 data = m68030_read_16(cpu, ea);
4354: data = acc_ror_16(cpu, data, 1);
4355: m68030_write_16(cpu, ea, data);
4356: }
4357:
4358: // %1110_011111_mmmrrr ROL.W <ea>
4359: OP_DEF(rol_w)
4360: {
4361: CYCLE(6);
4362: uint32 ea = cea_data_16(cpu);
4363: uint32 data = m68030_read_16(cpu, ea);
4364: data = acc_rol_16(cpu, data, 1);
4365: m68030_write_16(cpu, ea, data);
4366: }
4367:
4368: // %1110_100011_mmmrrr BFTST <ea>{#o:#w}
4369: OP_DEF(bftst)
4370: {
4371: uint n = RegIR & 0x3f;
4372: RegIR2 = m68030_fetch_16(cpu);
4373:
4374: acc_bf bf(cpu);
4375: if (n < 8) {
4376: // BFTST Dn{#o:#w}
4377: bf.LoadReg(n);
4378: } else {
4379: // BFTST <ea>{#o:#w}
4380: uint32 ea = cea_ctrl(cpu);
4381: bf.LoadMem(ea);
4382: }
4383: acc_move_32(cpu, bf.data);
4384: }
4385:
4386: // %1110_100111_mmmrrr BFEXTU <ea>{#o:#w},Dn
4387: OP_DEF(bfextu)
4388: {
4389: uint n = RegIR & 0x3f;
4390: RegIR2 = m68030_fetch_16(cpu);
4391: uint dn = RegIR2 >> 12;
4392:
4393: acc_bf bf(cpu);
4394: if (n < 8) {
4395: // BFEXTU Dn{#o:#w},Dn
4396: bf.LoadReg(n);
4397: } else {
4398: // BFEXTU <ea>{#o:#w},Dn
4399: uint32 ea = cea_ctrl(cpu);
4400: bf.LoadMem(ea);
4401: }
4402: // CCR は操作前のビットフィールドに対して
4403: acc_move_32(cpu, bf.data);
4404: // 符号なしシフト
4405: RegD(dn) = bf.data >> (32 - bf.width);
4406: }
4407:
4408: // %1110_101011_mmmrrr BFCHG <ea>{#o:#w}
4409: OP_DEF(bfchg)
4410: {
4411: uint n = RegIR & 0x3f;
4412: RegIR2 = m68030_fetch_16(cpu);
4413:
4414: acc_bf bf(cpu);
4415: if (n < 8) {
4416: // BFCHG Dn{#o:#w}
4417: bf.LoadReg(n);
4418: } else if (n >= 0x3a) {
4419: // BFCHG <ea> に PC 相対(と #imm) はない
4420: op_illegal(cpu);
4421: } else {
4422: // BFCHG <ea>{#o:#w}
4423: uint32 ea = cea_ctrl(cpu);
4424: bf.LoadMem(ea);
4425: }
4426: // CCR は操作前のビットフィールドに対して
4427: acc_move_32(cpu, bf.data);
4428: bf.data = ~bf.data;
4429: bf.Store(n);
4430: }
4431:
4432: // %1110_101111_mmmrrr BFEXTS <ea>{#o:#w},Dn
4433: OP_DEF(bfexts)
4434: {
4435: uint n = RegIR & 0x3f;
4436: RegIR2 = m68030_fetch_16(cpu);
4437: uint dn = RegIR2 >> 12;
4438:
4439: acc_bf bf(cpu);
4440: if (n < 8) {
4441: // BFEXTS Dn{#o:#w},Dn
4442: bf.LoadReg(n);
4443: } else {
4444: // BFEXTS <ea>{#o:#w},Dn
4445: uint32 ea = cea_ctrl(cpu);
4446: bf.LoadMem(ea);
4447: }
4448: // CCR は操作前のビットフィールドに対して
4449: acc_move_32(cpu, bf.data);
4450: // 符号付きシフト
4451: // XXX 負数の右シフト
4452: RegD(dn) = ((int32)bf.data) >> (32 - bf.width);
4453: }
4454:
4455: // %1110_110011_mmmrrr BFCLR <ea>{#o:#w}
4456: OP_DEF(bfclr)
4457: {
4458: uint n = RegIR & 0x3f;
4459: RegIR2 = m68030_fetch_16(cpu);
4460:
4461: acc_bf bf(cpu);
4462: if (n < 8) {
4463: // BFCLR Dn{#o:#w}
4464: bf.LoadReg(n);
4465: } else if (n >= 0x3a) {
4466: // BFCLR <ea> に PC 相対(と #imm) はない
4467: op_illegal(cpu);
4468: } else {
4469: // BFCLR <ea>{#o:#w}
4470: uint32 ea = cea_ctrl(cpu);
4471: bf.LoadMem(ea);
4472: }
4473: // CCR は操作前のビットフィールドに対して
4474: acc_move_32(cpu, bf.data);
4475: bf.data = 0;
4476: bf.Store(n);
4477: }
4478:
4479: // %1110_110111_mmmrrr BFFFO <ea>{#o:#w},Dn
4480: OP_DEF(bfffo)
4481: {
4482: uint n = RegIR & 0x3f;
4483: RegIR2 = m68030_fetch_16(cpu);
4484: uint dn = RegIR2 >> 12;
4485:
4486: acc_bf bf(cpu);
4487: if (n < 8) {
4488: // BFFFO Dn{#o:#w},Dn
4489: bf.LoadReg(n);
4490: } else {
4491: // BFFFO <ea>{#o:#w},Dn
4492: uint32 ea = cea_ctrl(cpu);
4493: bf.LoadMem(ea);
4494: }
4495: // CCR は操作前のビットフィールドに対して
4496: acc_move_32(cpu, bf.data);
4497: // 1 になっているビットを探す
4498: for (; (int)bf.width-- > 0 && (int32)bf.data >= 0; bf.data <<= 1) {
4499: bf.offset++;
4500: }
4501: RegD(dn) = bf.offset;
4502: }
4503:
4504: // %1110_111011_mmmrrr BFSET <ea>{#o:#w}
4505: OP_DEF(bfset)
4506: {
4507: uint n = RegIR & 0x3f;
4508: RegIR2 = m68030_fetch_16(cpu);
4509:
4510: acc_bf bf(cpu);
4511: if (n < 8) {
4512: // BFSET Dn{#o:#w}
4513: bf.LoadReg(n);
4514: } else if (n >= 0x3a) {
4515: // BFSET <ea> に PC 相対(と #imm) はない
4516: op_illegal(cpu);
4517: } else {
4518: // BFSET <ea>{#o:#w}
4519: uint32 ea = cea_ctrl(cpu);
4520: bf.LoadMem(ea);
4521: }
4522: // CCR は操作前のビットフィールドに対して
4523: acc_move_32(cpu, bf.data);
4524: bf.data = 0xffffffff;
4525: bf.Store(n);
4526: }
4527:
4528: // %1110_111111_mmmrrr BFINS Dn,<ea>{#o:#w}
4529: OP_DEF(bfins)
4530: {
4531: uint n = RegIR & 0x3f;
4532: RegIR2 = m68030_fetch_16(cpu);
4533: uint dn = RegIR2 >> 12;
4534:
4535: acc_bf bf(cpu);
4536: if (n < 8) {
4537: // BFINS Dm,Dn{#o:#w}
4538: bf.LoadReg(n);
4539: } else if (n >= 0x3a) {
4540: // BFINS Dn,<ea> に PC 相対(と #imm) はない
4541: op_illegal(cpu);
4542: } else {
4543: // BFINS Dn,<ea>{#o:#w}
4544: uint32 ea = cea_ctrl(cpu);
4545: bf.LoadMem(ea);
4546: }
4547: bf.data = RegD(dn) << (32 - bf.width);
4548: // BFINS のみ CCR は操作後のビットフィールドに対して
4549: acc_move_32(cpu, bf.data);
4550: bf.Store(n);
4551: }
4552:
4553: // %1111_000nnn_nnnnnn MMU_OP
4554: OP_DEF(mmuop)
4555: {
4556: cpu->ir2 = m68030_fetch_16(cpu);
4557: switch ((cpu->ir2 >> 8) & 0xff) {
4558: case (0x0800 >> 8):
4559: case (0x0900 >> 8):
4560: case (0x0c00 >> 8):
4561: case (0x0d00 >> 8):
4562: // %000_01n00_000_00000 PMOVE.L <ea>,TTn
4563: // %000_01n01_000_00000 PMOVEFD.L <ea>,TTn
4564: {
4565: CYCLE2(12, 14);
4566: uint32 ea = cea_copro(cpu);
4567: uint32 data = m68030_read_32(cpu, ea);
4568: int n = (RegIR2 >> 10) & 1;
4569: cpu->SetTT(n, data);
4570: if ((RegIR2 & 0x0100) == 0)
4571: cpu->atc.flush();
4572: break;
4573: }
4574: case (0x0a00 >> 8):
4575: case (0x0e00 >> 8):
4576: // %000_01n10_000_00000 PMOVE.L TTn,<ea>
4577: {
4578: CYCLE(8);
4579: uint32 ea = cea_copro(cpu);
4580: int n = (RegIR2 >> 10) & 1;
4581: m68030_write_32(cpu, ea, cpu->GetTT(n));
4582: break;
4583: }
4584: case (0x2000 >> 8):
4585: // %001_00000_000_00000 PLOADW SFC,<ea>
4586: // %001_00000_000_00001 PLOADW DFC,<ea>
4587: // %001_00000_000_01yyy PLOADW Dy,<ea>
4588: // %001_00000_000_10nnn PLOADW #<imm>,<ea>
4589: {
4590: cpulog(0, "ploadw");
4591: mmu_op_pload(cpu);
4592: break;
4593: }
4594: case (0x2200 >> 8):
4595: // %001_00010_000_00000 PLOADR SFC,<ea>
4596: // %001_00010_000_00001 PLOADR DFC,<ea>
4597: // %001_00010_000_01yyy PLOADR Dy,<ea>
4598: // %001_00010_000_10nnn PLOADR #<imm>,<ea>
4599: {
4600: cpulog(0, "ploadr");
4601: mmu_op_pload(cpu);
4602: break;
4603: }
4604: case (0x2400 >> 8):
4605: // %001_00100_000_00000 PFLUSHA
4606: {
4607: CYCLE2(12, 14);
4608: cpu->atc.flush();
4609: break;
4610: }
4611: case (0x3000 >> 8):
4612: // %001_10000_nnn_00000 PFLUSH SFC,#<mask>
4613: // %001_10000_nnn_00001 PFLUSH DFC,#<mask>
4614: // %001_10000_nnn_01yyy PFLUSH Dy,#<mask>
4615: // %001_10000_nnn_10nnn PFLUSH #<imm>,#<mask>
4616: {
4617: mmu_op_pflush(cpu);
4618: break;
4619: }
4620: case (0x3800 >> 8):
4621: // %001_11000_nnn_00000 PFLUSH SFC,#<mask>,<ea>
4622: // %001_11000_nnn_00001 PFLUSH DFC,#<mask>,<ea>
4623: // %001_11000_nnn_01yyy PFLUSH Dy,#<mask>,<ea>
4624: // %001_11000_nnn_10nnn PFLUSH #<imm>,#<mask>,<ea>
4625: {
4626: mmu_op_pflush_ea(cpu);
4627: break;
4628: }
4629: case (0x4000 >> 8):
4630: case (0x4100 >> 8):
4631: // %010_00000_000_00000 PMOVE.L <ea>,TC
4632: // %010_00001_000_00000 PMOVEFD.L <ea>,TC
4633: {
4634: // たぶん
4635: // 無効→有効が (38, 40)
4636: // 有効→無効が (56, 58)
4637: // 無効→無効が (14, 16) ってことだと思うんだけど。
4638: CYCLE2(14, 16);
4639: uint32 ea = cea_copro(cpu);
4640: uint32 data = m68030_read_32(cpu, ea);
4641: if (cpu->SetTC(data) == false) {
4642: m68030_exception(cpu, M68K_EXCEP_MMU_CONFIG);
4643: break;
4644: }
4645: if ((RegIR2 & 0x0100) == 0)
4646: cpu->atc.flush();
4647: break;
4648: }
4649: case (0x4200 >> 8):
4650: // %010_00010_000_00000 PMOVE.L TC,<ea>
4651: {
4652: CYCLE2(4, 5);
4653: uint32 ea = cea_copro(cpu);
4654: m68030_write_32(cpu, ea, cpu->GetTC());
4655: break;
4656: }
4657: case (0x4800 >> 8):
4658: case (0x4900 >> 8):
4659: // %010_01000_000_00000 PMOVE.Q <ea>,SRP
4660: // %010_01001_000_00000 PMOVEFD.Q <ea>,SRP
4661: {
4662: // たぶん有効になる時が (12, 14)
4663: // それ以外が (28, 30) ってことかな。
4664: CYCLE2(28, 30);
4665: uint32 ea = cea_copro(cpu);
4666: uint32 h = m68030_read_32(cpu, ea);
4667: uint32 l = m68030_read_32(cpu, ea + 4);
4668: cpu->SetSRP(h, l);
4669: if ((RegIR2 & 0x0100) == 0)
4670: cpu->atc.flush();
4671: break;
4672: }
4673: case (0x4a00 >> 8):
4674: // %010_01010_000_00000 PMOVE.Q SRP,<ea>
4675: {
4676: CYCLE2(4, 5);
4677: uint32 ea = cea_copro(cpu);
4678: m68030_write_32(cpu, ea, cpu->GetSRPh());
4679: m68030_write_32(cpu, ea + 4, cpu->GetSRPl());
4680: break;
4681: }
4682: case (0x4c00 >> 8):
4683: case (0x4d00 >> 8):
4684: // %010_01100_000_00000 PMOVE.Q <ea>,CRP
4685: // %010_01101_000_00000 PMOVEFD.Q <ea>,CRP
4686: {
4687: // たぶん有効になる時が (12, 14)
4688: // それ以外が (28, 30) ってことかな。
4689: CYCLE2(28, 30);
4690: uint32 ea = cea_copro(cpu);
4691: uint32 h = m68030_read_32(cpu, ea);
4692: uint32 l = m68030_read_32(cpu, ea + 4);
4693: cpu->SetCRP(h, l);
4694: if ((RegIR2 & 0x0100) == 0)
4695: cpu->atc.flush();
4696: break;
4697: }
4698: case (0x4e00 >> 8):
4699: // %010_01110_000_00000 PMOVE.Q CRP,<ea>
4700: {
4701: CYCLE2(4, 5);
4702: uint32 ea = cea_copro(cpu);
4703: m68030_write_32(cpu, ea, cpu->GetCRPh());
4704: m68030_write_32(cpu, ea + 4, cpu->GetCRPl());
4705: break;
4706: }
4707: case (0x6000 >> 8):
4708: // %011_00000_000_00000 PMOVE.W <ea>,MMUSR
4709: {
4710: CYCLE(6);
4711: uint32 ea = cea_copro(cpu);
4712: uint16 data = m68030_read_16(cpu, ea);
4713: cpu->SetMMUSR(data);
4714: break;
4715: }
4716: case (0x6200 >> 8):
4717: // %011_00010_000_00000 PMOVE.W MMUSR,<ea>
4718: {
4719: CYCLE2(4, 5);
4720: uint32 ea = cea_copro(cpu);
4721: m68030_write_16(cpu, ea, cpu->GetMMUSR());
4722: break;
4723: }
4724: case (0x8000 >> 8):
4725: case (0x8400 >> 8):
4726: case (0x8800 >> 8):
4727: case (0x8c00 >> 8):
4728: case (0x9000 >> 8):
4729: case (0x9400 >> 8):
4730: case (0x9800 >> 8):
4731: case (0x9c00 >> 8):
4732: // %100_nnn00_000_00000 PTESTW SFC,<ea>,#<level>
4733: // %100_nnn00_000_00001 PTESTW DFC,<ea>,#<level>
4734: // %100_nnn00_000_01yyy PTESTW Dy,<ea>,#<level>
4735: // %100_nnn00_000_10nnn PTESTW #<imm>,<ea>,#<level>
4736: {
4737: mmu_op_ptest(cpu);
4738: break;
4739: }
4740: case (0x8100 >> 8):
4741: case (0x8500 >> 8):
4742: case (0x8900 >> 8):
4743: case (0x8d00 >> 8):
4744: case (0x9100 >> 8):
4745: case (0x9500 >> 8):
4746: case (0x9900 >> 8):
4747: case (0x9d00 >> 8):
4748: // %100_nnn01_nnn_00000 PTESTW SFC,<ea>,#<level>,An
4749: // %100_nnn01_nnn_00001 PTESTW DFC,<ea>,#<level>,An
4750: // %100_nnn01_nnn_01yyy PTESTW Dy,<ea>,#<level>,An
4751: // %100_nnn01_nnn_10nnn PTESTW #<imm>,<ea>,#<level>,An
4752: {
4753: mmu_op_ptest(cpu);
4754: break;
4755: }
4756: case (0x8200 >> 8):
4757: case (0x8600 >> 8):
4758: case (0x8a00 >> 8):
4759: case (0x8e00 >> 8):
4760: case (0x9200 >> 8):
4761: case (0x9600 >> 8):
4762: case (0x9a00 >> 8):
4763: case (0x9e00 >> 8):
4764: // %100_nnn10_000_00000 PTESTR SFC,<ea>,#<level>
4765: // %100_nnn10_000_00001 PTESTR DFC,<ea>,#<level>
4766: // %100_nnn10_000_01yyy PTESTR Dy,<ea>,#<level>
4767: // %100_nnn10_000_10nnn PTESTR #<imm>,<ea>,#<level>
4768: {
4769: mmu_op_ptest(cpu);
4770: break;
4771: }
4772: case (0x8300 >> 8):
4773: case (0x8700 >> 8):
4774: case (0x8b00 >> 8):
4775: case (0x8f00 >> 8):
4776: case (0x9300 >> 8):
4777: case (0x9700 >> 8):
4778: case (0x9b00 >> 8):
4779: case (0x9f00 >> 8):
4780: // %100_nnn11_nnn_00000 PTESTR SFC,<ea>,#<level>,An
4781: // %100_nnn11_nnn_00001 PTESTR DFC,<ea>,#<level>,An
4782: // %100_nnn11_nnn_01yyy PTESTR Dy,<ea>,#<level>,An
4783: // %100_nnn11_nnn_10nnn PTESTR #<imm>,<ea>,#<level>,An
4784: {
4785: mmu_op_ptest(cpu);
4786: break;
4787: }
4788: default:
4789: OP_FUNC(illegal);
4790: break;
4791: }
4792: }
4793:
4794: // %1111_001000_nnnnnn FPGEN
4795: OP_DEF(fpgen)
4796: {
4797: if (cpu->has_fpu == 0) {
4798: op_fline(cpu);
4799: return;
4800: }
4801:
4802: fpu_op_start(cpu);
4803:
4804: RegIR2 = m68030_fetch_16(cpu);
4805: switch (RegIR2 >> 13) {
4806: case 0:
4807: fpu_op_fgen_reg(cpu);
4808: break;
4809: case 1:
4810: fpu_op_illg(cpu);
4811: break;
4812: case 2:
4813: fpu_op_fgen_mem(cpu);
4814: break;
4815: case 3:
4816: {
4817: // FMOVE reg,<ea> はサイズごとに分岐
4818: int size = (RegIR2 >> 10) & 7;
4819: switch (size) {
4820: case SIZE_B:
4821: fpu_op_fmove_b_mem(cpu);
4822: break;
4823: case SIZE_W:
4824: fpu_op_fmove_w_mem(cpu);
4825: break;
4826: case SIZE_L:
4827: fpu_op_fmove_l_mem(cpu);
4828: break;
4829: case SIZE_S:
4830: fpu_op_fmove_s_mem(cpu);
4831: break;
4832: case SIZE_D:
4833: fpu_op_fmove_d_mem(cpu);
4834: break;
4835: case SIZE_X:
4836: fpu_op_fmove_x_mem(cpu);
4837: break;
4838: case SIZE_P:
4839: case 7:
4840: fpu_op_fmove_p_mem(cpu);
4841: break;
4842: }
4843: break;
4844: }
4845: case 4:
4846: fpu_op_fmovem_ea2ctl(cpu);
4847: break;
4848: case 5:
4849: fpu_op_fmovem_ctl2ea(cpu);
4850: break;
4851: case 6:
4852: fpu_op_fmovem_ea2reg(cpu);
4853: break;
4854: case 7:
4855: fpu_op_fmovem_reg2ea(cpu);
4856: break;
4857: }
4858: }
4859:
4860: // %1111_001001_nnnnnn FScc.B <ea>
4861: // %1111_001001_001yyy FDBcc Dy,<label>
4862: // %1111_001001_111010 FTRAPcc.W #<imm>
4863: // %1111_001001_111011 FTRAPcc.L #<imm>
4864: // %1111_001001_111100 FTRAPcc
4865: OP_DEF(fxcc)
4866: {
4867: if (cpu->has_fpu == 0) {
4868: op_fline(cpu);
4869: return;
4870: }
4871:
4872: fpu_op_start(cpu);
4873:
4874: RegIR2 = m68030_fetch_16(cpu);
4875: switch (eamode(RegIR)) {
4876: case 1:
4877: fpu_op_fdbcc(cpu);
4878: return;
4879: case 7:
4880: switch (RegIR & 7) {
4881: case 0:
4882: case 1:
4883: fpu_op_fscc(cpu);
4884: return;
4885: case 2:
4886: fpu_op_ftrapcc_w(cpu);
4887: return;
4888: case 3:
4889: fpu_op_ftrapcc_l(cpu);
4890: return;
4891: case 4:
4892: fpu_op_ftrapcc(cpu);
4893: return;
4894: default:
4895: break;
4896: }
4897: break;
4898: default:
4899: fpu_op_fscc(cpu);
4900: return;
4901: }
4902: }
4903:
4904: // %1111_001010_nnnnnn FBcc.W <label>
4905: OP_DEF(fbcc_w)
4906: {
4907: if (cpu->has_fpu == 0) {
4908: op_fline(cpu);
4909: return;
4910: }
4911:
4912: fpu_op_start(cpu);
4913:
4914: fpu_op_fbcc_w(cpu);
4915: }
4916:
4917: // %1111_001011_nnnnnn FBcc.L <label>
4918: OP_DEF(fbcc_l)
4919: {
4920: if (cpu->has_fpu == 0) {
4921: op_fline(cpu);
4922: return;
4923: }
4924:
4925: fpu_op_start(cpu);
4926:
4927: fpu_op_fbcc_l(cpu);
4928: }
4929:
4930: // %1111_001100_nnnnnn FSAVE <ea>
4931: OP_DEF(fsave)
4932: {
4933: if (cpu->has_fpu == 0) {
4934: op_fline(cpu);
4935: return;
4936: }
4937:
4938: SUPERVISOR_OP;
4939:
4940: fpu_op_fsave(cpu);
4941: }
4942:
4943: // %1111_001101_nnnnnn FRESTORE <ea>
4944: OP_DEF(frestore)
4945: {
4946: if (cpu->has_fpu == 0) {
4947: op_fline(cpu);
4948: return;
4949: }
4950:
4951: SUPERVISOR_OP;
4952:
4953: fpu_op_frestore(cpu);
4954: }
4955:
4956: // %1111_nnnnnn_nnnnnn F-Line
4957: OP_DEF(fline)
4958: {
4959: CYCLE2(18, 20);
4960:
4961: if (cpu->fline_callback) {
4962: if (cpu->fline_callback(cpu, cpu->fline_arg)) {
4963: return;
4964: }
4965: }
4966: // F系列命令例外
4967: m68030_exception(cpu, M68K_EXCEP_FLINE);
4968: }
4969:
4970: // illegal instructions
4971: OP_DEF(illegal)
4972: {
4973: CYCLE2(18, 20);
4974: // 不当命令例外
4975: m68030_exception(cpu, M68K_EXCEP_ILLEGAL);
4976: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.