--- nono/m680x0/m680x0ops.cpp 2026/04/29 17:05:40 1.1.1.2 +++ nono/m680x0/m680x0ops.cpp 2026/04/29 17:05:57 1.1.1.3 @@ -2627,7 +2627,13 @@ OP_DEF(trap) uint n = ir & 0x3f; switch (n) { - case 0x00 ... 0x0e:// TRAP # + case 0x00: // TRAP #0 + CYCLE3(trap); + // TRAP#0 例外 (NetBSD システムコール表示のため別処理) + ExceptionTrap0(); + return; + + case 0x01 ... 0x0e:// TRAP # CYCLE3(trap); // TRAP#N 例外 Exception(M68K::EXCEP_TRAP0 + n); @@ -2972,9 +2978,9 @@ OP_DEF(scc) return; default: - OP_FUNC(illegal); - return; + break; } + OP_FUNC(illegal); } // %0101_qqq100_mmmrrr d.m+-rxw.. 034 SUBQ.B #qqq, @@ -3291,14 +3297,9 @@ OP_DEF(or_w_dn_ea) // PACK -(Ay),-(Ax),# CYCLE3(pack_an); uint32 imm = fetch_2(); - uint32 srcea; - uint32 src; - // -(Ay) を2回行う save_reg_pd(RegIRY); - srcea = internal_ea_anpd_1(RegIRY); - src = read_1(srcea); - srcea = internal_ea_anpd_1(RegIRY); - src |= (read_1(srcea) << 8); + uint32 srcea = internal_ea_anpd_2(RegIRY); + uint32 src = read_2(srcea); src += imm; uint32 dst = ((src >> 4) & 0x00f0) | (src & 0x000f); save_reg_pd_if(RegIRX); @@ -3339,13 +3340,9 @@ OP_DEF(or_l_dn_ea) uint16 src = read_1(srcea); src = ((src & 0x00f0) << 4) | (src & 0x000f); src += imm; - // -(Ax) を2回行う save_reg_pd_if(RegIRX); - uint32 dstea; - dstea = internal_ea_anpd_1(RegIRX); - write_1(dstea, (src & 0xff)); - dstea = internal_ea_anpd_1(RegIRX); - write_1(dstea, src >> 8); + uint32 dstea = internal_ea_anpd_2(RegIRX); + write_2(dstea, src); } else { // OR.L Dx, CYCLE3(or_dn_ea); @@ -3626,8 +3623,8 @@ OP_DEF(eor_b) uint32 ea = cea_data_1(); uint32 data = read_1(ea); data ^= (RegDX & 0xff); - write_1(ea, data); ACC.move_8(data); + write_1(ea, data); } } @@ -3659,8 +3656,8 @@ OP_DEF(eor_w) uint32 ea = cea_data_2(); uint32 data = read_2(ea); data ^= (RegDX & 0xffff); - write_2(ea, data); ACC.move_16(data); + write_2(ea, data); } } @@ -3691,8 +3688,8 @@ OP_DEF(eor_l) uint32 ea = cea_data_4(); uint32 data = read_4(ea); data ^= RegDX; - write_4(ea, data); ACC.move_32(data); + write_4(ea, data); } } @@ -4791,8 +4788,8 @@ OP_DEF(bfins) bf.Store(n); } -// %1111_000nnn_nnnnnn .......... -3- MMU_OP -OP_DEF(mmuop) +// %1111_000nnn_nnnnnn .......... -3- MMU30_OP +OP_DEF(mmu30) { // CPU ごとの virtual 関数になっている。 ops_mmu30(); @@ -4823,9 +4820,10 @@ MPU68030Device::ops_mmu30() uint32 data = read_4(ea); uint n = (ir2 >> 10) & 1; SetTT(n, data); - if ((ir2 & 0x0100) == 0) - atc.flush(); - break; + if ((ir2 & 0x0100) == 0) { + atc.FlushAll(); + } + return; } case (0x0a00 >> 8): case (0x0e00 >> 8): @@ -4835,7 +4833,7 @@ MPU68030Device::ops_mmu30() uint32 ea = cea_copro(); uint n = (ir2 >> 10) & 1; write_4(ea, GetTT(n)); - break; + return; } case (0x2000 >> 8): // %001_00000_000_00000 PLOADW SFC, @@ -4845,8 +4843,8 @@ MPU68030Device::ops_mmu30() { CYCLE3(pload); putlog(0, "ploadw"); - mmu_op_pload(); - break; + ops_mmu30_pload(); + return; } case (0x2200 >> 8): // %001_00010_000_00000 PLOADR SFC, @@ -4856,15 +4854,15 @@ putlog(0, "ploadw"); { CYCLE3(pload); putlog(0, "ploadr"); - mmu_op_pload(); - break; + ops_mmu30_pload(); + return; } case (0x2400 >> 8): // %001_00100_000_00000 PFLUSHA { CYCLE3(pflusha); - atc.flush(); - break; + ops_mmu30_pflusha(); + return; } case (0x3000 >> 8): // %001_10000_nnn_00000 PFLUSH SFC,# @@ -4873,8 +4871,8 @@ putlog(0, "ploadr"); // %001_10000_nnn_10nnn PFLUSH #,# { CYCLE3(pflush); - mmu_op_pflush(); - break; + ops_mmu30_pflush(); + return; } case (0x3800 >> 8): // %001_11000_nnn_00000 PFLUSH SFC,#, @@ -4883,8 +4881,8 @@ putlog(0, "ploadr"); // %001_11000_nnn_10nnn PFLUSH #,#, { CYCLE3(pflush); - mmu_op_pflush_ea(); - break; + ops_mmu30_pflush_ea(); + return; } case (0x4000 >> 8): case (0x4100 >> 8): @@ -4894,13 +4892,14 @@ putlog(0, "ploadr"); CYCLE3(pmove_ea_tc); uint32 ea = cea_copro(); uint32 data = read_4(ea); - if (SetTC(data) == false) { + if (SetTC(data)) { + if ((ir2 & 0x0100) == 0) { + atc.FlushAll(); + } + } else { Exception(M68K::EXCEP_MMU_CONFIG); - break; } - if ((ir2 & 0x0100) == 0) - atc.flush(); - break; + return; } case (0x4200 >> 8): // %010_00010_000_00000 PMOVE.L TC, @@ -4908,7 +4907,7 @@ putlog(0, "ploadr"); CYCLE3(pmove_tc_ea); uint32 ea = cea_copro(); write_4(ea, GetTC()); - break; + return; } case (0x4800 >> 8): case (0x4900 >> 8): @@ -4919,13 +4918,14 @@ putlog(0, "ploadr"); uint32 ea = cea_copro(); uint32 h = read_4(ea); uint32 l = read_4(ea + 4); - if (SetSRP(h, l) == false) { + if (SetSRP(h, l)) { + if ((ir2 & 0x0100) == 0) { + atc.FlushAll(); + } + } else { Exception(M68K::EXCEP_MMU_CONFIG); - break; } - if ((ir2 & 0x0100) == 0) - atc.flush(); - break; + return; } case (0x4a00 >> 8): // %010_01010_000_00000 PMOVE.Q SRP, @@ -4934,7 +4934,7 @@ putlog(0, "ploadr"); uint32 ea = cea_copro(); write_4(ea, GetSRPh()); write_4(ea + 4, GetSRPl()); - break; + return; } case (0x4c00 >> 8): case (0x4d00 >> 8): @@ -4945,13 +4945,14 @@ putlog(0, "ploadr"); uint32 ea = cea_copro(); uint32 h = read_4(ea); uint32 l = read_4(ea + 4); - if (SetCRP(h, l) == false) { + if (SetCRP(h, l)) { + if ((ir2 & 0x0100) == 0) { + atc.FlushAll(); + } + } else { Exception(M68K::EXCEP_MMU_CONFIG); - break; } - if ((ir2 & 0x0100) == 0) - atc.flush(); - break; + return; } case (0x4e00 >> 8): // %010_01110_000_00000 PMOVE.Q CRP, @@ -4960,7 +4961,7 @@ putlog(0, "ploadr"); uint32 ea = cea_copro(); write_4(ea, GetCRPh()); write_4(ea + 4, GetCRPl()); - break; + return; } case (0x6000 >> 8): // %011_00000_000_00000 PMOVE.W ,MMUSR @@ -4969,7 +4970,7 @@ putlog(0, "ploadr"); uint32 ea = cea_copro(); uint16 data = read_2(ea); SetMMUSR(data); - break; + return; } case (0x6200 >> 8): // %011_00010_000_00000 PMOVE.W MMUSR, @@ -4977,7 +4978,7 @@ putlog(0, "ploadr"); CYCLE3(pmove_mmusr_ea); uint32 ea = cea_copro(); write_2(ea, GetMMUSR()); - break; + return; } case (0x8000 >> 8): case (0x8400 >> 8): @@ -4992,8 +4993,8 @@ putlog(0, "ploadr"); // %100_nnn00_000_01yyy PTESTW Dy,,# // %100_nnn00_000_10nnn PTESTW #,,# { - mmu_op_ptest(); - break; + ops_mmu30_ptest(); + return; } case (0x8100 >> 8): case (0x8500 >> 8): @@ -5008,8 +5009,8 @@ putlog(0, "ploadr"); // %100_nnn01_nnn_01yyy PTESTW Dy,,#,An // %100_nnn01_nnn_10nnn PTESTW #,,#,An { - mmu_op_ptest(); - break; + ops_mmu30_ptest(); + return; } case (0x8200 >> 8): case (0x8600 >> 8): @@ -5024,8 +5025,8 @@ putlog(0, "ploadr"); // %100_nnn10_000_01yyy PTESTR Dy,,# // %100_nnn10_000_10nnn PTESTR #,,# { - mmu_op_ptest(); - break; + ops_mmu30_ptest(); + return; } case (0x8300 >> 8): case (0x8700 >> 8): @@ -5040,13 +5041,13 @@ putlog(0, "ploadr"); // %100_nnn11_nnn_01yyy PTESTR Dy,,#,An // %100_nnn11_nnn_10nnn PTESTR #,,#,An { - mmu_op_ptest(); - break; + ops_mmu30_ptest(); + return; } default: - OP_FUNC(illegal); break; } + OP_FUNC(illegal); } // 現在の FPCR/FPSR を fe 構造体にコピー。 @@ -5267,42 +5268,42 @@ MPU68040Device::ops_mmu40_pflush() { CYCLE(11); busaddr addr = busaddr(RegAY) | reg.dfc; - atc_inst->Flush(addr, false); - atc_data->Flush(addr, false); - break; + atc_inst->Flush(addr, true); + atc_data->Flush(addr, true); + return; } case 010 ... 017: // PFLUSH (Ay) { CYCLE(11); busaddr addr = busaddr(RegAY) | reg.dfc; - atc_inst->Flush(addr, true); - atc_data->Flush(addr, true); - break; + atc_inst->Flush(addr, false); + atc_data->Flush(addr, false); + return; } case 020: // PFLUSHAN { CYCLE(27); bool s = reg.dfc.IsSuper(); - atc_inst->Flush(s, false); - atc_data->Flush(s, false); - break; + atc_inst->Flush(s, true); + atc_data->Flush(s, true); + return; } case 030: // PFLUSHA { CYCLE3(pflusha); bool s = reg.dfc.IsSuper(); - atc_inst->Flush(s, true); - atc_data->Flush(s, true); - break; + atc_inst->Flush(s, false); + atc_data->Flush(s, false); + return; } default: - op_illegal(); - return; + break; } + op_illegal(); } // %1111_010101_mmmrrr ..m+.rxwp. 23- cpRESTORE