--- nono/m88xx0/m88100.h 2026/04/29 17:04:49 1.1.1.7 +++ nono/m88xx0/m88100.h 2026/04/29 17:05:05 1.1.1.11 @@ -71,6 +71,123 @@ struct m88100reg static const uint32 DM_D1 = DM_SIZE_W | DM_DOUB1; static const uint32 DM_D2 = DM_SIZE_W; + // FPECR(fcr0) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------+---------------+---------------+-+-+-+-+-+-+-+-+ + // | |I|U|P|O|D|U|O|I| + // | 0 |O|N|V|P|Z|F|V|N| + // +---------------+---------------+---------------+-+-+-+-+-+-+-+-+ + static const uint32 FPECR_MASK = 0x000000ff; // 有効ビットマスク + static const uint32 FPECR_FIOV = 0x00000080; // FP Integer Overflow + static const uint32 FPECR_FUNIMP= 0x00000040; // FP Unimplemented + static const uint32 FPECR_FPRV = 0x00000020; // FP Privilege Violation + static const uint32 FPECR_FROP = 0x00000010; // FP Reserved Operand + static const uint32 FPECR_FDVZ = 0x00000008; // FP Divice-by-Zero + static const uint32 FPECR_FUNF = 0x00000004; // FP Underflow + static const uint32 FPECR_FOVF = 0x00000002; // FP Overflow + static const uint32 FPECR_FINX = 0x00000001; // FP Inexact + + // FPHS1(fcr1) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +-+---------------------+---------------------------------------+ + // |S| Exponent | High order 20 bits of Mantissa | + // +-+---------------------+---------------------------------------+ + + // FPLS1(fcr2) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------------------------------------------------------+ + // | Low order bits of Mantissa or Integer Operand | + // +---------------------------------------------------------------+ + + // FPHS2(fcr3) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +-+---------------------+---------------------------------------+ + // |S| Exponent | High order 20 bits of Mantissa | + // +-+---------------------+---------------------------------------+ + + // FPLS2(fcr4) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------------------------------------------------------+ + // | Low order bits of Mantissa or Integer Operand | + // +---------------------------------------------------------------+ + + // FPPT(fcr5) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------+---------------+---------+---+---+---+---------+ + // | 0 | OPCODE |T1 |T2 |TD | DestReg | + // +---------------+---------------+---------+---+---+---+---------+ + static const uint32 FPPT_MASK = 0x0000ffff; // 有効ビットマスク + static const uint32 FPPT_OPCODE = 0x0000f800; // Opcode + static const uint32 FPPT_T1 = 0x00000600; // Source1 Operand Size + static const uint32 FPPT_T2 = 0x00000180; // Source2 Operand Size + static const uint32 FPPT_TD = 0x00000060; // Destination Size + static const uint32 FPPT_DEST = 0x0000001f; // Destination Register No. + + // FPRH(fcr6) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +-----+-+-+-+-+-+-----+---------+-------------+-----------------+ + // |S|RM |G|R|S|A| 0 | High Order Bits of Mantissa | + // +-----+-+-+-+-+-+-----+---------+-------------+-----------------+ + static const uint32 FPRH_MASK = 0xfe1fffff; // 有効ビットマスク + static const uint32 FPRH_SIGN = 0x80000000; // Result Sign + static const uint32 FPRH_RNDMODE= 0x60000000; // Rounding Mode for Res. + static const uint32 FPRH_GUARD = 0x10000000; // Guard Bit for Result + static const uint32 FPRH_ROUND = 0x08000000; // Round Bit for Result + static const uint32 FPRH_STICKY = 0x04000000; // Sticky Bit for Result + static const uint32 FPRH_ADDONE = 0x02000000; // Add One + static const uint32 FPRH_MANT = 0x001fffff; // Mantissa(High) + static const uint32 FPRH_1 = 0x00100000; // 隠し実数部の 1 + + // FPRL(fcr7) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------------------------------------------------------+ + // | Low Order Bits of Mantissa | + // +---------------------------------------------------------------+ + + // FPIT(fcr8) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +-----------------------+-------+---------+-+-+-+-+-+-+---------+ + // | | | |D|E|E|E|E|E| | + // | RESEXP (12bits) | 0 | OPCODE |S|V|Z|U|O|N| DestReg | + // +-----------------------+-------+---------+-+-+-+-+-+-+---------+ + static const uint32 FPIT_MASK = 0xfff0ffff; // 有効ビットマスク + static const uint32 FPIT_RESEXP = 0xfff00000; // Result Exponent + static const uint32 FPIT_OPCODE = 0x0000f800; // Opcode + static const uint32 FPIT_DESTSIZ= 0x00000400; // Destination Size + static const uint32 FPIT_EFINV = 0x00000200; // Enable Invalid Op. + static const uint32 FPIT_EFDVZ = 0x00000100; // Enable Divide-by-Zero + static const uint32 FPIT_EFUNF = 0x00000080; // Enable Underflow + static const uint32 FPIT_EFOVF = 0x00000040; // Enable Overflow + static const uint32 FPIT_EFINX = 0x00000020; // Enable Inexact + static const uint32 FPIT_DEST = 0x0000001f; // Destination Register No. + + // FPSR(fcr62) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------+---------------+---------------+-----+-+-+-+-+-+ + // | |A|A|A|A|A| + // | 0 |V|D|U|O|I| + // +---------------+---------------+---------------+-----+-+-+-+-+-+ + static const uint32 FPSR_MASK = 0x0000001f; // 有効ビットマスク + static const uint32 FPSR_AFINV = 0x00000010; // Acc. Invalid Op. Flag + static const uint32 FPSR_AFDVZ = 0x00000008; // Acc. Divide-by-Zero Flag + static const uint32 FPSR_AFUNF = 0x00000004; // Acc. Underflow Flag + static const uint32 FPSR_AFOVF = 0x00000002; // Acc. Overflow Flag + static const uint32 FPSR_AFINX = 0x00000001; // Acc. Inexact Flag + + // FPCR(fcr63) + // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + // +---------------+---------------+---+-----------+-----+-+-+-+-+-+ + // | | | |E|E|E|E|E| + // | 0 |RM | |V|D|U|O|I| + // +---------------+---------------+---+-----------+-----+-+-+-+-+-+ + static const uint32 FPCR_MASK = 0x0000c01f; // 有効ビットマスク + static const uint32 FPCR_RM = 0x0000c000; // Rounding Mask + static const uint32 FPCR_EFINV = 0x00000010; // Enable Invalid Operation + static const uint32 FPCR_EFDVZ = 0x00000008; // Enable Divide-by-Zero + static const uint32 FPCR_EFUNF = 0x00000004; // Enable Underflow + static const uint32 FPCR_EFOVF = 0x00000002; // Enable Overflow + static const uint32 FPCR_EFINX = 0x00000001; // Enable Inexact + // 頻繁にアクセスしそうな変数はオフセットの若いほうに持ってきておく。 // 実行中の命令 @@ -149,6 +266,7 @@ struct m88100reg psr |= ((cy & 1) << 28); } + static const uint32 fcr_mask[11]; static const char * const sipname[3]; static const char * const dmt_en_str[16]; }; @@ -167,12 +285,14 @@ class m88kcpu : public m88100reg }; public: - m88kcpu(uint32 reset_vector_); + m88kcpu(); virtual ~m88kcpu(); + void PowerOn(); + void RequestReset(); + uint32 Run(uint32 delta); void Release(); - void RequestReset(); // 仮想時刻を返す uint64 GetVTime() const { return total_vtime + Cycle2Vtime(used_cycle); } @@ -219,9 +339,9 @@ class m88kcpu : public m88100reg m88200 cmmu[2] {}; // ブランチ履歴 (例外履歴を含む) - BranchHistory_m88xx0 brhist {}; + BranchHistory_m88xx0 brhist { BranchHistory::BrHist }; // 例外履歴のみ - BranchHistory_m88xx0 exhist {}; + BranchHistory_m88xx0 exhist { BranchHistory::ExHistOnly }; // 32bit 命令コードからディスパッチ用の 12bit に変換。 static uint32 op32_to_12(uint32 op) { @@ -231,6 +351,12 @@ class m88kcpu : public m88100reg // 例外名を返す static const char *GetExceptionName(int vector); + // 疑似 STOP 状態に入る機能を有効にする場合 true + bool pseudo_stop_enable {}; + + // DOS call エミュレーションコールバックを設定する + void SetFLineCallback(bool (*callback)(m88kcpu *, void *), void *arg); + private: void Reset(); @@ -261,6 +387,15 @@ class m88kcpu : public m88100reg } } + // FPxS1, FPxS2 レジスタを設定 + void SetFPxS(uint32& h, uint32& l, double src, uint32 t); + void SetFPS1(double src, uint32 t1) { SetFPxS(fphs1, fpls1, src, t1); } + void SetFPS2(double src, uint32 t2) { SetFPxS(fphs2, fpls2, src, t2); } + void SetFPS1(uint32 src) { fpls1 = src; } + void SetFPS2(uint32 src) { fpls2 = src; } + // FP Result を FPIT, FPRH, FPRL レジスタに設定 + void SetFPRx(double src); + void Exception(int vec); void ExceptionCore(int vec, ExceptionKind cause); uint32 Calcdmt(uint32 flag); @@ -269,7 +404,10 @@ class m88kcpu : public m88100reg void WriteDataException32(uint32 addr, uint32 flag); void WriteDataException64(uint32 addr, uint32 flag); void XmemDataException(uint32 addr, uint32 flag); - void FPException(int fpex); + void FPPreciseException(uint32 cause, double s2); + void FPPreciseException(uint32 cause, double s1, double s2); + void FPPreciseException(uint32 cause); + void FPImpreciseException(uint32 cause); // ブランチ処理用 void EnterBranch(uint32 toaddr); @@ -281,6 +419,8 @@ class m88kcpu : public m88100reg bool ldst_usr(uint32& usr); uint32 ldst_scale(uint32 size); bool ldst_align(uint32 size, uint32& addr); + // 浮動小数点数命令用の処理 + void ops_int(int mode); #define OP_PROTO(name) void __CONCAT(op_,name)() #include "m88100ops.h" @@ -317,8 +457,31 @@ OP_PROTO(illegal); // ペンディング中の割り込みレベル int intr_pending {}; - // リセットベクタ - uint32 reset_vector {}; + // float,double と整数値の相互変換 + static float u2f(uint32 u) { + float v; + memcpy(&v, &u, sizeof(v)); + return v; + } + static double u2d(uint64 u) { + double v; + memcpy(&v, &u, sizeof(v)); + return v; + } + static uint32 f2u(float v) { + uint32 u; + memcpy(&u, &v, sizeof(u)); + return u; + } + static uint64 d2u(double v) { + uint64 u; + memcpy(&u, &v, sizeof(u)); + return u; + } + + // DOS call エミュレーション + bool (*fline_callback)(m88kcpu *, void *) = NULL; + void *fline_arg {}; // 例外名 static const char * const exception_names[];