--- nono/vm/bus.cpp	2026/04/29 17:04:28	1.1.1.1
+++ nono/vm/bus.cpp	2026/04/29 17:04:52	1.1.1.6
@@ -1,6 +1,7 @@
 //
 // nono
-// Copyright (C) 2017 isaki@NetBSD.org
+// Copyright (C) 2020 nono project
+// Licensed under nono-license.txt
 //
 
 #include "bus.h"
@@ -8,18 +9,24 @@
 
 IODevice *devtable[256];
 
+// RAM へのアクセスは、アクセスアドレスが direct_ram_size 未満なら ram[] を
+// 直接アクセスし、そうでなければデバイスクラス経由でアクセスする。
+// 高速モードでは RAM デバイスを経由すること自体とその中でアクセスウェイトを
+// 計算する分を回避したい。
+int direct_ram_size;
+
 //
 // 物理バスアクセス?
 // addr はそれぞれアラインされていること
 //
 
 uint64
-m68030_phys_read_8(uint32 addr)
+vm_phys_read_8(uint32 addr)
 {
 	uint64 data;
 
-	if (addr < ram_size) {
-		data = ram[HLB(addr)];
+	if (addr < direct_ram_size) {
+		data = mainram[HLB(addr)];
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
 		data = dev->Read8(addr);
@@ -28,13 +35,15 @@ m68030_phys_read_8(uint32 addr)
 }
 
 uint64
-m68030_phys_read_16(uint32 addr)
+vm_phys_read_16(uint32 addr)
 {
 	uint64 data;
 
-if ((addr & 1))PANIC("unaligned access $%08x", addr);
-	if (addr < ram_size) {
-		data = *(uint16 *)&ram[HLW(addr)];
+	if (__predict_false(addr & 1))
+		PANIC("unaligned access $%08x", addr);
+
+	if (addr < direct_ram_size) {
+		data = *(uint16 *)&mainram[HLW(addr)];
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
 		data = dev->Read16(addr);
@@ -43,14 +52,15 @@ if ((addr & 1))PANIC("unaligned access $
 }
 
 uint64
-m68030_phys_read_32(uint32 addr)
+vm_phys_read_32(uint32 addr)
 {
 	uint64 data;
 
-if ((addr & 3))PANIC("unaligned access $%08x", addr);
+	if (__predict_false(addr & 3))
+		PANIC("unaligned access $%08x", addr);
 
-	if (addr < ram_size) {
-		data = *(uint32 *)&ram[addr];
+	if (addr < direct_ram_size) {
+		data = *(uint32 *)&mainram[addr];
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
 		data = dev->Read32(addr);
@@ -59,10 +69,10 @@ if ((addr & 3))PANIC("unaligned access $
 }
 
 uint64
-m68030_phys_write_8(uint32 addr, uint32 data)
+vm_phys_write_8(uint32 addr, uint32 data)
 {
-	if (addr < ram_size) {
-		ram[HLB(addr)] = data;
+	if (addr < direct_ram_size) {
+		mainram[HLB(addr)] = data;
 		return 0;
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
@@ -71,11 +81,13 @@ m68030_phys_write_8(uint32 addr, uint32
 }
 
 uint64
-m68030_phys_write_16(uint32 addr, uint32 data)
+vm_phys_write_16(uint32 addr, uint32 data)
 {
-if ((addr & 1))PANIC("unaligned access $%08x", addr);
-	if (addr < ram_size) {
-		*(uint16 *)&ram[HLW(addr)] = data;
+	if (__predict_false(addr & 1))
+		PANIC("unaligned access $%08x", addr);
+
+	if (addr < direct_ram_size) {
+		*(uint16 *)&mainram[HLW(addr)] = data;
 		return 0;
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
@@ -84,11 +96,13 @@ if ((addr & 1))PANIC("unaligned access $
 }
 
 uint64
-m68030_phys_write_32(uint32 addr, uint32 data)
+vm_phys_write_32(uint32 addr, uint32 data)
 {
-if ((addr & 3))PANIC("unaligned access $%08x", addr);
-	if (addr < ram_size) {
-		*(uint32 *)&ram[addr] = data;
+	if (__predict_false(addr & 3))
+		PANIC("unaligned access $%08x", addr);
+
+	if (addr < direct_ram_size) {
+		*(uint32 *)&mainram[addr] = data;
 		return 0;
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
@@ -97,12 +111,12 @@ if ((addr & 3))PANIC("unaligned access $
 }
 
 uint64
-m68030_phys_peek_8(uint32 addr)
+vm_phys_peek_8(uint32 addr)
 {
 	uint64 data;
 
-	if (addr < ram_size) {
-		data = ram[HLB(addr)];
+	if (addr < direct_ram_size) {
+		data = mainram[HLB(addr)];
 	} else {
 		IODevice *dev = ::devtable[addr >> 24];
 		data = dev->Peek8(addr);