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Annotation of nono/vm/bus.cpp, revision 1.1.1.6

1.1       root        1: //
                      2: // nono
1.1.1.3   root        3: // Copyright (C) 2020 nono project
                      4: // Licensed under nono-license.txt
1.1       root        5: //
                      6: 
                      7: #include "bus.h"
                      8: #include "ram.h"
                      9: 
                     10: IODevice *devtable[256];
                     11: 
1.1.1.5   root       12: // RAM へのアクセスは、アクセスアドレスが direct_ram_size 未満なら ram[] を
                     13: // 直接アクセスし、そうでなければデバイスクラス経由でアクセスする。
                     14: // 高速モードでは RAM デバイスを経由すること自体とその中でアクセスウェイトを
                     15: // 計算する分を回避したい。
                     16: int direct_ram_size;
                     17: 
1.1       root       18: //
                     19: // 物理バスアクセス?
                     20: // addr はそれぞれアラインされていること
                     21: //
                     22: 
                     23: uint64
1.1.1.2   root       24: vm_phys_read_8(uint32 addr)
1.1       root       25: {
                     26:        uint64 data;
                     27: 
1.1.1.5   root       28:        if (addr < direct_ram_size) {
1.1.1.6 ! root       29:                data = mainram[HLB(addr)];
1.1       root       30:        } else {
                     31:                IODevice *dev = ::devtable[addr >> 24];
                     32:                data = dev->Read8(addr);
                     33:        }
                     34:        return data;
                     35: }
                     36: 
                     37: uint64
1.1.1.2   root       38: vm_phys_read_16(uint32 addr)
1.1       root       39: {
                     40:        uint64 data;
                     41: 
1.1.1.4   root       42:        if (__predict_false(addr & 1))
                     43:                PANIC("unaligned access $%08x", addr);
                     44: 
1.1.1.5   root       45:        if (addr < direct_ram_size) {
1.1.1.6 ! root       46:                data = *(uint16 *)&mainram[HLW(addr)];
1.1       root       47:        } else {
                     48:                IODevice *dev = ::devtable[addr >> 24];
                     49:                data = dev->Read16(addr);
                     50:        }
                     51:        return data;
                     52: }
                     53: 
                     54: uint64
1.1.1.2   root       55: vm_phys_read_32(uint32 addr)
1.1       root       56: {
                     57:        uint64 data;
                     58: 
1.1.1.4   root       59:        if (__predict_false(addr & 3))
                     60:                PANIC("unaligned access $%08x", addr);
1.1       root       61: 
1.1.1.5   root       62:        if (addr < direct_ram_size) {
1.1.1.6 ! root       63:                data = *(uint32 *)&mainram[addr];
1.1       root       64:        } else {
                     65:                IODevice *dev = ::devtable[addr >> 24];
                     66:                data = dev->Read32(addr);
                     67:        }
                     68:        return data;
                     69: }
                     70: 
                     71: uint64
1.1.1.2   root       72: vm_phys_write_8(uint32 addr, uint32 data)
1.1       root       73: {
1.1.1.5   root       74:        if (addr < direct_ram_size) {
1.1.1.6 ! root       75:                mainram[HLB(addr)] = data;
1.1       root       76:                return 0;
                     77:        } else {
                     78:                IODevice *dev = ::devtable[addr >> 24];
                     79:                return dev->Write8(addr, data);
                     80:        }
                     81: }
                     82: 
                     83: uint64
1.1.1.2   root       84: vm_phys_write_16(uint32 addr, uint32 data)
1.1       root       85: {
1.1.1.4   root       86:        if (__predict_false(addr & 1))
                     87:                PANIC("unaligned access $%08x", addr);
                     88: 
1.1.1.5   root       89:        if (addr < direct_ram_size) {
1.1.1.6 ! root       90:                *(uint16 *)&mainram[HLW(addr)] = data;
1.1       root       91:                return 0;
                     92:        } else {
                     93:                IODevice *dev = ::devtable[addr >> 24];
                     94:                return dev->Write16(addr, data);
                     95:        }
                     96: }
                     97: 
                     98: uint64
1.1.1.2   root       99: vm_phys_write_32(uint32 addr, uint32 data)
1.1       root      100: {
1.1.1.4   root      101:        if (__predict_false(addr & 3))
                    102:                PANIC("unaligned access $%08x", addr);
                    103: 
1.1.1.5   root      104:        if (addr < direct_ram_size) {
1.1.1.6 ! root      105:                *(uint32 *)&mainram[addr] = data;
1.1       root      106:                return 0;
                    107:        } else {
                    108:                IODevice *dev = ::devtable[addr >> 24];
                    109:                return dev->Write32(addr, data);
                    110:        }
                    111: }
                    112: 
                    113: uint64
1.1.1.2   root      114: vm_phys_peek_8(uint32 addr)
1.1       root      115: {
                    116:        uint64 data;
                    117: 
1.1.1.5   root      118:        if (addr < direct_ram_size) {
1.1.1.6 ! root      119:                data = mainram[HLB(addr)];
1.1       root      120:        } else {
                    121:                IODevice *dev = ::devtable[addr >> 24];
                    122:                data = dev->Peek8(addr);
                    123:        }
                    124:        return data;
                    125: }

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