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1.1 root 1: //
2: // nono
1.1.1.3 root 3: // Copyright (C) 2020 nono project
4: // Licensed under nono-license.txt
1.1 root 5: //
6:
1.1.1.8 ! root 7: //
! 8: // 物理バスアクセス?
! 9: //
! 10:
! 11: // addr はそれぞれアラインされていること
! 12:
1.1 root 13: #include "bus.h"
14: #include "ram.h"
15:
16: IODevice *devtable[256];
17:
1.1.1.5 root 18: // RAM へのアクセスは、アクセスアドレスが direct_ram_size 未満なら ram[] を
19: // 直接アクセスし、そうでなければデバイスクラス経由でアクセスする。
20: // 高速モードでは RAM デバイスを経由すること自体とその中でアクセスウェイトを
21: // 計算する分を回避したい。
22: int direct_ram_size;
23:
1.1 root 24: uint64
1.1.1.2 root 25: vm_phys_read_8(uint32 addr)
1.1 root 26: {
27: uint64 data;
28:
1.1.1.5 root 29: if (addr < direct_ram_size) {
1.1.1.6 root 30: data = mainram[HLB(addr)];
1.1 root 31: } else {
32: IODevice *dev = ::devtable[addr >> 24];
33: data = dev->Read8(addr);
34: }
35: return data;
36: }
37:
38: uint64
1.1.1.2 root 39: vm_phys_read_16(uint32 addr)
1.1 root 40: {
41: uint64 data;
42:
1.1.1.7 root 43: if (__predict_false((addr & 1) != 0))
1.1.1.8 ! root 44: VMPANIC("unaligned access $%08x", addr);
1.1.1.4 root 45:
1.1.1.5 root 46: if (addr < direct_ram_size) {
1.1.1.6 root 47: data = *(uint16 *)&mainram[HLW(addr)];
1.1 root 48: } else {
49: IODevice *dev = ::devtable[addr >> 24];
50: data = dev->Read16(addr);
51: }
52: return data;
53: }
54:
55: uint64
1.1.1.2 root 56: vm_phys_read_32(uint32 addr)
1.1 root 57: {
58: uint64 data;
59:
1.1.1.7 root 60: if (__predict_false((addr & 3) != 0))
1.1.1.8 ! root 61: VMPANIC("unaligned access $%08x", addr);
1.1 root 62:
1.1.1.5 root 63: if (addr < direct_ram_size) {
1.1.1.6 root 64: data = *(uint32 *)&mainram[addr];
1.1 root 65: } else {
66: IODevice *dev = ::devtable[addr >> 24];
67: data = dev->Read32(addr);
68: }
69: return data;
70: }
71:
72: uint64
1.1.1.2 root 73: vm_phys_write_8(uint32 addr, uint32 data)
1.1 root 74: {
1.1.1.5 root 75: if (addr < direct_ram_size) {
1.1.1.6 root 76: mainram[HLB(addr)] = data;
1.1 root 77: return 0;
78: } else {
79: IODevice *dev = ::devtable[addr >> 24];
80: return dev->Write8(addr, data);
81: }
82: }
83:
84: uint64
1.1.1.2 root 85: vm_phys_write_16(uint32 addr, uint32 data)
1.1 root 86: {
1.1.1.7 root 87: if (__predict_false((addr & 1) != 0))
1.1.1.8 ! root 88: VMPANIC("unaligned access $%08x", addr);
1.1.1.4 root 89:
1.1.1.5 root 90: if (addr < direct_ram_size) {
1.1.1.6 root 91: *(uint16 *)&mainram[HLW(addr)] = data;
1.1 root 92: return 0;
93: } else {
94: IODevice *dev = ::devtable[addr >> 24];
95: return dev->Write16(addr, data);
96: }
97: }
98:
99: uint64
1.1.1.2 root 100: vm_phys_write_32(uint32 addr, uint32 data)
1.1 root 101: {
1.1.1.7 root 102: if (__predict_false((addr & 3) != 0))
1.1.1.8 ! root 103: VMPANIC("unaligned access $%08x", addr);
1.1.1.4 root 104:
1.1.1.5 root 105: if (addr < direct_ram_size) {
1.1.1.6 root 106: *(uint32 *)&mainram[addr] = data;
1.1 root 107: return 0;
108: } else {
109: IODevice *dev = ::devtable[addr >> 24];
110: return dev->Write32(addr, data);
111: }
112: }
113:
114: uint64
1.1.1.2 root 115: vm_phys_peek_8(uint32 addr)
1.1 root 116: {
117: uint64 data;
118:
1.1.1.5 root 119: if (addr < direct_ram_size) {
1.1.1.6 root 120: data = mainram[HLB(addr)];
1.1 root 121: } else {
122: IODevice *dev = ::devtable[addr >> 24];
123: data = dev->Peek8(addr);
124: }
125: return data;
126: }
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