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1.1 root 1: //
2: // nono
3: // Copyright (C) 2017 [email protected]
4: //
5:
6: #include "dmac.h"
7:
8: DMACDevice::DMACDevice()
9: {
10: logname = "dmac";
11: devname = "DMAC";
12: devaddr = baseaddr;
13: devlen = 0x2000;
14: }
15:
16: DMACDevice::~DMACDevice()
17: {
18: }
19:
20: uint64
21: DMACDevice::Read8(uint32 addr)
22: {
23: uint8 data;
24: int ch;
25:
26: ch = (addr - baseaddr) / 0x40;
27: struct DMAC::channel *chan = &dmac.chan[ch];
28: int n = (addr - baseaddr) % 0x40;
29: switch (n) {
30: case DMAC::CSR:
31: data = chan->csr;
32: break;
33:
34: case DMAC::CER:
35: data = chan->cer;
36: break;
37:
38: case DMAC::DCR:
39: data = chan->dcr;
40: break;
41:
42: case DMAC::OCR:
43: data = chan->ocr;
44: break;
45:
46: case DMAC::SCR:
47: data = chan->scr;
48: break;
49:
50: case DMAC::CCR:
51: data = chan->ccr;
52: break;
53:
54: case DMAC::MTC:
55: data = chan->mtc >> 8;
56: break;
57: case DMAC::MTC + 1:
58: data = chan->mtc & 0xff;
59: break;
60:
61: case DMAC::MAR:
62: data = chan->mar >> 24;
63: break;
64: case DMAC::MAR + 1:
65: data = (chan->mar >> 16) & 0xff;
66: break;
67: case DMAC::MAR + 2:
68: data = (chan->mar >> 8) & 0xff;
69: break;
70: case DMAC::MAR + 3:
71: data = chan->mar & 0xff;
72: break;
73:
74: case DMAC::DAR:
75: data = chan->dar >> 24;
76: break;
77: case DMAC::DAR + 1:
78: data = (chan->dar >> 16) & 0xff;
79: break;
80: case DMAC::DAR + 2:
81: data = (chan->dar >> 8) & 0xff;
82: break;
83: case DMAC::DAR + 3:
84: data = chan->dar & 0xff;
85: break;
86:
87: case DMAC::BTC:
88: data = chan->btc >> 8;
89: break;
90: case DMAC::BTC + 1:
91: data = chan->btc & 0xff;
92: break;
93:
94: case DMAC::BAR:
95: data = chan->bar >> 24;
96: break;
97: case DMAC::BAR + 1:
98: data = (chan->bar >> 16) & 0xff;
99: break;
100: case DMAC::BAR + 2:
101: data = (chan->bar >> 8) & 0xff;
102: break;
103: case DMAC::BAR + 3:
104: data = chan->bar & 0xff;
105: break;
106:
107: case DMAC::NIV:
108: data = chan->niv;
109: break;
110:
111: case DMAC::EIV:
112: data = chan->eiv;
113: break;
114:
115: case DMAC::MFC:
116: data = chan->mfc;
117: break;
118:
119: case DMAC::CPR:
120: data = chan->cpr;
121: break;
122:
123: case DMAC::DFC:
124: data = chan->dfc;
125: break;
126:
127: case DMAC::BFC:
128: data = chan->bfc;
129: break;
130:
131: case DMAC::GCR:
132: if (ch == 3) {
133: data = dmac.gcr;
134: break;
135: } else {
136: data = 0xff;
137: }
138: break;
139:
140: default:
141: data = 0xff;
142: break;
143: }
144:
145: return data;
146: }
147:
148: uint64
149: DMACDevice::Write8(uint32 addr, uint32 data)
150: {
151: int ch;
152:
153: ch = (addr - baseaddr) / 0x40;
154: struct DMAC::channel *chan = &dmac.chan[ch];
155: int n = (addr - baseaddr) % 0x40;
156: switch (n) {
157: case DMAC::CSR:
158: write_csr(ch, data);
159: break;
160:
161: case DMAC::CER:
162: // Read only
163: break;
164:
165: case DMAC::DCR:
166: chan->dcr = data & 0xfb;
167: break;
168:
169: case DMAC::OCR:
170: chan->ocr = data;
171: break;
172:
173: case DMAC::SCR:
174: chan->scr = data & 0x0f;
175: break;
176:
177: case DMAC::CCR:
178: write_ccr(ch, data);
179: break;
180:
181: case DMAC::MTC:
182: chan->mtc = (chan->mtc & 0x00ff) | (data << 8);
183: break;
184: case DMAC::MTC + 1:
185: chan->mtc = (chan->mtc & 0xff00) | data;
186: break;
187:
188: case DMAC::MAR:
189: chan->mar = (chan->mar & 0x00ffffff) | (data << 24);
190: break;
191: case DMAC::MAR + 1:
192: chan->mar = (chan->mar & 0xff00ffff) | (data << 16);
193: break;
194: case DMAC::MAR + 2:
195: chan->mar = (chan->mar & 0xffff00ff) | (data << 8);
196: break;
197: case DMAC::MAR + 3:
198: chan->mar = (chan->mar & 0xffffff00) | data;
199: break;
200:
201: case DMAC::DAR:
202: chan->dar = (chan->dar & 0x00ffffff) | (data << 24);
203: break;
204: case DMAC::DAR + 1:
205: chan->dar = (chan->dar & 0xff00ffff) | (data << 16);
206: break;
207: case DMAC::DAR + 2:
208: chan->dar = (chan->dar & 0xffff00ff) | (data << 8);
209: break;
210: case DMAC::DAR + 3:
211: chan->dar = (chan->dar & 0xffffff00) | data;
212: break;
213:
214: case DMAC::BTC:
215: chan->btc = (chan->btc & 0x00ff) | (data << 8);
216: break;
217: case DMAC::BTC + 1:
218: chan->btc = (chan->btc & 0xff00) | data;
219: break;
220:
221: case DMAC::BAR:
222: chan->bar = (chan->bar & 0x00ffffff) | (data << 24);
223: break;
224: case DMAC::BAR + 1:
225: chan->bar = (chan->bar & 0xff00ffff) | (data << 16);
226: break;
227: case DMAC::BAR + 2:
228: chan->bar = (chan->bar & 0xffff00ff) | (data << 8);
229: break;
230: case DMAC::BAR + 3:
231: chan->bar = (chan->bar & 0xffffff00) | data;
232: break;
233:
234: case DMAC::NIV:
235: chan->niv = data;
236: break;
237:
238: case DMAC::EIV:
239: chan->eiv = data;
240: break;
241:
242: case DMAC::MFC:
243: chan->mfc = data & 7;
244: break;
245:
246: case DMAC::CPR:
247: chan->cpr = data & 3;
248: break;
249:
250: case DMAC::DFC:
251: chan->dfc = data & 7;
252: break;
253:
254: case DMAC::BFC:
255: chan->bfc = data & 7;
256: break;
257:
258: case DMAC::GCR:
259: if (ch == 3) {
260: dmac.gcr = data;
261: }
262: break;
263:
264: default:
265: break;
266: }
267: return 0;
268: }
269:
270: uint64
271: DMACDevice::Peek8(uint32 addr)
272: {
273: uint8 data;
274: int ch;
275:
276: ch = (addr - baseaddr) / 0x40;
277: struct DMAC::channel *chan = &dmac.chan[ch];
278: int n = (addr - baseaddr) % 0x40;
279: switch (n) {
280: case DMAC::CSR:
281: data = chan->csr;
282: break;
283:
284: case DMAC::CER:
285: data = chan->cer;
286: break;
287:
288: case DMAC::DCR:
289: data = chan->dcr;
290: break;
291:
292: case DMAC::OCR:
293: data = chan->ocr;
294: break;
295:
296: case DMAC::SCR:
297: data = chan->scr;
298: break;
299:
300: case DMAC::CCR:
301: data = chan->ccr;
302: break;
303:
304: case DMAC::MTC:
305: data = chan->mtc >> 8;
306: break;
307: case DMAC::MTC + 1:
308: data = chan->mtc & 0xff;
309: break;
310:
311: case DMAC::MAR:
312: data = chan->mar >> 24;
313: break;
314: case DMAC::MAR + 1:
315: data = (chan->mar >> 16) & 0xff;
316: break;
317: case DMAC::MAR + 2:
318: data = (chan->mar >> 8) & 0xff;
319: break;
320: case DMAC::MAR + 3:
321: data = chan->mar & 0xff;
322: break;
323:
324: case DMAC::DAR:
325: data = chan->dar >> 24;
326: break;
327: case DMAC::DAR + 1:
328: data = (chan->dar >> 16) & 0xff;
329: break;
330: case DMAC::DAR + 2:
331: data = (chan->dar >> 8) & 0xff;
332: break;
333: case DMAC::DAR + 3:
334: data = chan->dar & 0xff;
335: break;
336:
337: case DMAC::BTC:
338: data = chan->btc >> 8;
339: break;
340: case DMAC::BTC + 1:
341: data = chan->btc & 0xff;
342: break;
343:
344: case DMAC::BAR:
345: data = chan->bar >> 24;
346: break;
347: case DMAC::BAR + 1:
348: data = (chan->bar >> 16) & 0xff;
349: break;
350: case DMAC::BAR + 2:
351: data = (chan->bar >> 8) & 0xff;
352: break;
353: case DMAC::BAR + 3:
354: data = chan->bar & 0xff;
355: break;
356:
357: case DMAC::NIV:
358: data = chan->niv;
359: break;
360:
361: case DMAC::EIV:
362: data = chan->eiv;
363: break;
364:
365: case DMAC::MFC:
366: data = chan->mfc;
367: break;
368:
369: case DMAC::CPR:
370: data = chan->cpr;
371: break;
372:
373: case DMAC::DFC:
374: data = chan->dfc;
375: break;
376:
377: case DMAC::BFC:
378: data = chan->bfc;
379: break;
380:
381: case DMAC::GCR:
382: if (ch == 3) {
383: data = dmac.gcr;
384: break;
385: } else {
386: data = 0xff;
387: }
388: break;
389:
390: default:
391: data = 0xff;
392: break;
393: }
394:
395: return data;
396: }
397:
398: void
399: DMACDevice::write_csr(int ch, uint32 data)
400: {
401: putlog(1, "write_csr[%d] <- $%02x 未実装書き込み", ch, data);
402: }
403:
404: void
405: DMACDevice::write_ccr(int ch, uint32 data)
406: {
407: putlog(1, "write_ccr[%d] <- $%02x 未実装書き込み", ch, data);
408: }
409:
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