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1.1 root 1: //
2: // nono
1.1.1.3 ! root 3: // Copyright (C) 2020 nono project
! 4: // Licensed under nono-license.txt
1.1 root 5: //
6:
7: #pragma once
8:
9: #include "device.h"
1.1.1.2 root 10: #include "scheduler.h"
1.1 root 11:
12: struct DMAC
13: {
1.1.1.2 root 14: static const uint32 CSR = 0x00; // .B
15: static const uint32 CER = 0x01; // .B
16: static const uint32 DCR = 0x04; // .B
17: static const uint32 OCR = 0x05; // .B
18: static const uint32 SCR = 0x06; // .B
19: static const uint32 CCR = 0x07; // .B
20: static const uint32 MTC = 0x0a; // .W
21: static const uint32 MAR = 0x0c; // .L
22: static const uint32 DAR = 0x14; // .L
23: static const uint32 BTC = 0x1a; // .W
24: static const uint32 BAR = 0x1c; // .L
25: static const uint32 NIV = 0x25; // .B
26: static const uint32 EIV = 0x27; // .B
27: static const uint32 MFC = 0x29; // .B
28: static const uint32 CPR = 0x2d; // .B
29: static const uint32 DFC = 0x31; // .B
30: static const uint32 BFC = 0x39; // .B
31: static const uint32 GCR = 0x3f; // .B (ch#3のみ)
32:
33: // | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
34: // CSR | COC | BTC | NDT | ERR | ACT | --- | PCT | PCS |
35: //
36: static const uint32 CSR_COC = 0x80; // Channel Operation Complete
37: static const uint32 CSR_BTC = 0x40; // Block Transfer Complete
38: static const uint32 CSR_NDT = 0x20; // Normal Device Termination
39: static const uint32 CSR_ERR = 0x10; // Error Bit
40: static const uint32 CSR_ACT = 0x08; // Channel Active
41: static const uint32 CSR_PCT = 0x02; // PCL Transition
42: static const uint32 CSR_PCS = 0x01; // PCL Input Line State
43:
44: // CER
45: static const uint32 CER_NO_ERROR = 0x00; // No Error
46: static const uint32 CER_CONFIG = 0x01; // Configuration Error
47: static const uint32 CER_OPER_TIMING = 0x02; // Operation Timing Error
48: static const uint32 CER_ADDR_MAR = 0x05; // Address error in MAR
49: static const uint32 CER_ADDR_DAR = 0x06; // Address error in DAR
50: static const uint32 CER_ADDR_BAR = 0x07; // Address error in BAR
51: static const uint32 CER_BUS_MAR = 0x09; // Bus error in MAR
52: static const uint32 CER_BUS_DAR = 0x0a; // Bus error in DAR
53: static const uint32 CER_BUS_BAR = 0x0b; // Bus error in BAR
54: static const uint32 CER_COUNT_MTC = 0x0d; // Count error in MTC
55: static const uint32 CER_COUNT_BTC = 0x0f; // Count error in BTC
56: static const uint32 CER_EXT_ABORT = 0x10; // External Abort
57: static const uint32 CER_SOFT_ABORT = 0x11; // Software Abort
58:
59: // | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
60: // DCR | XRM | DTYP | DPS | --- | PCL |
61: static const uint32 DCR_XRM_BURST = 0; // Burst Transfer
62: static const uint32 DCR_XRM_CYCLE_WO_HOLD = 2; // Cycle Steal without Hold
63: static const uint32 DCR_XRM_CYCLE_WITH_HOLD = 3;// Cycle Steal with Hold
64: static const uint32 DCR_DTYP_68000 = 0; // 68000 devices
65: static const uint32 DCR_DTYP_6800 = 1; // 6800 devices
66: static const uint32 DCR_DTYP_ACK = 2; // Devices with ACK
67: static const uint32 DCR_DTYP_ACK_REDY = 3; // Devices with ACK+READY
68: static const uint32 DCR_DPS_8BIT = 0; // 8bit port
69: static const uint32 DCR_DPS_16BIT = 1; // 16bit port
70: static const uint32 DCR_PCL_STATUS = 0; // Status Input
71: static const uint32 DCR_PCL_STATUS_INTR = 1; // Status Input with Interrupt
72: static const uint32 DCR_PCL_PULSE = 2; // Start Pulse
73: static const uint32 DCR_PCL_ABORT = 3; // Abort Input
74:
75: // | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
76: // OCR | DIR | --- | SIZE | CHAIN | REQG |
77: //
78: static const uint32 OCR_DIR_MtoD = 0; // Memory to Device
79: static const uint32 OCR_DIR_DtoM = 1; // Device to Memory
80: static const uint32 OCR_SIZE_8BIT = 0; // 8bit
81: static const uint32 OCR_SIZE_16BIT = 1; // 16bit
82: static const uint32 OCR_SIZE_32BIT = 2; // 32bit
83: static const uint32 OCR_SIZE_8BIT_UP = 3; // 8bit (Non-Pack Operation)
84: static const uint32 OCR_CHAIN_NOCHAIN = 0; // Chain operation is disabled
85: static const uint32 OCR_CHAIN_ARRAY = 2; // Array Chaining
86: static const uint32 OCR_CHAIN_LINK = 3; // Linked Array Chaining
87: static const uint32 OCR_REQG_AUTO_LIM = 0; // Auto Request (Limited)
88: static const uint32 OCR_REQG_AUTO_MAX = 1; // AUto Request (Max)
89: static const uint32 OCR_REQG_EXTERNAL = 2; // External Request
90: static const uint32 OCR_REQG_AUTOFIRST = 3; // Auto first then ext.
91:
92: // | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
93: // SCR | --- --- --- --- | MAC | DAC |
94: static const uint32 SCR_NO_COUNT = 0; // Does not count
95: static const uint32 SCR_COUNT_UP = 1; // Count up
96: static const uint32 SCR_COUNT_DOWN = 2; // Count down
97:
98: // CCR
99: static const uint32 CCR_STR = 0x80; // Start Operation
100: static const uint32 CCR_CNT = 0x40; // Continue Operation
101: static const uint32 CCR_HLT = 0x20; // Halt Operation
102: static const uint32 CCR_SAB = 0x10; // Software Abort
103: static const uint32 CCR_INT = 0x08; // Interrupt Enable
1.1 root 104:
105: // 各チャンネル
1.1.1.2 root 106: struct Channel {
107: // 二次変数など
108: int ch; // チャンネル番号
109: const char *desc; // チャンネルの用途(モニタ表示用)
110: DMACDevice *parent;
111:
112: // レジスタ
113:
114: // CSR
115: uint8 csr; // COC,BTC,NDT,ERR を保持
116: bool active; // ACT
117: bool pcl; // PCL の状態 (High が true)
118: bool prev_pcl; // 前回の PCL の状態 (High が true)
119:
1.1 root 120: uint8 cer;
121: uint8 dcr;
1.1.1.2 root 122: uint32 GetXRM() const { return (dcr >> 6); }
123: uint32 GetDTYP() const { return (dcr >> 4) & 3; }
124: uint32 GetDPS() const { return (dcr >> 3) & 1; }
125: uint32 GetPCL() const { return (dcr & 3); }
126:
1.1 root 127: uint8 ocr;
1.1.1.2 root 128: uint32 GetDIR() const { return (ocr >> 7); }
129: uint32 GetSIZE() const { return (ocr >> 4) & 3; }
130: uint32 GetCHAIN() const { return (ocr >> 2) & 3; }
131: uint32 GetREQG() const { return (ocr & 3); }
132:
133: // 転送種別 (DPS と SIZE から決まる)
134: uint32 xfertype;
135:
1.1 root 136: uint8 scr;
1.1.1.2 root 137: uint32 GetMAC() const { return (scr >> 2) & 3; }
138: uint32 GetDAC() const { return (scr & 3); }
139:
1.1 root 140: uint8 ccr;
1.1.1.2 root 141: bool int_enable; // INT: 割り込み許可なら true
142:
1.1 root 143: uint16 mtc;
144: uint32 mar;
145: uint32 dar;
146: uint16 btc;
147: uint32 bar;
148: uint8 niv;
149: uint8 eiv;
150: uint8 mfc;
151: uint8 cpr;
152: uint8 dfc;
153: uint8 bfc;
1.1.1.2 root 154:
155: uint8 PeekCSR() const;
156: void WriteCSR(uint32 data);
157: uint8 PeekCCR() const;
158: void WriteCCR(uint32 data);
159:
160: // 転送開始
161: void StartTransfer();
162: // 割り込み
163: void SetINT(uint32 val);
1.1 root 164: } chan[4];
165:
166: // 全体
167: uint8 gcr;
168: };
169:
170: class DMACDevice
171: : public IODevice
172: {
1.1.1.3 ! root 173: using inherited = IODevice;
1.1 root 174:
175: static const int baseaddr = 0xe84000;
176:
177: public:
178: DMACDevice();
1.1.1.3 ! root 179: ~DMACDevice() override;
1.1 root 180:
1.1.1.3 ! root 181: bool MonitorUpdate() override;
1.1.1.2 root 182:
183: // 転送
184: void AbortTransfer(DMAC::Channel *chan);
185: void Transfer(int arg);
186: int64 TransferM8toD8(DMAC::Channel *chan);
187: int64 TransferD8toM8(DMAC::Channel *chan);
188:
1.1.1.3 ! root 189: protected:
! 190: // BusIO インタフェース
! 191: static const uint NPORT = 256;
! 192: uint64 Read(uint32 addr);
! 193: uint64 Write(uint32 addr, uint32 data);
! 194: uint64 Peek(uint32 addr);
! 195:
1.1 root 196: private:
1.1.1.2 root 197: void MonitorReg4(int x, int y, uint32 reg, const char * const *names);
1.1 root 198:
199: struct DMAC dmac {};
1.1.1.2 root 200: Event event[4] {};
201:
202: static const char * const errnames[];
1.1 root 203: };
1.1.1.2 root 204:
205: extern std::unique_ptr<DMACDevice> gDMAC;
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