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Annotation of ntddk/inc/jazzdma.h, revision 1.1.1.1

1.1       root        1: /*++ BUILD Version: 0001    // Increment this if a change has global effects
                      2: 
                      3: Copyright (c) 1990  Microsoft Corporation
                      4: 
                      5: Module Name:
                      6: 
                      7:     jazzdma.h
                      8: 
                      9: Abstract:
                     10: 
                     11:     This module is the header file that describes the DMA control register
                     12:     structure for the Jazz system.
                     13: 
                     14: Author:
                     15: 
                     16:     David N. Cutler (davec) 13-Nov-1990
                     17: 
                     18: Revision History:
                     19: 
                     20: --*/
                     21: 
                     22: #ifndef _JAZZDMA_
                     23: #define _JAZZDMA_
                     24: 
                     25: //
                     26: // Define DMA register structure.
                     27: //
                     28: 
                     29: typedef struct _DMA_REGISTER {
                     30:     ULONG Long;
                     31:     ULONG Fill;
                     32: } DMA_REGISTER, *PDMA_REGISTER;
                     33: 
                     34: //
                     35: // Define DMA channel register structure.
                     36: //
                     37: 
                     38: typedef struct _DMA_CHANNEL {
                     39:     DMA_REGISTER Mode;
                     40:     DMA_REGISTER Enable;
                     41:     DMA_REGISTER ByteCount;
                     42:     DMA_REGISTER Address;
                     43: } DMA_CHANNEL, *PDMA_CHANNEL;
                     44: 
                     45: //
                     46: // Define DMA control register structure.
                     47: //
                     48: 
                     49: typedef volatile struct _DMA_REGISTERS {
                     50:     DMA_REGISTER Configuration;
                     51:     DMA_REGISTER RevisionLevel;
                     52:     DMA_REGISTER InvalidAddress;
                     53:     DMA_REGISTER TranslationBase;
                     54:     DMA_REGISTER TranslationLimit;
                     55:     DMA_REGISTER TranslationInvalidate;
                     56:     DMA_REGISTER CacheMaintenance;
                     57:     DMA_REGISTER RemoteFailedAddress;
                     58:     DMA_REGISTER MemoryFailedAddress;
                     59:     DMA_REGISTER PhysicalTag;
                     60:     DMA_REGISTER LogicalTag;
                     61:     DMA_REGISTER ByteMask;
                     62:     DMA_REGISTER BufferWindowLow;
                     63:     DMA_REGISTER BufferWindowHigh;
                     64:     DMA_REGISTER RemoteSpeed[16];
                     65:     DMA_REGISTER ParityDiagnosticLow;
                     66:     DMA_REGISTER ParityDiagnosticHigh;
                     67:     DMA_CHANNEL Channel[8];
                     68:     DMA_REGISTER InterruptSource;
                     69:     DMA_REGISTER Errortype;
                     70:     DMA_REGISTER RefreshRate;
                     71:     DMA_REGISTER RefreshCounter;
                     72:     DMA_REGISTER SystemSecurity;
                     73:     DMA_REGISTER InterruptInterval;
                     74:     DMA_REGISTER IntervalTimer;
                     75:     DMA_REGISTER InterruptAcknowledge;
                     76: } DMA_REGISTERS, *PDMA_REGISTERS;
                     77: 
                     78: //
                     79: // Define DMA channel mode register structure.
                     80: //
                     81: 
                     82: typedef struct _DMA_CHANNEL_MODE {
                     83:     ULONG AccessTime : 3;
                     84:     ULONG TransferWidth : 2;
                     85:     ULONG InterruptEnable : 1;
                     86:     ULONG BurstMode : 1;
                     87:     ULONG FastDmaCycle : 1;
                     88:     ULONG Reserved1 : 24;
                     89: } DMA_CHANNEL_MODE, *PDMA_CHANNEL_MODE;
                     90: 
                     91: //
                     92: // Define access time values.
                     93: //
                     94: 
                     95: #define ACCESS_40NS 0x0                 // 40ns access time
                     96: #define ACCESS_80NS 0x1                 // 80ns access time
                     97: #define ACCESS_120NS 0x2                // 120ns access time
                     98: #define ACCESS_160NS 0x3                // 160ns access time
                     99: #define ACCESS_200NS 0x4                // 200ns access time
                    100: #define ACCESS_240NS 0x5                // 240ns access time
                    101: #define ACCESS_280NS 0x6                // 280ns access time
                    102: #define ACCESS_320NS 0x7                // 320ns access time
                    103: 
                    104: //
                    105: // Define transfer width values.
                    106: //
                    107: 
                    108: #define WIDTH_8BITS 0x1                 // 8-bit transfer width
                    109: #define WIDTH_16BITS 0x2                // 16-bit transfer width
                    110: #define WIDTH_32BITS 0x3                // 32-bit transfer width
                    111: 
                    112: //
                    113: // Define DMA channel enable register structure.
                    114: //
                    115: 
                    116: typedef struct _DMA_CHANNEL_ENABLE {
                    117:     ULONG ChannelEnable : 1;
                    118:     ULONG TransferDirection : 1;
                    119:     ULONG Reserved1 : 6;
                    120:     ULONG TerminalCount : 1;
                    121:     ULONG MemoryError : 1;
                    122:     ULONG TranslationError : 1;
                    123:     ULONG Reserved2 : 21;
                    124: } DMA_CHANNEL_ENABLE, *PDMA_CHANNEL_ENABLE;
                    125: 
                    126: //
                    127: // Define transfer direction values.
                    128: //
                    129: 
                    130: #define DMA_READ_OP 0x0                 // read from device
                    131: #define DMA_WRITE_OP 0x1                // write to device
                    132: 
                    133: //
                    134: // Define interrupt source register structure.
                    135: //
                    136: 
                    137: typedef struct _DMA_INTERRUPT_SOURCE {
                    138:     ULONG InterruptPending : 8;
                    139:     ULONG MemoryParityError : 1;
                    140:     ULONG R4000AddressError : 1;
                    141:     ULONG IoCacheFlushError : 1;
                    142:     ULONG reserved1 : 21;
                    143: } DMA_INTERRUPT_SOURCE, *PDMA_INTERRUPT_SOURCE;
                    144: 
                    145: //
                    146: // Define translation table entry structure.
                    147: //
                    148: 
                    149: typedef volatile struct _TRANSLATION_ENTRY {
                    150:     ULONG PageFrame;
                    151:     ULONG Fill;
                    152: } TRANSLATION_ENTRY, *PTRANSLATION_ENTRY;
                    153: 
                    154: #endif // _JAZZDMA_

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