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1.1 root 1: /*++
2:
3: Copyright (c) 1993 Microsoft Corporation
4: Copyright (c) 1993 Logitech Inc.
5:
6: Module Name:
7:
8: uart.h
9:
10: Abstract:
11:
12: Hardware dependent support for the serial port.
13:
14: Environment:
15:
16: Kernel mode only.
17:
18: Notes:
19:
20: Revision History:
21:
22: --*/
23:
24: #ifndef UART_H
25: #define UART_H
26:
27: //
28: // Constants
29: //
30:
31: //
32: // Define the INS8250 ACE Register Offsets And Bit Definitions
33: //
34:
35: #define ACE_RBR 0 // Receiver Buffer
36: #define ACE_THR 0 // Transmit Holding Register
37:
38: #define ACE_IER 1 // Interrupt Enable
39: #define ACE_ERBFI 0x01 // Received Data Available 00000001b
40: #define ACE_ETBEI 0x02 // Transmitter Holding Register Empty 00000010b
41: #define ACE_ELSI 0x04 // Receiver Line Status 00000100b
42: #define ACE_EDSSI 0x08 // Modem Status 00001000b
43:
44: #define ACE_IIDR 2 // Interrupt Identification
45: #define ACE_IIP 0x01 // Inverted Interrupt Pending (0=int) 00000001b
46: #define ACE_IID 0x06 // Interrupt ID 00000110b
47: #define ACE_MSI 0x00 // Modem Status 00000000b
48: #define ACE_THREI 0x02 // Transmitter Holding Register Empty 00000010b
49: #define ACE_RDAI 0x04 // Received Data Available 00000100b
50: #define ACE_RLSI 0x06 // Receiver Line Status 00000110b
51:
52: #define ACE_LCR 3 // Line Control
53: #define ACE_WLS 0x03 // Word Length Select Bits 00000011b
54: #define ACE_WLS0 0x01 // Word Length Select Bit 0 00000001b
55: #define ACE_WLS1 0x02 // Word Length Select Bit 1 00000010b
56: #define ACE_5BW 0x00 // 5 Bit Words 00000000b
57: #define ACE_6BW 0x01 // 6 Bit Words 00000001b
58: #define ACE_7BW 0x02 // 7 Bit Words 00000010b
59: #define ACE_8BW 0x03 // 8 Bit Words 00000011b
60: #define ACE_STB 0x04 // Stop Bits 00000100b
61: #define ACE_1SB 0x00 // 1 Stop Bits (1.5 for 5 bit words) 00000000b
62: #define ACE_2SB 0x04 // 2 Stop Bits 00000100b
63: #define ACE_PEN 0x08 // Parity Enable 00001000b
64: #define ACE_PSB 0x30 // Parity Select bits 00110000b
65: #define ACE_EPS 0x10 // Even Parity Select 00010000b
66: #define ACE_SP 0x20 // Stick Parity 00100000b
67: #define ACE_SB 0x40 // Set Break 01000000b
68: #define ACE_DLAB 0x80 // Divisor Latch Access Bit 10000000b
69:
70: #define ACE_MCR 4 // Modem Control
71: #define ACE_DTR 0x01 // Data Terminal ready 00000001b
72: #define ACE_RTS 0x02 // Request To Send 00000010b
73: #define ACE_OUT1 0x04 // Output Line 1 00000100b
74: #define ACE_OUT2 0x08 // Output Line 2 00001000b
75: #define ACE_LOOP 0x10 // Loopback 00010000b
76:
77: #define ACE_LSR 5 // Line Status
78: #define ACE_DR 0x01 // Data Ready 00000001b
79: #define ACE_OR 0x02 // Overrun Error 00000010b
80: #define ACE_PE 0x04 // Parity Error 00000100b
81: #define ACE_FE 0x08 // Framing Error 00001000b
82: #define ACE_BI 0x10 // Break Interrupt 00010000b
83: #define ACE_THRE 0x20 // Transmitter Holding Register Empty 00100000b
84: #define ACE_TSRE 0x40 // Transmitter Shift Register Empty 01000000b
85: #define ACE_LERR (ACE_OR | ACE_PE | ACE_FE | ACE_BI)
86:
87: #define ACE_MSR 6 // Modem Status
88: #define ACE_DCTS 0x01 // Delta Clear to Send 00000001b
89: #define ACE_DDSR 0x02 // Delta Data Set Ready 00000010b
90: #define ACE_TERI 0x04 // Trailing Edge Ring Indicator 00000100b
91: #define ACE_DRLSD 0x08 // Delta Receive Line Signal Detect 00001000b
92: #define ACE_CTS 0x10 // Clear To Send 00010000b
93: #define ACE_DSR 0x20 // Data Set ready 00100000b
94: #define ACE_RI 0x40 // Ring Indicator 01000000b
95: #define ACE_RLSD 0x80 // Receive Line Signal Detect 10000000b
96:
97: #define ACE_DLL 0 // LSB Baud Rate Divisor
98:
99: #define ACE_DLM 1 // MSB Baud Rate Divisor
100:
101: //
102: // Define the Baud Generator Divisor. BaudClock (a value known via the
103: // hardware registry) is actually BAUD_GENERATOR_DIVISOR times the baud rate.
104: // For example, if the output frequency of the Baud Generator is 16 times
105: // the baud rate, then BAUD_GENERATOR_DIVISOR is 16.
106: //
107: // The Baud Rate Factor is BaudClock/BAUD_GENERATOR_DIVISOR.
108: //
109: // The Baud Rate Divisor for the DLAB is Baud Rate Factor divided by the
110: // desired baud rate, where the desired baud rate is 1200, 2400, and so on.
111: //
112:
113: #define BAUD_GENERATOR_DIVISOR 16
114:
115: //
116: // Type definitions.
117: //
118:
119: //
120: // UART configuration
121: //
122: typedef struct _UART {
123: ULONG BaudRate;
124: UCHAR LineCtrl;
125: UCHAR ModemCtrl;
126: UCHAR InterruptCtrl;
127: } UART, *PUART;
128:
129:
130: //
131: // Function prototypes
132: //
133:
134: VOID
135: UARTSetFifo(
136: PUCHAR Port,
137: UCHAR Value
138: );
139:
140: UCHAR
141: UARTGetInterruptCtrl(
142: PUCHAR Port
143: );
144:
145: UCHAR
146: UARTSetInterruptCtrl(
147: PUCHAR Port,
148: UCHAR Value
149: );
150:
151: UCHAR
152: UARTGetLineCtrl(
153: PUCHAR Port
154: );
155:
156: UCHAR
157: UARTSetLineCtrl(
158: PUCHAR Port,
159: UCHAR Value
160: );
161:
162: UCHAR
163: UARTGetModemCtrl(
164: PUCHAR Port
165: );
166:
167: UCHAR
168: UARTSetModemCtrl(
169: PUCHAR Port,
170: UCHAR Value
171: );
172:
173: BOOLEAN
174: UARTSetDlab(
175: PUCHAR Port,
176: BOOLEAN Set
177: );
178:
179: ULONG
180: UARTGetBaudRate(
181: PUCHAR Port,
182: ULONG BaudClock
183: );
184:
185: VOID
186: UARTSetBaudRate(
187: PUCHAR Port,
188: ULONG BaudRate,
189: ULONG BaudClock
190: );
191:
192: VOID
193: UARTGetState(
194: PUCHAR Port,
195: PUART Uart,
196: ULONG BaudClock
197: );
198:
199: VOID
200: UARTSetState(
201: PUCHAR Port,
202: PUART Uart,
203: ULONG BaudClock
204: );
205:
206: BOOLEAN
207: UARTIsReceiveBufferFull(
208: PUCHAR Port
209: );
210:
211: BOOLEAN
212: UARTReadCharNoWait(
213: PUCHAR Port,
214: PUCHAR Value
215: );
216:
217: BOOLEAN
218: UARTReadChar(
219: PUCHAR Port,
220: PUCHAR Value,
221: ULONG Timeout
222: );
223:
224: BOOLEAN
225: UARTFlushReadBuffer(
226: PUCHAR Port
227: );
228:
229: BOOLEAN
230: UARTIsTransmitEmpty(
231: PUCHAR Port
232: );
233:
234: BOOLEAN
235: UARTWriteChar(
236: PUCHAR Port,
237: UCHAR Value
238: );
239:
240: BOOLEAN
241: UARTWriteString(
242: PUCHAR Port,
243: PSZ Buffer
244: );
245:
246: #endif // UART_H
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