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1.1 root 1:
2: /*++ BUILD Version: 0002 // Increment this if a change has global effects
3:
4:
5: Copyright (c) 1992 Microsoft Corporation
6:
7: Module Name:
8:
9: hardware.h
10:
11: Abstract:
12:
13: This include file defines constants and types for
14: the Sound Blaster card.
15:
16: Author:
17:
18: Robin Speed (RobinSp) 20-Oct-92
19:
20: Revision History:
21:
22: --*/
23:
24: //
25: // Configuration info
26: //
27:
28: #define INTERRUPT_MODE Latched
29: #define IRQ_SHARABLE FALSE
30: #define SOUND_DEF_DMACHANNEL 1 // DMA channel no
31: #define SOUND_DEF_INT 7
32: #define SOUND_DEF_PORT 0x220
33:
34: #define SB_BASE_PORT 0x220
35:
36:
37: #define NUMBER_OF_SOUND_PORTS (0xf)
38:
39: //
40: // Don't support pre dsp version 1
41: //
42:
43: #define MIN_DSP_VERSION 0x0100
44:
45: //
46: // Defaults
47: //
48:
49: #define WAVE_INPUT_DEFAULT_RATE 11025 // Samples per second
50: #define WAVE_OUTPUT_DEFAULT_RATE 11025 // Samples per second
51:
52: //
53: // Port offsets from the base address
54: //
55:
56: #define MIX_ADDR_PORT 0x04 // Mixer ports
57:
58: #define VOICE_VOL_REG 0x04 // The mixer registers to use to set vol
59: #define MIC_MIX_REG 0x0A
60: #define LINEIN_VOL_REG 0x2E
61: #define SYNTH_VOL_REG 0x26
62: #define OUTPUT_SETTING_REG 0x0E
63:
64: #define MIX_DATA_PORT 0x05 // Where to write volume
65:
66: #define DATA_AVAIL_PORT 0x0E // data available port offset
67: #define DATA_STATUS_PORT 0x0C // write data staus port
68: #define DATA_PORT 0x0A // data port offset
69: #define RESET_PORT 0x06 // dsp reset port
70:
71: //
72: // Version checking
73: //
74:
75: #define SB1(pHw) ((pHw)->DSPVersion < 0x200)
76: #define SB2(pHw) ((pHw)->DSPVersion >= 0x200)
77: #define SBPRO(pHw) ((pHw)->DSPVersion >= 0x300)
78:
79: //
80: // DSP commands
81: //
82:
83: #define DSP_GET_VERSION 0xE1 // dsp version command
84: #define DSP_SPEAKER_ON 0xD1 // speaker on command
85: #define DSP_SPEAKER_OFF 0xD3 // speaker off command
86: #define DSP_SET_SAMPLE_RATE 0x40 // set the sample rate
87: #define DSP_SET_BLOCK_SIZE 0x48 // set dma block size
88: #define DSP_WRITE 0x14 // Start non-auto DMA
89: #define DSP_WRITE_AUTO 0x1C // auto init output mode
90: #define DSP_READ 0x24 // Start non-auto read
91: #define DSP_READ_AUTO 0x2C // auto init mode input
92: #define DSP_HALT_DMA 0xD0 // stop dma
93: #define DSP_CONTINUE_DMA 0xD4 // continue halted dma
94: #define DSP_STOP_AUTO 0xDA // exit from auto init mode
95: #define DSP_MIDI_READ 0x31 // Interrupt driver midi input
96: #define DSP_MIDI_READ_UART 0x35 // Interrupt driver midi input (uart mode)
97: #define DSP_MIDI_TS_READ 0x37 // Midi time-stamped read
98: #define DSP_MIDI_WRITE 0x38 // Midi output
99: #define DSP_GENERATE_INT 0xF2 // Special code to generate a interrupt
100:
101: //
102: // Hardware state data
103: //
104:
105: typedef struct {
106: ULONG Key; // For debugging
107: #define HARDWARE_KEY (*(ULONG *)"Hw ")
108:
109: //
110: // Configuration
111: //
112:
113: USHORT DSPVersion; // Card version
114: BOOLEAN ThunderBoard; // it's a Thunderboard
115:
116: PUCHAR PortBase; // base port address for sound
117: KSPIN_LOCK HwSpinLock; // Make sure we can write
118: // or read after checking status
119: // before someone else gets in!
120: // (could it be a spectrum?)
121:
122: UCHAR Half; // For keeping in synch for SB1
123: BOOLEAN SpeakerOn; // Speaker is on - prevent crash
124: // restarting DMA from Dpc routine
125: #if DBG
126: BOOLEAN LockHeld; // Get spin lock right
127: #endif // DBG
128:
129: //
130: // Hardware data
131: //
132:
133: BOOLEAN Stereo; // Was format stereo last time?
134: UCHAR Format; // Current wave format sent to device
135: UCHAR InputSource; // Where is input configured to?
136: } SOUND_HARDWARE, *PSOUND_HARDWARE;
137:
138: //
139: // Macros to assist in safely using our spin lock
140: //
141:
142: #if DBG
143: #define HwEnter(pHw) \
144: { \
145: KIRQL OldIrql; \
146: KeAcquireSpinLock(&(pHw)->HwSpinLock, &OldIrql);\
147: ASSERT((pHw)->LockHeld == FALSE); \
148: (pHw)->LockHeld = TRUE;
149:
150: #define HwLeave(pHw) \
151: ASSERT((pHw)->LockHeld == TRUE); \
152: (pHw)->LockHeld = FALSE; \
153: KeReleaseSpinLock(&(pHw)->HwSpinLock, OldIrql);\
154: }
155: #else
156: #define HwEnter(pHw) \
157: { \
158: KIRQL OldIrql; \
159: ASSERT((pHw)->LockHeld == FALSE); \
160: KeAcquireSpinLock(&(pHw)->HwSpinLock, &OldIrql);
161:
162: #define HwLeave(pHw) \
163: ASSERT((pHw)->LockHeld == TRUE); \
164: KeReleaseSpinLock(&(pHw)->HwSpinLock, OldIrql);\
165: }
166: #endif
167:
168: //
169: // Devices - these values are also used as array indices
170: //
171:
172: typedef enum {
173: WaveInDevice = 0,
174: WaveOutDevice,
175: MidiOutDevice,
176: MidiInDevice,
177: LineInDevice,
178: #ifdef MICMIX
179: MicDevice,
180: #endif // MICMIX
181: #ifdef MASTERVOLUME
182: MasterVolumeDevice,
183: #endif // MASTERVOLUME
184: NumberOfDevices
185: } SOUND_DEVICES;
186:
187: //
188: // macros for doing port reads
189: //
190:
191: #define INPORT(pHw, port) \
192: READ_PORT_UCHAR((PUCHAR)((pHw->PortBase) + (port)))
193:
194: #define OUTPORT(pHw, port, data) \
195: WRITE_PORT_UCHAR((PUCHAR)((pHw->PortBase) + (port)), (UCHAR)(data))
196:
197:
198: //
199: // Exported routines
200: //
201: VOID
202: HwSetVolume(
203: IN PLOCAL_DEVICE_INFO pLDI
204: );
205: UCHAR
206: dspRead(
207: IN PSOUND_HARDWARE pHw
208: );
209: BOOLEAN
210: dspReset(
211: PSOUND_HARDWARE pHw
212: );
213: BOOLEAN
214: dspWrite(
215: PSOUND_HARDWARE pHw,
216: UCHAR value
217: );
218: USHORT
219: dspGetVersion(
220: PSOUND_HARDWARE pHw
221: );
222: BOOLEAN
223: dspSpeakerOn(
224: PSOUND_HARDWARE pHw
225: );
226: BOOLEAN
227: dspSpeakerOff(
228: PSOUND_HARDWARE pHw
229: );
230:
231:
232:
233: /****************************************************************************
234: *
235: * Definitions for Media Vision Pro Audio Spectrum
236: *
237: ****************************************************************************/
238:
239: //==========================================================================
240: //
241: // Definitions from pasdef.h
242: //
243: //==========================================================================
244:
245: //
246: // THESE DEFINITIONS FOR CAPABILITIES FILED
247: //
248:
249:
250: #define DEFAULT_BASE 0x388 // default base I/O address of Pro AudioSpectrum
251:
252: //// THESE ARE BASE REGISTER ATES
253:
254: //
255: // Used only during initialization
256: //
257:
258: #define PCM_CONTROL 0x0f8a //
259:
260: #define ENHANCED_SCSI_DETECT_REG 0x7f89 //
261:
262: #define SYSTEM_CONFIG_1 0x8388 //
263: #define SYSTEM_CONFIG_2 0x8389 //
264: #define SYSTEM_CONFIG_3 0x838a //
265: #define SYSTEM_CONFIG_4 0x838b //
266:
267: #define IO_PORT_CONFIG_1 0xf388 //
268: #define IO_PORT_CONFIG_2 0xf389 //
269: #define IO_PORT_CONFIG_3 0xf38a //
270:
271: #define COMPATIBLE_REGISTER_ENABLE 0xf788 // SB and MPU emulation
272: #define EMULATION_ADDRESS_POINTER 0xf789 // D0-D3 is SB; D4-D7 is MPU
273:
274: #define EMULATION_INTERRUPT_POINTER 0xfb8a // MPU and SB IRQ and SB DMA settings
275:
276: #define CHIP_REV 0xff88 // MV101 chip revision number
277: #define MASTER_MODE_READ 0xff8b // aka Master Address Pointer
278:
279: //
280: // Used for volume setting
281: //
282:
283: #define MIXER_508_REG 0x078b // Mixer 508 1 port
284:
285: #define SERIAL_MIXER 0x0b88 // for Pas 1 and Pas 8
286: #define FEATURE_ENABLE 0x0b88 // for Pas 16 boards only
287: #define INTERRUPT_ENABLE 0x0b89 //
288: #define FILTER_REGISTER 0x0b8a //
289: #define INTERRUPT_CTRL_REG 0x0b8b //
290:
291:
292: //
293: // Only one of each of these
294: //
295:
296: #define PAS_2_WAKE_UP_REG 0x9a01 // aka Master Address Pointer
297:
298:
299: //
300: // Not used here
301: //
302:
303: #define TIMEOUT_COUNTER 0x4388 //
304: #define TIMEOUT_STATUS 0x4389 //
305: #define WAIT_STATE 0xbf88 //
306: #define PRESCALE_DIVIDER 0xbf8A //
307:
308: #define SLAVE_MODE_READ 0xef8b // bits D0-D1
309:
310:
311:
312: #define READ_PAS(pGDI, port) \
313: READ_PORT_UCHAR((PUCHAR)((port) ^ (pGDI->TranslateCode)))
314:
315: #define WRITE_PAS(pGDI, port, data) \
316: WRITE_PORT_UCHAR((PUCHAR)((port) ^ (pGDI->TranslateCode)), (UCHAR)(data))
317:
318:
319: // useful bit definitions
320: #define D0 (1<<0)
321: #define D1 (1<<1)
322: #define D2 (1<<2)
323: #define D3 (1<<3)
324: #define D4 (1<<4)
325: #define D5 (1<<5)
326: #define D6 (1<<6)
327: #define D7 (1<<7)
328:
329:
330: //// BIT FIELDS FOR COMPATIBLE_REGISTER_ENABLE
331: #define MPU_ENABLE_BIT D0
332: #define SB_ENABLE_BIT D1
333: #define SB_IRQ_ENABLE_BIT D2 // read only
334:
335: //// BIT FIELDS FOR FEATURE_ENABLE (0xb88)
336: #define PCM_FEATURE_ENABLE D0
337: #define FM_FEATURE_ENABLE D1
338: #define MIXER_FEATURE_ENABLE D2
339: #define SB_FEATURE_ENABLE D4
340:
341: /// BIT FIELDS FOR PCM CONTROL
342: #define PCM_STEREO D0+D3
343: #define PCM_DAC D4
344: #define PCM_MONO D5
345: #define PCM_ENGINE D6
346: #define PCM_DRQ D7
347:
348: /// BIT FIELDS FOR SYSTEM CONFIG 3
349: #define C3_ENHANCED_TIMER D0
350: #define C3_SB_CLOCK_EMUL D1 // don't set! see Brian Colvin
351: #define C3_VCO_INVERT D2
352: #define C3_INVERT_BCLK D3
353: #define C3_SYNC_PULSE D4
354: #define C3_PSEUDO_PCM_STEREO D5
355:
356: /// BIT FIELDS FOR INTERRUPT ENABLE
357: #define INT_LEFT_FM D0
358: #define INT_RIGHT_FM D1
359: #define INT_SB D1
360: #define INT_SAMPLE_RATE D2
361: #define INT_SAMPLE_BUFFER D3
362: #define INT_MIDI D4
363:
364:
365:
366: /// BIT FIELDS FOR COMPATIBLE REGISTER ENABLE
367: #define COMPAT_MPU D0
368: #define COMPAT_SB D1
369:
370:
371: /// IRQ POINTER VALUES FOR EMULATION INTERRUPT POINTER
372: #define EMUL_IRQ_NONE 0
373: #define EMUL_IRQ_2 1
374: #define EMUL_IRQ_3 2
375: #define EMUL_IRQ_5 3
376: #define EMUL_IRQ_7 4
377: #define EMUL_IRQ_10 5
378: #define EMUL_IRQ_11 6
379: #define EMUL_IRQ_12 7
380:
381: /// DMA POINTER VALUES FOR EMULATION DMA POINTER
382: #define EMUL_DMA_NONE 0
383: #define EMUL_DMA_1 1
384: #define EMUL_DMA_2 2
385: #define EMUL_DMA_3 3
386:
387:
388: /// BIT VALUES FOR FILTER REGISTER
389: #define FILTER_NOMUTE D5
390:
391:
392: #define MIXCROSSCAPS_NORMAL_STEREO 0 // Left->Left, Right->Right
393: #define MIXCROSSCAPS_RIGHT_TO_BOTH 1 // Right->Left, Right->Right
394: #define MIXCROSSCAPS_LEFT_TO_BOTH 2 // Left->Left, Left->Right
395: #define MIXCROSSCAPS_REVERSE_STEREO 4 // Left->Right, Right->Left
396: #define MIXCROSSCAPS_RIGHT_TO_LEFT 8 // Right->Left, Right->Right
397: #define MIXCROSSCAPS_LEFT_TO_RIGHT 0x10 // Left->Left, Left->Right
398:
399: #define OUT_AMPLIFIER 0
400: #define OUT_PCM 1
401:
402: #define _LEFT 1
403: #define _RIGHT 2
404:
405: #define _BASS 0
406: #define _TREBLE 1
407:
408:
409: #define MV_508_ADDRESS D7
410: #define MV_508_INPUT D4
411: #define MV_508_SWAP D6
412: #define MV_508_BASS (D0+D1)
413: #define MV_508_TREBLE (D2)
414: #define MV_508_EQMODE (D2+D0)
415:
416: #define MV_508_LOUDNESS D2
417: #define MV_508_ENHANCE (D1+D0)
418:
419: /// DEFINES FOR SERIAL MIXER
420: #define NATIONAL_SELECTMUTE_REG 0x40
421: #define NATIONAL_LOUD_ENH_REG 0x41
422: #define NATIONAL_BASS_REG 0x42
423: #define NATIONAL_TREB_REG 0x43
424: #define NATIONAL_LEFT_VOL_REG 0x44
425: #define NATIONAL_RIGHT_VOL_REG 0x45
426: #define NATIONAL_MODESELECT_REG 0x46
427:
428: #define NATIONAL_COMMAND D7
429: #define NATIONAL_LOUDNESS D0
430: #define NATIONAL_ENHANCE D1
431:
432: #define SERIAL_MIX_LEVEL D0
433: #define SERIAL_MIX_CLOCK D1
434: #define SERIAL_MIX_STROBE D2
435: #define SERIAL_MIX_MASTER D4
436: #define SERIAL_MIX_REALSOUND D6
437: #define SERIAL_MIX_DUALFM D7
438:
439:
440: // FILTER_REGISTER
441: #define fFIdatabits 0x1f // 00011111B filter select and decode field bits
442: #define fFImutebits D5 // filter mute field bit
443: #define fFIpcmbits (D7+D6) // 11000000B filter sample rate field bits
444: #define bFImute D5 // filter mute bit
445: #define bFIsrate D6 // filter sample rate timer mask
446: #define bFIsbuff D7 // filter sample buffer counter mask
447:
448: #define FILTERMAX 6 // six possible settings
449:
450: #define FILTER_MUTE 0 // mute - goes to PC speaker
451: #define FILTER_LEVEL_1 1 // 20hz to 2.9khz
452: #define FILTER_LEVEL_2 2 // 20hz to 5.9khz
453: #define FILTER_LEVEL_3 3 // 20hz to 8.9khz
454: #define FILTER_LEVEL_4 4 // 20hz to 11.9khz
455: #define FILTER_LEVEL_5 5 // 20hz to 15.9khz
456: #define FILTER_LEVEL_6 6 // 20hz to 17.8khz
457:
458:
459: /// SLAVE_MODE_READ BITS
460: #define SLAVE_MODE_OPL3 D2
461: #define SLAVE_MODE_16 D3
462:
463:
464: #define PASX_IN(pFI, port) \
465: READ_PORT_UCHAR(pFI->PROBase + ( (port) ^ pFI->TranslateCode) )
466:
467: #define PASX_OUT(pFI, port, data) \
468: WRITE_PORT_UCHAR(pFI->PROBase + ((port) ^ pFI->TranslateCode), (UCHAR)(data))
469:
470:
471: //==========================================================================
472: //
473: // Definitions from patch.h (mixer stuff)
474: //
475: //==========================================================================
476:
477: // INPUT LINES
478: #define IN_SYNTHESIZER 0
479: #define IN_MIXER 1
480: #define IN_EXTERNAL 2
481: #define IN_INTERNAL 3
482: #define IN_MICROPHONE 4
483: #define IN_PCM 5
484: #define IN_PC_SPEAKER 6
485: #define IN_SNDBLASTER 7
486:
487: #define OUT_AMPLIFIER 0
488: #define OUT_PCM 1
489:
490: #define NUM_IN_PATCHES 9
491: #define NUM_OUT_PATCHES 3
492:
493:
494: //==========================================================================
495: //
496: // Definitions from findpas.h (card searching)
497: //
498: //==========================================================================
499:
500:
501:
502: typedef struct {
503: USHORT wBoardRev;
504: USHORT wChipRev;
505: union
506: {
507: struct /* Our PAS_16 gives */
508: {
509: unsigned long CDInterfaceType:2; /* 3 */
510: unsigned long EnhancedSCSI:1; /* 0 - not enhanced SCSI*/
511: unsigned long DAC16:1; /* 1 DAC16 */
512:
513: unsigned long OPL_3:1; /* 1 OPL3 */
514: unsigned long Mixer_508:1; /* 1 Mixer 508 */
515: unsigned long DualDAC:1; /* 1 Dual DAC */
516: unsigned long MPU401:1; /* 0 NO mpu401 */
517:
518: unsigned long Slot16:1; /* 1 - slot 16 */
519: unsigned long MCA:1; /* 0 - not MCA */
520: unsigned long CDPC:1; /* 0 - not CDPC */
521: unsigned long SoundBlaster:1; /* 1 - sound blaster */
522:
523: unsigned long SCSI_IO_16:1; /* 1 - ? */
524: unsigned long reserved:2;
525: unsigned long Did_HW_Init:1; /* 0 - ? */
526: unsigned long unused:16;
527: } CapsBits;
528: ULONG dwCaps;
529: } Caps;
530: ULONG ProPort;
531: UCHAR ProDMA;
532: UCHAR ProIRQ;
533: USHORT SBPort;
534: UCHAR SBDMA;
535: UCHAR SBIRQ;
536: USHORT MPUPort;
537: UCHAR MPUIRQ;
538: UCHAR CDIRQ;
539: ULONG TranslateCode;
540: UCHAR ReservedB1;
541: UCHAR ReservedB2;
542: PUCHAR PROBase;
543: } FOUNDINFO, *PFOUNDINFO;
544:
545:
546: // these version numbers are found in 0B8Bh
547: #define PAS_VERSION_1 0x000 // original
548: #define PAS_PLUS 0x001 // Pro Audio Spectrum Plus with SCSI
549: #define PAS_SIXTEEN 0x001 // Pro Audio Spectrum 16 with SCSI
550: #define PAS_CDPC 0x007 // CDPC 05/06/92 mmq
551: #define BOARD_REV_MASK 07
552:
553:
554: #define CHIP_REV_B 0x002
555: #define CHIP_REV_D 0x004
556:
557: #define NO_PAS_INSTALLED 0x000 // can't find board
558:
559:
560: // CD interface type definitions
561: #define NO_INTERFACE 0
562: #define MITSUMI_TYPE 1
563: #define SONY_TYPE 2
564: #define SCSI_TYPE 3
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