![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to tokhrd.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [WindowsNT SDKs] / ntddk / src / network / ibmtok|
Return to tokhrd.h CVS log | Up to [WindowsNT SDKs] / ntddk / src / network / ibmtok |
1.1 root 1: /*++
2:
3: Copyright (c) 1990 Microsoft Corporation
4:
5: Module Name:
6:
7: tokhrd.h
8:
9: Abstract:
10:
11: The hardware-related definitions for the IBMTOK drivers.
12:
13:
14: Author:
15:
16: Anthony V. Ercolano (tonye) creation-date 19-Jun-1990
17: Adam Barr (adamba) 18-Feb-1991
18:
19: Environment:
20:
21: Architecturally, there is an assumption in this driver that we are
22: on a little endian machine.
23:
24: Notes:
25:
26: optional-notes
27:
28: Revision History:
29:
30: Sean Selitrennikoff - 9/??/91
31: Added/Changed definitions to allow for Microchannel cards too.
32:
33:
34: --*/
35:
36: #ifndef _IBMTOKHARDWARE_
37: #define _IBMTOKHARDWARE_
38:
39:
40:
41: //
42: // Start of I/O ports based on which adapter it is.
43: //
44:
45: #define PRIMARY_ADAPTER_OFFSET 0xa20
46: #define ALTERNATE_ADAPTER_OFFSET 0xa24
47:
48: //
49: // Offsets from above of the actual ports used.
50: //
51:
52: #define SWITCH_READ_1 0x000
53: #define RESET_LATCH 0x001
54: #define SWITCH_READ_2 0x002
55: #define RESET_RELEASE 0x002
56: #define INTERRUPT_RELEASE_ISA_ONLY 0x003
57:
58:
59: //
60: // Registers in the MMIO. These are in the Attachment
61: // Control Area, which starts at offset 0x1e00 of the ACA.
62: //
63:
64: #define RRR_LOW 0x1e00
65: #define RRR_HIGH 0x1e01
66: #define WRBR_LOW 0x1e02
67: #define WRBR_HIGH 0x1e03
68: #define ISRP_LOW 0x1e08
69: #define ISRP_LOW_RESET 0x1e28
70: #define ISRP_LOW_SET 0x1e48
71: #define ISRP_HIGH 0x1e09
72: #define ISRP_HIGH_RESET 0x1e29
73: #define ISRA_LOW 0x1e0a
74: #define ISRA_HIGH 0x1e0b
75: #define ISRA_HIGH_SET 0x1e4b
76: #define TCR_LOW 0x1e0c
77: #define TCR_HIGH 0x1e0d
78: #define TVR_LOW 0x1e0e
79: #define TVR_HIGH 0x1e0f
80: #define SRPR_LOW 0x1e18
81: #define SRPR_HIGH 0x1e19
82:
83:
84: //
85: // These are registers in the AIP (aka the ID PROM),
86: // which starts at offset 0x1f00 of the ACA.
87: //
88:
89: #define CHANNEL_IDENTIFIER 0x1f30
90: #define TOTAL_ADAPTER_RAM 0x1fa6
91: #define SHARED_RAM_PAGING 0x1fa8
92: #define MAX_4_MBPS_DHB 0x1faa
93: #define MAX_16_MBPS_DHB 0x1fac
94:
95:
96: //
97: // Bits in the ISRA Low (even) register.
98: //
99:
100: #define ISRA_LOW_TIMER_INTERRUPT 0x40
101: #define ISRA_LOW_INTERRUPT_MASK 0x01
102:
103: //
104: // Bits in the ISRA High (odd) register.
105: //
106:
107: #define ISRA_HIGH_COMMAND_IN_SRB 0x20
108: #define ISRA_HIGH_RESPONSE_IN_ASB 0x10
109: #define ISRA_HIGH_SRB_FREE_REQUEST 0x08
110: #define ISRA_HIGH_ASB_FREE_REQUEST 0x04
111: #define ISRA_HIGH_ARB_FREE 0x02
112: #define ISRA_HIGH_SSB_FREE 0x01
113:
114: //
115: // Bits in the ISRP Low (even) register.
116: //
117:
118: #define ISRP_LOW_NO_CHANNEL_CHECK 0x80
119: #define ISRP_LOW_INTERRUPT_ENABLE 0x40
120:
121: //
122: // Bits in the ISRP High (odd) register.
123: //
124:
125: #define ISRP_HIGH_ADAPTER_CHECK 0x40
126: #define ISRP_HIGH_SRB_RESPONSE 0x20
127: #define ISRP_HIGH_ASB_FREE 0x10
128: #define ISRP_HIGH_ARB_COMMAND 0x08
129: #define ISRP_HIGH_SSB_RESPONSE 0x04
130:
131: //
132: // Bits in the TCR Low (even) register.
133: //
134:
135: #define TCR_LOW_INTERRUPT_MASK 0x80
136: #define TCR_LOW_RELOAD_TIMER 0x40
137: #define TCR_LOW_COUNTER_ENABLE 0x20
138:
139:
140: #define WRITE_ADAPTER_REGISTER(a, r, v) \
141: NdisWriteRegisterUchar((a)->MmioRegion + (r), (v))
142:
143: #define READ_ADAPTER_REGISTER(a, r, v) \
144: NdisReadRegisterUchar((a)->MmioRegion + (r), (v))
145:
146:
147: #define WRITE_ADAPTER_PORT(a, p, v) \
148: NdisWritePortUchar((a)->NdisAdapterHandle, (a)->IbmtokPortAddress + (p), (v))
149:
150: #define READ_ADAPTER_PORT(a, p, v) \
151: NdisReadPortUchar((a)->NdisAdapterHandle, (a)->IbmtokPortAddress + (p), (v))
152:
153:
154:
155: //
156: // An IBMSHORT is a short that is in IBM byte ordering,
157: // with the high and low bytes reversed.
158: //
159:
160: typedef USHORT IBMSHORT;
161:
162:
163: //
164: // BUGBUG: These are dangerous because s appears twice in them.
165: //
166:
167: #define READ_IBMSHORT(s) (USHORT)((((PUCHAR)&s)[0] << 8) + ((PUCHAR)&s)[1])
168: #define WRITE_IBMSHORT(s, val) {\
169: USHORT _tmp; \
170: _tmp = (USHORT)((((val) >> 8) & 0xff) | (((val) & 0xff) << 8)); \
171: NdisWriteRegisterUshort((PUSHORT)&s, _tmp); \
172: }
173: #define USHORT_TO_IBMSHORT(val) (IBMSHORT)((((val) >> 8) & 0xff) | \
174: (((val) & 0xff) << 8))
175: #define IBMSHORT_TO_USHORT(val) (USHORT)((((val) >> 8) & 0xff) | \
176: (((val) & 0xff) << 8))
177:
178:
179: //
180: // An SRAM_PTR is a pointer into the Shared RAM on the adapter.
181: // It uses the IBM byte ordering.
182: //
183:
184: typedef IBMSHORT SRAM_PTR;
185:
186: #define NULL_SRAM_PTR ((SRAM_PTR)0x0000)
187:
188: #define SRAM_PTR_TO_PVOID(a, p) \
189: ((PVOID)((a)->SharedRam + IBMSHORT_TO_USHORT(p)))
190:
191: #define SHARED_RAM_ADDRESS(a, p) \
192: ((PVOID)((a)->SharedRam + ((ULONG)(p))))
193:
194:
195: //
196: // Macros to deal with the frame status field.
197: //
198:
199: #define GET_FRAME_STATUS_HIGH_AC(Fs) ((UCHAR)(((Fs) & 0xc0) >> 6))
200: #define GET_FRAME_STATUS_LOW_AC(Fs) ((UCHAR)(((Fs) & 0x0c) >> 2))
201:
202: #define AC_NOT_RECOGNIZED 0x00
203: #define AC_INVALID 0x01
204: #define AC_NOT_COPIED 0x10
205: #define AC_COPIED 0x11
206:
207:
208: //
209: // Some adapters have to have the upper section of the
210: // Shared RAM zeroed out after initialization.
211: //
212:
213: #define SHARED_RAM_ZERO_OFFSET ((PVOID)0xfe00)
214: #define SHARED_RAM_ZERO_LENGTH 0x0200
215:
216:
217: //
218: // The highest command correlator used by the adapter
219: // transmit logic.
220: //
221:
222: #define MAX_COMMAND_CORRELATOR 128
223:
224:
225: //
226: // This macro is used to set up the SRPR depending on
227: // the given address (should only be called if it is
228: // known that the adapter supports Shared RAM Paging!!).
229: //
230:
231: #define SETUP_SRPR(Adapter, Address) \
232: WRITE_ADAPTER_REGISTER((Adapter), SRPR_LOW, ((ULONG)(Address) >> 14))
233:
234:
235: //
236: // This macro retrieves the part of an address that
237: // is used once SETUP_SRPR has been called.
238: //
239:
240: #define SHARED_RAM_LOW_BITS(Address) \
241: ((ULONG)(Address) & 0x3fff)
242:
243:
244: //
245: // This macro determines if an address will fit on a
246: // single Shared RAM page. It makes sure that the beginning
247: // and end of the sequence have the same high two bits.
248: //
249:
250: #define SINGLE_SHARED_RAM_PAGE(Address, Length) \
251: (((ULONG)(Address) & 0xc000) == (((ULONG)(Address)+(Length)-1) & 0xc000))
252:
253:
254:
255: //
256: // Various structures which are read after the adapter
257: // is reset.
258: //
259:
260: typedef struct _ADAPTER_ADDRESS {
261: UCHAR NodeAddress[6];
262: UCHAR GroupAddress[4];
263: UCHAR FunctionalAddress[4];
264: } ADAPTER_ADDRESS, * PADAPTER_ADDRESS;
265:
266:
267: typedef struct _ADAPTER_PARAMETERS {
268: UCHAR PhysicalAddress[4];
269: UCHAR NaunNodeAddress[6];
270: UCHAR NaunPhysicalAddress[4];
271: UCHAR LastPoolAddress[6];
272: UCHAR Reserved1[2];
273: IBMSHORT TransmitAccessPriority;
274: IBMSHORT SourceClassAuthorization;
275: IBMSHORT LastAttentionCode;
276: UCHAR LastSourceAddress[6];
277: IBMSHORT LastBeaconType;
278: IBMSHORT LastMajorVector;
279: IBMSHORT RingStatus;
280: IBMSHORT SoftErrorTimer;
281: IBMSHORT FrontEndError;
282: IBMSHORT LocalRingNumber;
283: IBMSHORT MonitorErrorCode;
284: IBMSHORT BeaconTransmitType;
285: IBMSHORT BeaconReceiveType;
286: IBMSHORT FrameCorrelator;
287: UCHAR BeaconNaun[6];
288: UCHAR Reserved2[4];
289: UCHAR BeaconPhysicalAddress[4];
290: } ADAPTER_PARAMETERS, * PADAPTER_PARAMETERS;
291:
292:
293: typedef struct _SRB_BRING_UP_RESULT {
294: UCHAR Command;
295: UCHAR InitStatus;
296: UCHAR Reserved1[4];
297: IBMSHORT ReturnCode;
298: SRAM_PTR EncodedAddressPointer;
299: SRAM_PTR LevelAddressPointer;
300: SRAM_PTR AdapterAddressPointer; // points to ADAPTER_ADDRESS
301: SRAM_PTR ParameterAddressPointer; // points to ADAPTER_PARAMETERS
302: SRAM_PTR MacBufferPointer;
303: } SRB_BRING_UP_RESULT, * PSRB_BRING_UP_RESULT;
304:
305:
306:
307:
308: //
309: // Structure of the System Request Block as defined
310: // for various commands.
311: //
312:
313: typedef struct _SRB_GENERIC {
314: UCHAR Command;
315: UCHAR Reserved1[1];
316: UCHAR ReturnCode;
317: } SRB_GENERIC, * PSRB_GENERIC;
318:
319:
320: //
321: // Values for the SRB Command field.
322: //
323:
324: #define SRB_CMD_CLOSE_ADAPTER 0x04
325: #define SRB_CMD_INTERRUPT 0x00
326: #define SRB_CMD_MODIFY_OPEN_PARMS 0x01
327: #define SRB_CMD_OPEN_ADAPTER 0x03
328: #define SRB_CMD_READ_LOG 0x08
329: #define SRB_CMD_RESTORE_OPEN_PARMS 0x02
330: #define SRB_CMD_SET_FUNCTIONAL_ADDRESS 0x07
331: #define SRB_CMD_SET_GROUP_ADDRESS 0x06
332: #define SRB_CMD_TRANSMIT_DIR_FRAME 0x0a
333: #define SRB_CMD_DLC_STATISTICS 0x1e
334:
335:
336: typedef struct _SRB_OPEN_ADAPTER {
337: UCHAR Command;
338: UCHAR Reserved1[7];
339: IBMSHORT OpenOptions;
340: UCHAR NodeAddress[6];
341: UCHAR GroupAddress[4];
342: UCHAR FunctionalAddress[4];
343: IBMSHORT ReceiveBufferNum;
344: IBMSHORT ReceiveBufferLen;
345: IBMSHORT TransmitBufferLen;
346: UCHAR TransmitBufferNum;
347: UCHAR Reserved2[1];
348: UCHAR DlcValues[10];
349: UCHAR ProductId[18];
350: } SRB_OPEN_ADAPTER, * PSRB_OPEN_ADAPTER;
351:
352:
353: //
354: // Bit values for the OpenOptions field (these are
355: // reversed to be in IBMSHORT format).
356: //
357:
358: #define OPEN_LOOPBACK 0x0080
359: #define OPEN_DISABLE_HARD_ERROR 0x0040
360: #define OPEN_DISABLE_SOFT_ERROR 0x0020
361: #define OPEN_PASS_ADAPTER_MAC 0x0010
362: #define OPEN_PASS_ATTENTION_MAC 0x0008
363: #define OPEN_CONTENDER 0x0001
364: #define OPEN_PASS_BEACON_MAC 0x8000
365: #define OPEN_MODIFIED_TOKEN_RELEASE 0x1000
366:
367:
368: typedef struct _SRB_OPEN_RESPONSE {
369: UCHAR Command;
370: UCHAR Reserved1[1];
371: UCHAR ReturnCode;
372: UCHAR Reserved2[3];
373: IBMSHORT ErrorCode;
374: SRAM_PTR AsbPointer;
375: SRAM_PTR SrbPointer;
376: SRAM_PTR ArbPointer;
377: SRAM_PTR SsbPointer;
378: } SRB_OPEN_RESPONSE, * PSRB_OPEN_RESPONSE;
379:
380:
381: typedef struct _SRB_TRANSMIT_DIR_FRAME {
382: UCHAR Command;
383: UCHAR CommandCorrelator;
384: UCHAR ReturnCode;
385: UCHAR Reserved1[1];
386: IBMSHORT StationId;
387: } SRB_TRANSMIT_DIR_FRAME, * PSRB_TRANSMIT_DIR_FRAME;
388:
389:
390: typedef struct _SRB_SET_FUNCT_ADDRESS {
391: UCHAR Command;
392: UCHAR Reserved1[1];
393: UCHAR ReturnCode;
394: UCHAR Reserved2[3];
395: //
396: // Making this a TR_FUNCTIONAL_ADDRESS would cause
397: // the compiler to insert two bytes for alignment.
398: //
399: UCHAR FunctionalAddress[4];
400: } SRB_SET_FUNCT_ADDRESS, * PSRB_SET_FUNCT_ADDRESS;
401:
402:
403: typedef struct _SRB_SET_GROUP_ADDRESS {
404: UCHAR Command;
405: UCHAR Reserved1[1];
406: UCHAR ReturnCode;
407: UCHAR Reserved2[3];
408: //
409: // Making this a TR_FUNCTIONAL_ADDRESS would cause
410: // the compiler to insert two bytes for alignment.
411: //
412: UCHAR GroupAddress[4];
413: } SRB_SET_GROUP_ADDRESS, * PSRB_SET_GROUP_ADDRESS;
414:
415:
416: typedef struct _SRB_INTERRUPT {
417: UCHAR Command;
418: UCHAR Reserved1[1];
419: UCHAR ReturnCode;
420: } SRB_INTERRUPT, * PSRB_INTERRUPT;
421:
422:
423: typedef struct _SRB_READ_LOG {
424: UCHAR Command;
425: UCHAR Reserved1[1];
426: UCHAR ReturnCode;
427: UCHAR Reserved2[3];
428: UCHAR LineErrors;
429: UCHAR InternalErrors;
430: UCHAR BurstErrors;
431: UCHAR AcErrors;
432: UCHAR AbortDelimeters;
433: UCHAR Reserved3[1];
434: UCHAR LostFrames;
435: UCHAR ReceiveCongestionCount;
436: UCHAR FrameCopiedErrors;
437: UCHAR FrequencyErrors;
438: UCHAR TokenErrors;
439: UCHAR Reserved4[3];
440: } SRB_READ_LOG, * PSRB_READ_LOG;
441:
442:
443: typedef struct _SRB_DLC_STATS{
444: UCHAR Command;
445: UCHAR Reserved1;
446: UCHAR ReturnCode;
447: UCHAR Reserved2;
448: IBMSHORT StationId;
449: IBMSHORT CountersOffset;
450: IBMSHORT HeaderAddr;
451: UCHAR ResetOption;
452: }SRB_DLC_STATS, *PSRB_DLC_STATS;
453:
454:
455: typedef struct _DLC_COUNTERS{
456: IBMSHORT TransmitCount;
457: IBMSHORT ReceiveCount;
458: UCHAR TransmitErrors;
459: UCHAR ReceiveErrors;
460: IBMSHORT T1Expires;
461: UCHAR ReceivedCommand;
462: UCHAR SentCommand;
463: UCHAR PrimaryState;
464: UCHAR SecondaryState;
465: UCHAR SendState;
466: UCHAR ReceiveState;
467: UCHAR LastReceivedNr;
468: }DLC_COUNTERS, *PDLC_COUNTERS;
469:
470:
471:
472:
473: //
474: // Structure of the Adapter Request Block as defined
475: // for various commands.
476: //
477:
478: typedef struct _ARB_GENERIC {
479: UCHAR Command;
480: } ARB_GENERIC, * PARB_GENERIC;
481:
482:
483: //
484: // Values for the ARB Command field.
485: //
486:
487: #define ARB_CMD_DLC_STATUS 0x83
488: #define ARB_CMD_RECEIVED_DATA 0x81
489: #define ARB_CMD_RING_STATUS_CHANGE 0x84
490: #define ARB_CMD_TRANSMIT_DATA_REQUEST 0x82
491:
492:
493: typedef struct _ARB_RING_STATUS_CHANGE {
494: UCHAR Command;
495: UCHAR Reserved1[5];
496: IBMSHORT NetworkStatus;
497: } ARB_RING_STATUS_CHANGE, * PARB_RING_STATUS_CHANGE;
498:
499:
500: typedef struct _ARB_DLC_STATUS {
501: UCHAR Command;
502: UCHAR Reserved1[3];
503: IBMSHORT StationId;
504: IBMSHORT Status;
505: UCHAR FrmrData[5];
506: UCHAR AccessPriority;
507: UCHAR RemoteAddress[6];
508: UCHAR RemoteRsapValue;
509: } ARB_DLC_STATUS, * PARB_DLC_STATUS;
510:
511:
512: typedef struct _ARB_TRANSMIT_DATA_REQUEST {
513: UCHAR Command;
514: UCHAR CommandCorrelator;
515: UCHAR Reserved1[2];
516: IBMSHORT StationId;
517: SRAM_PTR DhbPointer;
518: } ARB_TRANSMIT_DATA_REQUEST, * PARB_TRANSMIT_DATA_REQUEST;
519:
520:
521: typedef struct _ARB_RECEIVED_DATA {
522: UCHAR Command;
523: UCHAR Reserved1[3];
524: IBMSHORT StationId;
525: SRAM_PTR ReceiveBuffer; // points to a RECEIVE_BUFFER
526: UCHAR LanHeaderLength;
527: UCHAR DlcHeaderLength;
528: IBMSHORT FrameLength;
529: UCHAR MessageType;
530: } ARB_RECEIVED_DATA, * PARB_RECEIVED_DATA;
531:
532:
533: typedef struct _RECEIVE_BUFFER {
534: //
535: // Leave out the first two reserved bytes.
536: //
537: SRAM_PTR NextBuffer;
538: UCHAR Reserved2[1];
539: UCHAR ReceiveFs;
540: IBMSHORT BufferLength;
541: UCHAR FrameData[1];
542: } RECEIVE_BUFFER, * PRECEIVE_BUFFER;
543:
544:
545:
546:
547: //
548: // Structure of the Adapter Status Block as defined
549: // for various commands.
550: //
551:
552: typedef struct _ASB_GENERIC {
553: UCHAR Command;
554: UCHAR Reserved1[1];
555: UCHAR ReturnCode;
556: } ASB_GENERIC, * PASB_GENERIC;
557:
558:
559: //
560: // The ASB Command field takes the same values as the
561: // ARB Command field.
562: //
563:
564: typedef struct _ASB_TRANSMIT_DATA_STATUS {
565: UCHAR Command;
566: UCHAR CommandCorrelator;
567: UCHAR ReturnCode;
568: UCHAR Reserved1[1];
569: IBMSHORT StationId;
570: IBMSHORT FrameLength;
571: UCHAR Reserved2[2];
572: } ASB_TRANSMIT_DATA_STATUS, * PASB_TRANSMIT_DATA_STATUS;
573:
574:
575: typedef struct _ASB_RECEIVED_DATA_STATUS {
576: UCHAR Command;
577: UCHAR Reserved1[1];
578: UCHAR ReturnCode;
579: UCHAR Reserved2[1];
580: IBMSHORT StationId;
581: SRAM_PTR ReceiveBuffer;
582: } ASB_RECEIVED_DATA_STATUS, * PASB_RECEIVED_DATA_STATUS;
583:
584:
585:
586:
587: //
588: // Structure of the System Status Block as defined
589: // for various commands.
590: //
591:
592: typedef struct _SSB_GENERIC {
593: UCHAR Command;
594: } SSB_GENERIC, * PSSB_GENERIC;
595:
596:
597: //
598: // The SSB Command field takes the same values as the
599: // SRB Command field.
600: //
601:
602: typedef struct _SSB_TRANSMIT_COMPLETE {
603: UCHAR Command;
604: UCHAR CommandCorrelator;
605: UCHAR ReturnCode;
606: UCHAR Reserved1[1];
607: IBMSHORT StationId;
608: UCHAR ErrorFrameStatus;
609: } SSB_TRANSMIT_COMPLETE, * PSSB_TRANSMIT_COMPLETE;
610:
611:
612:
613: #endif // _IBMTOKHARDWARE_
614:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.