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1.1 root 1: /*++
2:
3: Copyright (c) 1990 Microsoft Corporation
4:
5: Module Name:
6:
7: aha154x.h
8:
9: Abstract:
10:
11: This module contains the structures, specific to the Adaptec aha154x
12: host bus adapter, used by the SCSI miniport driver. Data structures
13: that are part of standard ANSI SCSI will be defined in a header
14: file that will be available to all SCSI device drivers.
15:
16: Author:
17:
18: Mike Glass December 1990
19:
20:
21: Revision History:
22:
23: --*/
24:
25: #include "scsi.h"
26:
27: //
28: // The following definitions are used to convert ULONG addresses
29: // to Adaptec's 3 byte address format.
30: //
31:
32: typedef struct _THREE_BYTE {
33: UCHAR Msb;
34: UCHAR Mid;
35: UCHAR Lsb;
36: } THREE_BYTE, *PTHREE_BYTE;
37:
38: //
39: // Convert four-byte Little Endian to three-byte Big Endian
40: //
41:
42: #define FOUR_TO_THREE(Three, Four) { \
43: ASSERT(!((Four)->Byte3)); \
44: (Three)->Lsb = (Four)->Byte0; \
45: (Three)->Mid = (Four)->Byte1; \
46: (Three)->Msb = (Four)->Byte2; \
47: }
48:
49: #define THREE_TO_FOUR(Four, Three) { \
50: (Four)->Byte0 = (Three)->Lsb; \
51: (Four)->Byte1 = (Three)->Mid; \
52: (Four)->Byte2 = (Three)->Msb; \
53: (Four)->Byte3 = 0; \
54: }
55:
56: ///////////////////////////////////////////////////////////////////////////////
57: //
58: // CCB - Adaptec SCSI Command Control Block
59: //
60: // The CCB is a superset of the CDB (Command Descriptor Block)
61: // and specifies detailed information about a SCSI command.
62: //
63: ///////////////////////////////////////////////////////////////////////////////
64:
65: //
66: // Byte 0 Command Control Block Operation Code
67: //
68:
69: #define SCSI_INITIATOR_COMMAND 0x00
70: #define TARGET_MODE_COMMAND 0x01
71: #define SCATTER_GATHER_COMMAND 0x04
72:
73: //
74: // Byte 1 Address and Direction Control
75: //
76:
77: #define CCB_TARGET_ID_SHIFT 0x06 // CCB Op Code = 00, 02
78: #define CCB_INITIATOR_ID_SHIFT 0x06 // CCB Op Code = 01
79: #define CCB_DATA_XFER_OUT 0x10 // Write
80: #define CCB_DATA_XFER_IN 0x08 // Read
81: #define CCB_LUN_MASK 0x07 // Logical Unit Number
82:
83: //
84: // Byte 2 SCSI_Command_Length - Length of SCSI CDB
85: //
86: // Byte 3 Request Sense Allocation Length
87: //
88:
89: #define FOURTEEN_BYTES 0x00 // Request Sense Buffer size
90: #define NO_AUTO_REQUEST_SENSE 0x01 // No Request Sense Buffer
91:
92: //
93: // Bytes 4, 5 and 6 Data Length // Data transfer byte count
94: //
95: // Bytes 7, 8 and 9 Data Pointer // SGD List or Data Buffer
96: //
97: // Bytes 10, 11 and 12 Link Pointer // Next CCB in Linked List
98: //
99: // Byte 13 Command Link ID // TBD (I don't know yet)
100: //
101: // Byte 14 Host Status // Host Adapter status
102: //
103:
104: #define CCB_COMPLETE 0x00 // CCB completed without error
105: #define CCB_LINKED_COMPLETE 0x0A // Linked command completed
106: #define CCB_LINKED_COMPLETE_INT 0x0B // Linked complete with interrupt
107: #define CCB_SELECTION_TIMEOUT 0x11 // Set SCSI selection timed out
108: #define CCB_DATA_OVER_UNDER_RUN 0x12
109: #define CCB_UNEXPECTED_BUS_FREE 0x13 // Target dropped SCSI BSY
110: #define CCB_PHASE_SEQUENCE_FAIL 0x14 // Target bus phase sequence failure
111: #define CCB_BAD_MBO_COMMAND 0x15 // MBO command not 0, 1 or 2
112: #define CCB_INVALID_OP_CODE 0x16 // CCB invalid operation code
113: #define CCB_BAD_LINKED_LUN 0x17 // Linked CCB LUN different from first
114: #define CCB_INVALID_DIRECTION 0x18 // Invalid target direction
115: #define CCB_DUPLICATE_CCB 0x19 // Duplicate CCB
116: #define CCB_INVALID_CCB 0x1A // Invalid CCB - bad parameter
117:
118: //
119: // Byte 15 Target Status
120: //
121: // See SCSI.H files for these statuses.
122: //
123:
124: //
125: // Bytes 16 and 17 Reserved (must be 0)
126: //
127:
128: //
129: // Bytes 18 through 18+n-1, where n=size of CDB Command Descriptor Block
130: //
131:
132: //
133: // Bytes 18+n through 18+m-1, where m=buffer size Allocated for Sense Data
134: //
135:
136: #define REQUEST_SENSE_BUFFER_SIZE 18
137:
138: ///////////////////////////////////////////////////////////////////////////////
139: //
140: // Scatter/Gather Segment List Definitions
141: //
142: ///////////////////////////////////////////////////////////////////////////////
143:
144: //
145: // Adapter limits
146: //
147:
148: #define MAX_SG_DESCRIPTORS 17
149: #define MAX_TRANSFER_SIZE 64 * 1024
150:
151: //
152: // Scatter/Gather Segment Descriptor Definition
153: //
154:
155: typedef struct _SGD {
156: THREE_BYTE Length;
157: THREE_BYTE Address;
158: } SGD, *PSGD;
159:
160: typedef struct _SDL {
161: SGD Sgd[MAX_SG_DESCRIPTORS];
162: } SDL, *PSDL;
163:
164: #define SEGMENT_LIST_SIZE MAX_SG_DESCRIPTORS * sizeof(SGD)
165:
166: ///////////////////////////////////////////////////////////////////////////////
167: //
168: // CCB Typedef
169: //
170:
171: typedef struct _CCB {
172: UCHAR OperationCode;
173: UCHAR ControlByte;
174: UCHAR CdbLength;
175: UCHAR RequestSenseLength;
176: THREE_BYTE DataLength;
177: THREE_BYTE DataPointer;
178: THREE_BYTE LinkPointer;
179: UCHAR LinkIdentifier;
180: UCHAR HostStatus;
181: UCHAR TargetStatus;
182: UCHAR Reserved[2];
183: UCHAR Cdb[MAXIMUM_CDB_SIZE];
184: PVOID SrbAddress;
185: PVOID AbortSrb;
186: SDL Sdl;
187: UCHAR RequestSenseBuffer[REQUEST_SENSE_BUFFER_SIZE];
188: } CCB, *PCCB;
189:
190: //
191: // CCB and request sense buffer
192: //
193:
194: #define CCB_SIZE sizeof(CCB)
195:
196: ///////////////////////////////////////////////////////////////////////////////
197: //
198: // Adapter Command Overview
199: //
200: // Adapter commands are issued by writing to the Command/Data Out port.
201: // They are used to initialize the host adapter and to establish control
202: // conditions within the host adapter. They may not be issued when there
203: // are outstanding SCSI commands.
204: //
205: // All adapter commands except Start SCSI(02) and Enable Mailbox-Out
206: // Interrupt(05) must be executed only when the IDLE bit (Status bit 4)
207: // is one. Many commands require additional parameter bytes which are
208: // then written to the Command/Data Out I/O port (base+1). Before each
209: // byte is written by the host to the host adapter, the host must verify
210: // that the CDF bit (Status bit 3) is zero, indicating that the command
211: // port is ready for another byte of information. The host adapter usually
212: // clears the Command/Data Out port within 100 microseconds. Some commands
213: // require information bytes to be returned from the host adapter to the
214: // host. In this case, the host monitors the DF bit (Status bit 2) to
215: // determine when the host adapter has placed a byte in the Data In I/O
216: // port for the host to read. The DF bit is reset automatically when the
217: // host reads the byte. The format of each adapter command is strictly
218: // defined, so the host adapter and host system can always agree upon the
219: // correct number of parameter bytes to be transferred during a command.
220: //
221: //
222: ///////////////////////////////////////////////////////////////////////////////
223:
224: //
225: // Host Adapter Command Operation Codes
226: //
227:
228: #define AC_NO_OPERATION 0x00
229: #define AC_MAILBOX_INITIALIZATION 0x01
230: #define AC_START_SCSI_COMMAND 0x02
231: #define AC_START_BIOS_COMMAND 0x03
232: #define AC_ADAPTER_INQUIRY 0x04
233: #define AC_ENABLE_MBO_AVAIL_INT 0x05
234: #define AC_SET_SELECTION_TIMEOUT 0x06
235: #define AC_SET_BUS_ON_TIME 0x07
236: #define AC_SET_BUS_OFF_TIME 0x08
237: #define AC_SET_TRANSFER_SPEED 0x09
238: #define AC_RET_INSTALLED_DEVICES 0x0A
239: #define AC_RET_CONFIGURATION_DATA 0x0B
240: #define AC_ENABLE_TARGET_MODE 0x0C
241: #define AC_RETURN_SETUP_DATA 0x0D
242: #define AC_WRITE_CHANNEL_2_BUFFER 0x1A
243: #define AC_READ_CHANNEL_2_BUFFER 0x1B
244: #define AC_WRITE_FIFO_BUFFER 0x1C
245: #define AC_READ_FIFO_BUFFER 0x1D
246: #define AC_ECHO_COMMAND_DATA 0x1F
247: #define AC_SET_HA_OPTION 0x21
248: #define AC_GET_BIOS_INFO 0x28
249: #define AC_SET_MAILBOX_INTERFACE 0x29
250: #define AC_EXTENDED_SETUP_INFO 0x8D
251:
252:
253: //
254: // DMA Transfer Speeds
255: //
256:
257: #define DMA_SPEED_50_MBS 0x00
258:
259: //
260: // I/O Port Interface
261: //
262:
263: typedef struct _BASE_REGISTER {
264: UCHAR StatusRegister;
265: UCHAR CommandRegister;
266: UCHAR InterruptRegister;
267: } BASE_REGISTER, *PBASE_REGISTER;
268:
269: //
270: // Base+0 Write: Control Register
271: //
272:
273: #define IOP_HARD_RESET 0x80 // bit 7
274: #define IOP_SOFT_RESET 0x40 // bit 6
275: #define IOP_INTERRUPT_RESET 0x20 // bit 5
276: #define IOP_SCSI_BUS_RESET 0x10 // bit 4
277:
278: //
279: // Base+0 Read: Status
280: //
281:
282: #define IOP_SELF_TEST 0x80 // bit 7
283: #define IOP_INTERNAL_DIAG_FAILURE 0x40 // bit 6
284: #define IOP_MAILBOX_INIT_REQUIRED 0x20 // bit 5
285: #define IOP_SCSI_HBA_IDLE 0x10 // bit 4
286: #define IOP_COMMAND_DATA_OUT_FULL 0x08 // bit 3
287: #define IOP_DATA_IN_PORT_FULL 0x04 // bit 2
288: #define IOP_INVALID_COMMAND 0X01 // bit 1
289:
290: //
291: // Base+1 Write: Command/Data Out
292: //
293:
294: //
295: // Base+1 Read: Data In
296: //
297:
298: //
299: // Base+2 Read: Interrupt Flags
300: //
301:
302: #define IOP_ANY_INTERRUPT 0x80 // bit 7
303: #define IOP_SCSI_RESET_DETECTED 0x08 // bit 3
304: #define IOP_COMMAND_COMPLETE 0x04 // bit 2
305: #define IOP_MBO_EMPTY 0x02 // bit 1
306: #define IOP_MBI_FULL 0x01 // bit 0
307:
308: ///////////////////////////////////////////////////////////////////////////////
309: //
310: // Mailbox Definitions
311: //
312: //
313: ///////////////////////////////////////////////////////////////////////////////
314:
315: //
316: // Mailbox Definition
317: //
318:
319: #define MB_COUNT 0x04 // number of mailboxes
320:
321: //
322: // Mailbox Out
323: //
324:
325: typedef struct _MBO {
326: UCHAR Command;
327: THREE_BYTE Address;
328: } MBO, *PMBO;
329:
330: //
331: // MBO Command Values
332: //
333:
334: #define MBO_FREE 0x00
335: #define MBO_START 0x01
336: #define MBO_ABORT 0x02
337:
338: //
339: // Mailbox In
340: //
341:
342: typedef struct _MBI {
343: UCHAR Status;
344: THREE_BYTE Address;
345: } MBI, *PMBI;
346:
347: //
348: // MBI Status Values
349: //
350:
351: #define MBI_FREE 0x00
352: #define MBI_SUCCESS 0x01
353: #define MBI_ABORT 0x02
354: #define MBI_NOT_FOUND 0x03
355: #define MBI_ERROR 0x04
356:
357: //
358: // Mailbox Initialization
359: //
360:
361: typedef struct _MAILBOX_INIT {
362: UCHAR Count;
363: THREE_BYTE Address;
364: } MAILBOX_INIT, *PMAILBOX_INIT;
365:
366: #define MAILBOX_UNLOCK 0x00
367: #define TRANSLATION_LOCK 0x01 // mailbox locked for extended BIOS
368: #define DYNAMIC_SCAN_LOCK 0x02 // mailbox locked for 154xC
369: #define TRANSLATION_ENABLED 0x08 // extended BIOS translation (1023/64)
370:
371: //
372: // Scatter/Gather firmware bug detection
373: //
374:
375: #define BOARD_ID 0x00
376: #define HARDWARE_ID 0x01
377: #define FIRMWARE_ID 0x02
378: #define OLD_BOARD_ID1 0x00
379: #define OLD_BOARD_ID2 0x30
380: #define A154X_BOARD 0x41
381: #define A154X_BAD_HARDWARE_ID 0x30
382: #define A154X_BAD_FIRMWARE_ID 0x33
383:
384: //
385: // MCA specific definitions.
386: //
387:
388: #define NUMBER_POS_SLOTS 8
389: #define POS_IDENTIFIER 0x0F1F
390: #define POS_PORT_MASK 0xC7
391: #define POS_PORT_130 0x01
392: #define POS_PORT_134 0x41
393: #define POS_PORT_230 0x02
394: #define POS_PORT_234 0x42
395: #define POS_PORT_330 0x03
396: #define POS_PORT_334 0x43
397:
398: typedef struct _POS_DATA {
399: USHORT AdapterId;
400: UCHAR BiosEnabled;
401: UCHAR IoPortInformation;
402: UCHAR ScsiInformation;
403: UCHAR DmaInformation;
404: } POS_DATA, *PPOS_DATA;
405:
406: typedef struct _INIT_DATA {
407:
408: ULONG AdapterId;
409: ULONG CardSlot;
410: POS_DATA PosData[NUMBER_POS_SLOTS];
411:
412: } INIT_DATA, *PINIT_DATA;
413:
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