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1.1 root 1:
2: /*++
3:
4: Copyright (c) 1991 Microsoft Corporation
5:
6: Module Name:
7:
8: 174x.h
9:
10: Abstract:
11:
12: This module contains the structures, specific to the Adaptec 174x
13: host bus adapter, used by the SCSI port driver. Data structures
14: that are part of standard ANSI SCSI will be defined in a header
15: file that will be available to all SCSI device drivers.
16:
17: Author:
18:
19: Mike Glass
20:
21: Revision History:
22:
23: --*/
24:
25: #include "scsi.h"
26:
27: #define MAXIMUM_EISA_SLOTS 0x10
28: #define EISA_ADDRESS_BASE 0x0C80
29: #define MAXIMUM_SGL_DESCRIPTORS 0x11
30: #define MAXIMUM_DESCRIPTOR_SIZE 0x3FFFFF
31: #define MAXIMUM_TRANSFER_SIZE 0xFFFFFF
32: #define REQUEST_SENSE_BUFFER_SIZE 0x18
33:
34: //***************
35: // *
36: // Status Block *
37: // *
38: //***************
39:
40: typedef struct _STATUS_BLOCK {
41: USHORT StatusWord;
42: UCHAR HaStatus;
43: UCHAR TargetStatus;
44: ULONG ResidualByteCount;
45: ULONG ResidualAddress;
46: USHORT AdditionalStatusLength;
47: UCHAR RequestSenseLength;
48: UCHAR Reserved0;
49: ULONG Reserved1;
50: ULONG Reserved2;
51: USHORT Reserved3;
52: UCHAR Cdb[6];
53: } STATUS_BLOCK, *PSTATUS_BLOCK;
54:
55: //
56: // Status Word Bit Values
57: //
58:
59: #define SB_STATUS_NO_ERROR 0x0001
60: #define SB_STATUS_DATA_UNDERRUN 0x0002
61: #define SB_STATUS_HA_QUEUE_FULL 0x0008
62: #define SB_STATUS_SPECIFICATION_CHECK 0x0010
63: #define SB_STATUS_DATA_OVERRUN 0x0020
64: #define SB_STATUS_CHAINING_HALTED 0x0040
65: #define SB_STATUS_SCB_INTERRUPT 0x0080
66: #define SB_STATUS_ADDITIONAL_STATUS 0x0100
67: #define SB_STATUS_SENSE_INFORMATION 0x0200
68: #define SB_STATUS_INIT_REQUIRED 0x0800
69: #define SB_STATUS_MAJOR_ERROR 0x1000
70: #define SB_STATUS_EXT_CONT_ALLEGIANCE 0x4000
71:
72: //
73: // HOST_ADAPTER_STATUS
74: //
75:
76: #define SB_HASTATUS_HOST_ABORTED 0x04
77: #define SB_HASTATUS_ADAPTER_ABORTED 0x05
78: #define SB_HASTATUS_FW_NOT_DOWNLOADED 0x08
79: #define SB_HASTATUS_TARGET_NOT_USED 0x0A
80: #define SB_HASTATUS_SELECTION_TIMEOUT 0x11
81: #define SB_HASTATUS_DATA_OVERUNDER_RUN 0x12
82: #define SB_HASTATUS_UNEXPECTED_BUS_FREE 0x13
83: #define SB_HASTATUS_INVALID_BUS_PHASE 0x14
84: #define SB_HASTATUS_INVALID_OPERATION 0x16
85: #define SB_HASTATUS_INVALID_SCSI_LINK 0x17
86: #define SB_HASTATUS_INVALID_ECB 0x18
87: #define SB_HASTATUS_DUPLICATE_TARGET 0x19
88: #define SB_HASTATUS_INVALID_SGL 0x1A
89: #define SB_HASTATUS_REQUEST_SENSE_FAILED 0x1B
90: #define SB_HASTATUS_TAGGED_QUEUE_REJECTED 0x1C
91: #define SB_HASTATUS_ADAPTER_HARDWARE_ERROR 0x20
92: #define SB_HASTATUS_TARGET_NO_RESPOND 0x21
93: #define SB_HASTATUS_ADAPTER_RESET_BUS 0x22
94: #define SB_HASTATUS_DEVICE_RESET_BUS 0x23
95: #define SB_HASTATUS_CHECKSUM_FAILURE 0x80
96:
97: //
98: // Target Status - See SCSI.H
99: //
100:
101: //**********************
102: // *
103: // Scatter Gather List *
104: // *
105: //**********************
106:
107: typedef struct _SG_DESCRIPTOR {
108: ULONG Address;
109: ULONG Length;
110: } SG_DESCRIPTOR, *PSG_DESCRIPTOR;
111:
112: typedef struct _SGL {
113: SG_DESCRIPTOR Descriptor[MAXIMUM_SGL_DESCRIPTORS];
114: } SGL, *PSGL;
115:
116: //**************************
117: // *
118: // Enhanced Control Block *
119: // *
120: //**************************
121:
122: typedef struct _ECB {
123: USHORT Command;
124: USHORT Flags[2];
125: USHORT Reserved1;
126: ULONG PhysicalSgl;
127: ULONG SglLength;
128: ULONG StatusBlockAddress;
129: ULONG NextEcb;
130: ULONG Reserved2;
131: ULONG SenseInfoAddress;
132: UCHAR SenseInfoLength;
133: UCHAR CdbLength;
134: USHORT DataCheckSum;
135: UCHAR Cdb[12];
136: PVOID SrbAddress;
137: PSCSI_REQUEST_BLOCK AbortSrb;
138: SGL Sgl;
139: STATUS_BLOCK StatusBlock;
140: } ECB, *PECB;
141:
142: //
143: // Commands
144: //
145:
146: #define ECB_COMMAND_NO_OPERATION 0x0000
147: #define ECB_COMMAND_INITIATOR_COMMAND 0x0001
148: #define ECB_COMMAND_RUN_DIAGNOSTICS 0x0005
149: #define ECB_COMMAND_INITIALIZE_SCSI 0x0006
150: #define ECB_COMMAND_READ_SENSE_INFO 0x0008
151: #define ECB_COMMAND_DOWNLOAD_FIRMWARE 0x0009
152: #define ECB_COMMAND_READ_INQUIRY_DATA 0x000A
153: #define ECB_COMMAND_TARGET_COMMAND 0x0010
154:
155: //
156: // Flag word 1
157: //
158:
159: #define ECB_FLAGS_CHAIN_NO_ERROR 0x0001
160: #define ECB_FLAGS_DISABLE_INTERRUPT 0x0080
161: #define ECB_FLAGS_SUPPRESS_UNDERRUN 0x0400
162: #define ECB_FLAGS_SCATTER_GATHER 0x1000
163: #define ECB_FLAGS_DISABLE_STATUS_BLOCK 0x4000
164: #define ECB_FLAGS_AUTO_REQUEST_SENSE 0x8000
165:
166: //
167: // Flag word 2
168: //
169:
170: #define ECB_FLAGS_SIMPLE_QUEUE_TAG 0x0008
171: #define ECB_FLAGS_HEAD_QUEUE_TAG 0x0018
172: #define ECB_FLAGS_ORDERED_QUEUE_TAG 0x0028
173: #define ECB_FLAGS_NO_DISCONNECT 0x0040
174: #define ECB_FLAGS_DATA_TRANSFER 0x0100
175: #define ECB_FLAGS_READ 0x0300
176: #define ECB_FLAGS_WRITE 0x0100
177: #define ECB_FLAGS_SUPPRESS_TRANSFER 0x0400
178: #define ECB_FLAGS_CALCULATE_CHECKSUM 0x0800
179: #define ECB_FLAGS_ERROR_RECOVERY 0x4000
180:
181: //****************************
182: // *
183: // EISA Controller registers *
184: // *
185: //****************************
186:
187: typedef struct _EISA_CONTROLLER {
188:
189: UCHAR BoardId[4]; // zC80
190: UCHAR EBControl; // zC84
191: UCHAR Unused[0x3B]; // zC85
192: UCHAR PortAddress; // zCC0
193: UCHAR BiosAddress; // zCC1
194: UCHAR Interrupt; // zCC2
195: UCHAR ScsiId; // zCC3
196: UCHAR DmaChannel; // zCC4
197: UCHAR Reserved[11]; // zCC5
198: ULONG MailBoxOut; // zCD0
199: UCHAR Attention; // zCD4
200: UCHAR Control; // zCD5
201: UCHAR InterruptStatus; // zCD6
202: UCHAR Status; // zCD7
203: ULONG MailBoxIn; // zCD8
204: UCHAR MoreStatus; // zCDC
205:
206: } EISA_CONTROLLER, *PEISA_CONTROLLER;
207:
208: //
209: // PortAddress Register Definition
210: //
211:
212: #define ENHANCED_INTERFACE_ENABLED 0x80
213:
214: //
215: // Bios address mask.
216: //
217:
218: #define BIOS_ADDRESS 0x0f
219: #define BIOS_ENABLED 0x40
220: #define BIOS_LENGTH 0x4000
221:
222: //
223: // Attention Register Bit Definitions
224: //
225:
226: #define IMMEDIATE_COMMAND 0x10
227: #define START_ECB 0x40
228: #define ABORT_ECB 0x50
229:
230:
231: //
232: // Control Register Bit Definitions
233: //
234:
235: #define SET_HOST_READY 0x20
236: #define CLEAR_INTERRUPT 0x40
237: #define HARD_RESET 0x80
238:
239: //
240: // Interrupt Status Register Bit Definitions
241: //
242:
243: #define ECB_COMPLETE_SUCCESS 0x01
244: #define ECB_COMPLETE_SUCCESS_RETRY 0x05
245: #define ADAPTER_FAILURE 0x07
246: #define IMMEDIATE_COMMAND_SUCCESS 0x0A
247: #define ECB_COMPLETE_ERROR 0x0C
248: #define ASYNCHRONOUS_EVENT_NOTIFICATION 0x0D
249: #define IMMEDIATE_COMMAND_ERROR 0x0E
250:
251: //
252: // Status Register Bit Definition
253: //
254:
255: #define ADAPTER_BUSY 0x01
256: #define INTERRUPT_PENDING 0x02
257: #define MAILBOX_OUT_EMPTY 0x04
258:
259: //
260: // Immediate commands
261: //
262:
263: #define ECB_IMMEDIATE_RESET 0x00000080
264: #define ECB_IMMEDIATE_RESUME 0x00000090
265:
266: //
267: // Status2 Register Definition
268: //
269:
270: #define HOST_READY 0x01
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