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Annotation of ntddk/src/scsi/atdisk/alpha/atd_plat.h, revision 1.1.1.1

1.1       root        1: /*++
                      2: 
                      3: Copyright (c) 1993  Microsoft Corporation
                      4: 
                      5: Module Name:
                      6: 
                      7:     mips\atd_plat.h
                      8: 
                      9: Abstract:
                     10: 
                     11:     This file includes mips platform-dependent declarations for the AT
                     12:     disk (aka ST506 and ISA standard hard disk) driver for NT.
                     13: 
                     14:     If this driver is ported to a different platform, this file (and
                     15:     atd_conf.h) will need to be modified extensively.  The build
                     16:     procedure should make sure that the proper version of this file is
                     17:     available as atd_plat.h (which is included by atdisk.c) when
                     18:     building for a specific platform.
                     19: 
                     20: Author:
                     21: 
                     22:     Chad Schwitters (chads) 21-Feb-1991.
                     23:     Mike Glass (mglass) 5-April-1993
                     24: 
                     25: Environment:
                     26: 
                     27:     Kernel mode only.
                     28: 
                     29: Notes:
                     30: 
                     31: Revision History:
                     32: 
                     33: --*/
                     34: 
                     35: //
                     36: // Macros to access the controller, which on the ix86 is in I/O space.
                     37: //
                     38: 
                     39: #define READ_CONTROLLER( Address )                                    \
                     40:     READ_PORT_UCHAR( (Address) )
                     41: 
                     42: #define READ_CONTROLLER_BUFFER( Address, Value, Length )              \
                     43:     READ_PORT_BUFFER_USHORT(                                          \
                     44:         ( PUSHORT )(Address),                                         \
                     45:         ( PUSHORT )(Value),                                           \
                     46:         ( ULONG )(Length) / 2 )
                     47: 
                     48: #define WRITE_CONTROLLER( Address, Value )                            \
                     49:     WRITE_PORT_UCHAR( (Address), ( UCHAR )(Value) )
                     50: 
                     51: #define WRITE_CONTROLLER_BUFFER( Address, Value, Length )             \
                     52:     WRITE_PORT_BUFFER_USHORT(                                         \
                     53:         ( PUSHORT )(Address),                                         \
                     54:         ( PUSHORT )(Value),                                           \
                     55:         ( ULONG )(Length) / 2 )
                     56: 
                     57: //
                     58: // ST506 register definitions, as offsets from a base (which should be
                     59: // passed in by configuration management).
                     60: //
                     61: 
                     62: #define DATA_REGISTER                0
                     63: #define WRITE_PRECOMP_REGISTER       1
                     64: #define ERROR_REGISTER               1
                     65: #define SECTOR_COUNT_REGISTER        2
                     66: #define SECTOR_NUMBER_REGISTER       3
                     67: #define CYLINDER_LOW_REGISTER        4
                     68: #define CYLINDER_HIGH_REGISTER       5
                     69: #define DRIVE_HEAD_REGISTER          6
                     70: #define COMMAND_REGISTER             7
                     71: #define STATUS_REGISTER              7
                     72: 
                     73: //
                     74: // In addition to I/O space access to the controller registers, ISA defines
                     75: // a separate "drive control" register.  Here's commands to send to that
                     76: // register.
                     77: //
                     78: 
                     79: #define RESET_CONTROLLER    0x04
                     80: #define ENABLE_INTERRUPTS   0x00
                     81: 

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