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1.1 ! root 1: /*++ ! 2: ! 3: Copyright (c) 1991, 1992 Microsoft Corporation ! 4: Copyright (c) 1992 Future Domain Corporation ! 5: ! 6: Module Name: ! 7: ! 8: fd8xx.h ! 9: ! 10: Abstract: ! 11: ! 12: Definitions for the Future Domain TMC-8XX SCSI controllers. ! 13: ! 14: Author: ! 15: ! 16: Bob Rinne (bobri - Microsoft) June 1991 ! 17: Roger Stoller (v-rogs - Future Domain) August 1992 ! 18: ! 19: Revision History: ! 20: ! 21: --*/ ! 22: ! 23: #include "scsi.h" ! 24: ! 25: // ! 26: // Size of memory mapped area used. ! 27: // ! 28: #define FD8XX_ADDRESS_SIZE 0x2000 ! 29: ! 30: // ! 31: // I/O Memory Map Interface. Offsets from BaseAddress referrences. ! 32: // ! 33: #define WRITE_CONTROL 0x1C00 ! 34: #define READ_STATUS 0x1C00 ! 35: #define WRITE_SCSI 0x1E00 ! 36: #define READ_SCSI 0x1E00 ! 37: ! 38: // ! 39: // Macros for accessing the control memory of the FD8XX. ! 40: // ! 41: #define FD8XX_SET_CONTROL(BASE, VALUE) \ ! 42: ScsiPortWriteRegisterUchar((BASE + WRITE_CONTROL), (VALUE)) ! 43: ! 44: #define FD8XX_READ_STATUS(BASE) \ ! 45: ScsiPortReadRegisterUchar(BASE + READ_STATUS) ! 46: ! 47: #define FD8XX_READ_ALTERNATE_STATUS(BASE, OFFSET) \ ! 48: ScsiPortReadRegisterUchar(BASE + (READ_STATUS + OFFSET)) ! 49: ! 50: #define FD8XX_WRITE_DATA(BASE, VALUE) \ ! 51: ScsiPortWriteRegisterUchar((BASE + WRITE_SCSI), (UCHAR) (VALUE)) ! 52: ! 53: #define FD8XX_READ_DATA(BASE) \ ! 54: ScsiPortReadRegisterUchar(BASE + READ_SCSI) ! 55: ! 56: #define FD8XX_READ_ALTERNATE_DATA(BASE, OFFSET) \ ! 57: ScsiPortReadRegisterUchar(BASE + READ_SCSI + OFFSET) ! 58: ! 59: // ! 60: // Control port output codes. ! 61: // ! 62: #define C_RESET 0x01 // Assert SCSI reset line ! 63: #define C_SELECT 0x02 // Assert SCSI select line ! 64: #define C_BUSY 0x04 // Assert SCSI busy line ! 65: #define C_ATTENTION 0x08 // Assert SCSI attention line ! 66: #define C_ARBITRATION 0x10 // Start arbitration ! 67: #define C_PARITY_ENABLE 0x20 // Parity enable ! 68: #define C_INT_ENABLE 0x40 // Enable interrupt ! 69: #define C_BUS_ENABLE 0x80 // Bus enable ! 70: ! 71: // ! 72: // Input status bit definitions. ! 73: // ! 74: #define S_BUSY 0x01 // Busy line from SCSI bus ! 75: #define S_MESSAGE 0x02 // Message line from SCSI bus ! 76: #define S_IO 0x04 // Input/Output line from SCSI bus ! 77: #define S_CD 0x08 // Command/Data line from SCSI bus ! 78: #define S_REQUEST 0x10 // Request line from SCSI bus ! 79: #define S_SELECT 0x20 // Select line from SCSI bus ! 80: #define S_PARITY 0x40 // Parity error status ! 81: #define S_ARB_COMPLETE 0x80 // Arbitration complete ! 82: ! 83: // ! 84: // Useful status combinations. ! 85: // ! 86: #define BP_BUS_FREE 0 ! 87: #define BP_COMMAND ( S_BUSY | S_CD | S_REQUEST ) ! 88: #define BP_MESSAGE_IN ( S_BUSY | S_MESSAGE | S_IO | S_CD | S_REQUEST ) ! 89: #define BP_MESSAGE_OUT ( S_BUSY | S_MESSAGE | S_CD | S_REQUEST ) ! 90: #define BP_DATA_IN ( S_BUSY | S_IO | S_REQUEST ) ! 91: #define BP_DATA_OUT ( S_BUSY | S_REQUEST ) ! 92: #define BP_STATUS ( S_BUSY | S_IO | S_CD | S_REQUEST ) ! 93: #define BP_RESELECT ( S_SELECT | S_IO ) ! 94: ! 95: // ! 96: // Status mask for bus phase. This is everything except Parity and ! 97: // Arbitration complete. ! 98: // ! 99: #define S_PHASE_MASK ((UCHAR) 0x3F) ! 100: ! 101: #define FD8XX_READ_PHASE(BASE) ((UCHAR) (FD8XX_READ_STATUS(BASE) & S_PHASE_MASK)) ! 102: ! 103: // ! 104: // Interrupt definition. ! 105: // ! 106: #define FD8XX_IDT_VECTOR 5 ! 107: ! 108: // ! 109: // SCSI source identifier for host system. ! 110: // ! 111: #define SCSI_INITIATOR_ID 7 ! 112: ! 113: // ! 114: // Various timeout values (in microseconds). ! 115: // ! 116: #define REQUEST_SPIN_WAIT 1000000 // Wait for target to assert REQUEST ! 117: #define RESET_HOLD_TIME 25 // Time to hold RESET line to reset bus ! 118: #define SELECTION_DELAY 100000 // Wait for target to assert BUSY ! 119: #define RESELECTION_WAIT 100000 // Wait for target to de-assert BUSY ! 120: #define ARBITRATION_DELAY 3 // Wait for arbitration complete ! 121: #define FD8xx_TIMER_VALUE 10000 // Time for timer to fire ! 122: ! 123: ! 124: // ! 125: // Various limits... ! 126: // ! 127: ! 128: // ! 129: // Number of adapters this driver will support. ! 130: // ! 131: #define MAX_ADAPTERS 4 ! 132: ! 133: // ! 134: // Actually there is no limit to the transfer size, but since the I/O area ! 135: // has to be mapped into memory for the transfer we restrict it to the ! 136: // number below. ! 137: // ! 138: #define MAX_TRANSFER_LENGTH ( 64 * 1024 ) ! 139: ! 140: // ! 141: // Size of the memory-mapped SCSI data register on the adapter. ! 142: // ! 143: #define MAX_BUFFER_LENGTH 0x200 ! 144: #define MAX_HEAD_LENGTH 0x10 ! 145: #define MAX_TAIL_LENGTH 0x01 ! 146: ! 147: // ! 148: // Number of times to attempt arbitration before giving up. ! 149: // ! 150: #define MAX_ARB_ATTEMPTS 150 ! 151: ! 152: #define min(l, r) (((l) < (r)) ? (l) : (r))
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