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1.1 root 1: /*++
2:
3: Copyright (c) 1990 Microsoft Corporation
4:
5: Module Name:
6:
7: ncr53c9x.h
8:
9: Abstract:
10:
11: The module defines the structures, defines and functions for the NCR 53c9x
12: family of host bus adapter chips.
13:
14: Author:
15:
16: Jeff Havens (jhavens) 28-Feb-1991
17:
18: Revision History:
19:
20: --*/
21:
22: #ifndef _NCR53C9X_
23: #define _NCR53C9X_
24:
25:
26: //
27: // Define SCSI Protocol Chip register format.
28: //
29:
30: #if defined(DECSTATION)
31:
32: typedef struct _SCSI_REGISTER {
33: UCHAR Byte;
34: UCHAR Fill[3];
35: } SCSI_REGISTER, *PSCSI_REGISTER;
36:
37: #else
38:
39: #define SCSI_REGISTER UCHAR
40:
41: #endif // DECSTATION
42:
43: //
44: // SCSI Protocol Chip Definitions.
45: //
46: // Define SCSI Protocol Chip Read registers structure.
47: //
48:
49: typedef struct _SCSI_READ_REGISTERS {
50: SCSI_REGISTER TransferCountLow;
51: SCSI_REGISTER TransferCountHigh;
52: SCSI_REGISTER Fifo;
53: SCSI_REGISTER Command;
54: SCSI_REGISTER ScsiStatus;
55: SCSI_REGISTER ScsiInterrupt;
56: SCSI_REGISTER SequenceStep;
57: SCSI_REGISTER FifoFlags;
58: SCSI_REGISTER Configuration1;
59: SCSI_REGISTER Reserved1;
60: SCSI_REGISTER Reserved2;
61: SCSI_REGISTER Configuration2;
62: SCSI_REGISTER Configuration3;
63: SCSI_REGISTER Configuration4;
64: SCSI_REGISTER TransferCountPage;
65: SCSI_REGISTER FifoBottem;
66: } SCSI_READ_REGISTERS, *PSCSI_READ_REGISTERS;
67:
68: //
69: // Define SCSI Protocol Chip Write registers structure.
70: //
71:
72: typedef struct _SCSI_WRITE_REGISTERS {
73: SCSI_REGISTER TransferCountLow;
74: SCSI_REGISTER TransferCountHigh;
75: SCSI_REGISTER Fifo;
76: SCSI_REGISTER Command;
77: SCSI_REGISTER DestinationId;
78: SCSI_REGISTER SelectTimeOut;
79: SCSI_REGISTER SynchronousPeriod;
80: SCSI_REGISTER SynchronousOffset;
81: SCSI_REGISTER Configuration1;
82: SCSI_REGISTER ClockConversionFactor;
83: SCSI_REGISTER TestMode;
84: SCSI_REGISTER Configuration2;
85: SCSI_REGISTER Configuration3;
86: SCSI_REGISTER Configuration4;
87: SCSI_REGISTER TransferCountPage;
88: SCSI_REGISTER FifoBottem;
89: } SCSI_WRITE_REGISTERS, *PSCSI_WRITE_REGISTERS;
90:
91: typedef union _SCSI_REGISTERS {
92: SCSI_READ_REGISTERS ReadRegisters;
93: SCSI_WRITE_REGISTERS WriteRegisters;
94: } SCSI_REGISTERS, *PSCSI_REGISTERS;
95:
96: //
97: // Define SCSI Command Codes.
98: //
99:
100: #define NO_OPERATION_DMA 0x80
101: #define FLUSH_FIFO 0x1
102: #define RESET_SCSI_CHIP 0x2
103: #define RESET_SCSI_BUS 0x3
104: #define TRANSFER_INFORMATION 0x10
105: #define TRANSFER_INFORMATION_DMA 0x90
106: #define COMMAND_COMPLETE 0x11
107: #define MESSAGE_ACCEPTED 0x12
108: #define TRANSFER_PAD 0x18
109: #define SET_ATTENTION 0x1a
110: #define RESET_ATTENTION 0x1b
111: #define RESELECT 0x40
112: #define SELECT_WITHOUT_ATTENTION 0x41
113: #define SELECT_WITH_ATTENTION 0x42
114: #define SELECT_WITH_ATTENTION_STOP 0x43
115: #define ENABLE_SELECTION_RESELECTION 0x44
116: #define DISABLE_SELECTION_RESELECTION 0x45
117: #define SELECT_WITH_ATTENTION3 0x46
118:
119: //
120: // Define SCSI Status Register structure.
121: //
122: typedef struct _SCSI_STATUS {
123: UCHAR Phase : 3;
124: UCHAR ValidGroup : 1;
125: UCHAR TerminalCount : 1;
126: UCHAR ParityError : 1;
127: UCHAR GrossError : 1;
128: UCHAR Interrupt : 1;
129: } SCSI_STATUS, *PSCSI_STATUS;
130:
131: //
132: // Define SCSI Phase Codes.
133: //
134:
135: #define DATA_OUT 0x0
136: #define DATA_IN 0x1
137: #define COMMAND_OUT 0x2
138: #define STATUS_IN 0x3
139: #define MESSAGE_OUT 0x6
140: #define MESSAGE_IN 0x7
141:
142: //
143: // Define SCSI Interrupt Register structure.
144: //
145:
146: typedef struct _SCSI_INTERRUPT {
147: UCHAR Selected : 1;
148: UCHAR SelectedWithAttention : 1;
149: UCHAR Reselected : 1;
150: UCHAR FunctionComplete : 1;
151: UCHAR BusService : 1;
152: UCHAR Disconnect : 1;
153: UCHAR IllegalCommand : 1;
154: UCHAR ScsiReset : 1;
155: } SCSI_INTERRUPT, *PSCSI_INTERRUPT;
156:
157: //
158: // Define SCSI Sequence Step Register structure.
159: //
160:
161: typedef struct _SCSI_SEQUENCE_STEP {
162: UCHAR Step : 3;
163: UCHAR MaximumOffset : 1;
164: UCHAR Reserved : 4;
165: } SCSI_SEQUENCE_STEP, *PSCSI_SEQUENCE_STEP;
166:
167: //
168: // Define SCSI Fifo Flags Register structure.
169: //
170:
171: typedef struct _SCSI_FIFO_FLAGS {
172: UCHAR ByteCount : 5;
173: UCHAR FifoStep : 3;
174: } SCSI_FIFO_FLAGS, *PSCSI_FIFO_FLAGS;
175:
176: //
177: // Define SCSI Configuration 1 Register structure.
178: //
179:
180: typedef struct _SCSI_CONFIGURATION1 {
181: UCHAR HostBusId : 3;
182: UCHAR ChipTestEnable : 1;
183: UCHAR ParityEnable : 1;
184: UCHAR ParityTestMode : 1;
185: UCHAR ResetInterruptDisable : 1;
186: UCHAR SlowCableMode : 1;
187: } SCSI_CONFIGURATION1, *PSCSI_CONFIGURATION1;
188:
189: //
190: // Define SCSI Configuration 2 Register structure.
191: //
192:
193: typedef struct _SCSI_CONFIGURATION2 {
194: UCHAR DmaParityEnable : 1;
195: UCHAR RegisterParityEnable : 1;
196: UCHAR TargetBadParityAbort : 1;
197: UCHAR Scsi2 : 1;
198: UCHAR HighImpedance : 1;
199: UCHAR EnableByteControl : 1;
200: UCHAR EnablePhaseLatch : 1;
201: UCHAR ReserveFifoByte : 1;
202: } SCSI_CONFIGURATION2, *PSCSI_CONFIGURATION2;
203:
204: //
205: // Define SCSI Configuration 3 Register structure.
206: //
207:
208: typedef struct _SCSI_CONFIGURATION3 {
209: UCHAR Threshold8 : 1;
210: UCHAR AlternateDmaMode : 1;
211: UCHAR SaveResidualByte : 1;
212: UCHAR FastClock : 1;
213: UCHAR FastScsi : 1;
214: UCHAR EnableCdb10 : 1;
215: UCHAR EnableQueue : 1;
216: UCHAR CheckIdMessage : 1;
217: } SCSI_CONFIGURATION3, *PSCSI_CONFIGURATION3;
218:
219: //
220: // Define SCSI Configuration 4 Register structure.
221: //
222:
223: typedef struct _SCSI_CONFIGURATION4 {
224: UCHAR ActiveNegation : 1;
225: UCHAR TestTransferCounter : 1;
226: UCHAR BackToBackTransfer : 1;
227: UCHAR Reserved : 5;
228: } SCSI_CONFIGURATION4, *PSCSI_CONFIGURATION4;
229:
230: //
231: // Define Emulex FAS 218 unique part Id code.
232: //
233:
234: typedef struct _NCR_PART_CODE {
235: UCHAR RevisionLevel : 3;
236: UCHAR ChipFamily : 5;
237: }NCR_PART_CODE, *PNCR_PART_CODE;
238:
239: #define EMULEX_FAS_216 2
240: #define NCR_53c96 0x14
241:
242: //
243: // SCSI Protocol Chip Control read and write macros.
244: //
245:
246: #if defined(DECSTATION)
247:
248: #define SCSI_READ(ChipAddr, Register) \
249: (READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register.Byte)))
250:
251: #define SCSI_WRITE(ChipAddr, Register, Value) \
252: WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register.Byte), (Value))
253:
254: #else
255:
256: #define SCSI_READ(ChipAddr, Register) \
257: (READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register)))
258:
259: #define SCSI_WRITE(ChipAddr, Register, Value) \
260: WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register), (Value))
261:
262: #endif
263:
264:
265: //
266: // Define SCSI Adapter Specific Read registers structure
267: //
268:
269: typedef struct _ADAPTER_READ_REGISTERS {
270: UCHAR Reserved00;
271: UCHAR Reserved01;
272: UCHAR OptionSelect1;
273: UCHAR OptionSelect2;
274: UCHAR Reserved04;
275: UCHAR OptionSelect5;
276: UCHAR Reserved06;
277: UCHAR Reserved07;
278: UCHAR Reserved08;
279: UCHAR Reserved09;
280: UCHAR Reserved0a;
281: UCHAR Reserved0b;
282: UCHAR DmaStatus;
283: UCHAR Reserved0d;
284: UCHAR Reserved0e;
285: UCHAR Reserved0f;
286: } ADAPTER_READ_REGISTERS, *PADAPTER_READ_REGISTERS;
287:
288: //
289: // Define SCSI Adapter Specific Write registers structure
290: //
291:
292: typedef struct _ADAPTER_WRITE_REGISTERS {
293: UCHAR Reserved00;
294: UCHAR Reserved01;
295: UCHAR OptionSelect1;
296: UCHAR OptionSelect2;
297: UCHAR Reserved04;
298: UCHAR OptionSelect5;
299: UCHAR Reserved06;
300: UCHAR Reserved07;
301: UCHAR Reserved08;
302: UCHAR Reserved09;
303: UCHAR DmaDecode;
304: UCHAR Reserved0b;
305: UCHAR Reserved0c;
306: UCHAR Reserved0d;
307: UCHAR Reserved0e;
308: UCHAR Reserved0f;
309: } ADAPTER_WRITE_REGISTERS, *PADAPTER_WRITE_REGISTERS;
310:
311:
312:
313: typedef union _ADAPTER_REGISTERS {
314: ADAPTER_READ_REGISTERS ReadRegisters;
315: ADAPTER_WRITE_REGISTERS WriteRegisters;
316: } ADAPTER_REGISTERS, *PADAPTER_REGISTERS;
317:
318:
319:
320: //
321: // Define Option Select Register structures.
322: //
323:
324: typedef struct _POS_DATA_1 {
325: UCHAR AdapterEnable : 1;
326: UCHAR IoAddressSelects : 3;
327: UCHAR InterruptSelects : 2;
328: UCHAR InterruptEnable : 1;
329: UCHAR Reserved : 1;
330: } POS_DATA_1, *PPOS_DATA_1;
331:
332: typedef struct _POS_DATA_2 {
333: UCHAR DmaSelects : 3;
334: UCHAR UnusedDmaSelect : 1;
335: UCHAR AdapterFairness : 1;
336: UCHAR PreemptCount : 2;
337: UCHAR DmaEnable : 1;
338: } POS_DATA_2, *PPOS_DATA_2;
339:
340: typedef struct _POS_DATA_3 {
341: UCHAR Reserved : 3;
342: UCHAR SramAddressSelects : 3; // 7f4c only
343: UCHAR HostIdSelects : 2; // 7f4c only
344: } POS_DATA_3, *PPOS_DATA_3;
345:
346: typedef struct _POS_DATA_4 {
347: UCHAR Reserved0 : 5;
348: UCHAR HostIdSelects : 1; // 7f4d & 7f4f only
349: UCHAR Reserved1 : 2;
350: } POS_DATA_4, *PPOS_DATA_4;
351:
352: //
353: // Define SCSI Dma Status Register structure.
354: //
355:
356: typedef struct _SCSI_DMA_STATUS {
357: UCHAR Interrupt : 1;
358: UCHAR DmaRequest : 1;
359: UCHAR Reserved : 6;
360: } SCSI_DMA_STATUS, *PSCSI_DMA_STATUS;
361:
362: //
363: // Adapter configuration Information.
364: //
365:
366: #define ONBOARD_C94_ADAPTER_ID 0x7f4c
367: #define ONBOARD_C90_ADAPTER_ID 0x7f4d
368: #define PLUGIN_C90_ADAPTER_ID 0x7f4f
369:
370: typedef struct _POS_DATA {
371: USHORT AdapterId;
372: UCHAR OptionData1;
373: UCHAR OptionData2;
374: UCHAR OptionData3;
375: UCHAR OptionData4;
376: } POS_DATA, *PPOS_DATA;
377:
378: typedef struct _INIT_DATA {
379: ULONG AdapterId;
380: ULONG CardSlot;
381: POS_DATA PosData[8];
382: }INIT_DATA, *PINIT_DATA;
383:
384: static const PVOID
385: AdapterBaseAddress[] = {
386: (PVOID) 0x0000,
387: (PVOID) 0x0240,
388: (PVOID) 0x0340,
389: (PVOID) 0x0400,
390: (PVOID) 0x0420,
391: (PVOID) 0x3240,
392: (PVOID) 0x8240,
393: (PVOID) 0xa240
394: };
395:
396: static const UCHAR
397: AdapterInterruptLevel[] = {
398: 0x03,
399: 0x05,
400: 0x07,
401: 0x09
402: };
403:
404: static const UCHAR
405: AdapterDmaLevel[] = {
406: 0x00,
407: 0x01,
408: 0x02, // invalid setting
409: 0x03,
410: 0x04, // invalid setting
411: 0x05,
412: 0x06,
413: 0x07
414: };
415:
416: static const UCHAR
417: AdapterScsiIdC90[] = {
418: 0x06,
419: 0x07
420: };
421:
422: static const UCHAR
423: AdapterScsiIdC94[] = {
424: 0x04,
425: 0x05,
426: 0x06,
427: 0x07
428: };
429:
430: #endif
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