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1.1 root 1: /******************************Module*Header*******************************\
2: * Module Name: S3.h
3: *
4: * All the S3 specific driver h file stuff
5: *
6: * Copyright (c) 1992 Microsoft Corporation
7: *
8: \**************************************************************************/
9:
10: #define CLIPOBJ_vGetrclBounds(pco, prcl) (*(prcl) = (pco)->rclBounds)
11: #define CLIPOBJ_vSetrclBounds(pco, prcl) ((pco)->rclBounds = *(prcl))
12:
13: #define CLIPOBJ_vGetDComplexity(pco) (*(pco)->iDComplexity)
14: #define CLIPOBJ_vSetDComplexity(pco, j) (*(pco)->iDComplexity = (j))
15:
16: #define CLIPOBJ_fjGetClipState(pco) ((pco)->ajPad)
17: #define CLIPOBJ_vSetClipState(pco, fj) ((pco)->ajPad == (fj))
18:
19: #define SURFOBJ_vGetpvScan0(pso, ppv) (*(ppv) = (pso)->pvScan0)
20: #define SURFOBJ_vSetpvScan0(pso, pv) ((pso)->pvScan0 = (pv))
21:
22:
23: // debug stuff
24:
25: #if 0
26:
27: #define LOG_OUTS 1
28:
29: #else
30:
31: #define CATCHIT_ON 1
32: #define CATCHIT (CATCHIT_ON && DBG)
33:
34: #endif
35:
36: // Porting stuff.
37:
38: #if !defined(i386)
39:
40: // The code makes extensive use of the inp, inpw, outp and outpw x86
41: // intrinsic functions. Since these don't exist on the Alpha platform,
42: // map them into something we can handle. Since the CSRs are mapped
43: // on Alpha, we have to add the register base to the register number
44: // passed in the source.
45:
46: #include "ioaccess.h"
47:
48: extern PUCHAR gpucCsrBase;
49:
50: #define inp(p) READ_PORT_UCHAR (gpucCsrBase + (p))
51: #define inpw(p) READ_PORT_USHORT ((PUSHORT)(gpucCsrBase + (p)))
52: #define outp(p,v) WRITE_PORT_UCHAR (gpucCsrBase + (p), (v))
53: #define outpw(p,v) WRITE_PORT_USHORT ((PUSHORT)(gpucCsrBase + (p)), (v))
54:
55:
56: #endif // !defined(i386)
57:
58:
59: #if CATCHIT
60:
61: VOID vCheckDataReady(PPDEV);
62: VOID vCheckDataComplete(PPDEV);
63:
64: #define CHECK_DATA_READY vCheckDataReady(ppdev)
65: #define CHECK_DATA_COMPLETE vCheckDataComplete(ppdev)
66:
67: VOID outpw_test(unsigned, unsigned);
68: VOID outp_test(unsigned, int);
69: BYTE inp_test(WORD);
70: WORD inpw_test(WORD);
71:
72: #define OUTPW(port, val) outpw_test(port, val)
73: #define OUTP(port, val) outp_test(port, val)
74: #define INPW(port) inpw_test(port)
75: #define INP(port) inp_test(port)
76:
77: #define OUTPW1(port, val) outpw(port, val)
78: #define OUTP1(port, val) outp(port, val)
79: #define INPW1(port) inpw(port)
80: #define INP1(port) inp(port)
81:
82: #else
83:
84: #define CHECK_DATA_READY
85: #define CHECK_DATA_COMPLETE
86:
87: #if LOG_OUTS
88:
89: VOID outpw_log(unsigned, unsigned);
90: VOID outp_log(unsigned, int);
91:
92: #define OUTPW(port, val) outpw_log(port, val)
93: #define OUTP(port, val) outp_log(port, val)
94: #define INPW(port) inpw(port)
95: #define INP(port) inp(port)
96:
97: #define OUTPW1(port, val) outpw_log(port, val)
98: #define OUTP1(port, val) outp_log(port, val)
99: #define INPW1(port) inpw(port)
100: #define INP1(port) inp(port)
101:
102: #else
103:
104: #define OUTPW(port, val) outpw(port, val)
105: #define OUTP(port, val) outp(port, val)
106: #define INPW(port) inpw(port)
107: #define INP(port) inp(port)
108:
109: #define OUTPW1(port, val) outpw(port, val)
110: #define OUTP1(port, val) outp(port, val)
111: #define INPW1(port) inpw(port)
112: #define INP1(port) inp(port)
113:
114: #endif
115: #endif
116:
117: #if LOG_OUTS
118:
119: #define TEST_928(s) \
120: if (INP1(0x3d4) == 0xff) \
121: { \
122: RIP(s); \
123: }
124:
125: #else
126:
127: #define TEST_928(s)
128:
129: #endif
130:
131: // S3 Chip equates.
132:
133: #define STATUS_1 0x3DA
134: #define VSY_NOT 0x08
135:
136: #define CRTC_INDEX 0x3D4
137: #define CRTC_DATA 0x3D5
138:
139: #define S3R8 0x38
140: #define S3R9 0x39
141: #define S3R1 0x31
142: #define S3R5 0x35
143:
144: #define CR39 0x39
145: #define CR4C 0x4C
146: #define CR4D 0x4D
147:
148: #define HGC_MODE 0x45
149: #define HGC_ENABLE 0x01
150: #define HGC_DISABLE 0x00
151:
152:
153: #define HGC_ORGX_LSB 0x47
154: #define HGC_ORGX_MSB 0x46
155: #define HGC_ORGY_LSB 0x49
156: #define HGC_ORGY_MSB 0x48
157:
158: #define HGC_DX 0x4E
159: #define HGC_DY 0x4F
160:
161:
162: #define REG_UNLOCK_1 0x48
163: #define CPUA_BASE 0X01
164:
165: #define SYSCTL_UNLOCK 0xA0
166: #define SYSCTL_LOCK 0x00
167:
168: #define SYS_CNFG 0x40
169: #define LAW_CTL 0x58
170: #define EX_SCTL_2 0x51
171: #define EX_DAC_CT 0x55
172:
173: #define MISC_1 0x3A
174:
175: // Brooktree 485 defines.
176:
177:
178: // Registers.
179:
180: #define BT485_ADDR_CMD_REG0 0x3c6
181: #define BT485_ADDR_CMD_REG1 0x3c8
182: #define BT485_ADDR_CMD_REG2 0x3c9
183: #define BT485_ADDR_CMD_REG3 0x3c6
184:
185:
186: #define BT485_CMD_REG_3_ACCESS 0x80
187:
188: #define BT485_ADDR_CUR_COLOR_WRITE 0x3c8
189: #define BT485_CUR_COLOR_DATA 0x3c9
190: #define BT485_ADDR_CUR_RAM_WRITE 0x3c8
191: #define BT485_CUR_RAM_ARRAY_DATA 0X3c7
192:
193:
194:
195: #define BT485_CURSOR_COLOR_1 0x1
196: #define BT485_CURSOR_COLOR_2 0x2
197:
198: #define BT485_CURSOR_X_LOW 0x3c8
199: #define BT485_CURSOR_X_HIGH 0x3c9
200:
201: #define BT485_CURSOR_Y_LOW 0x3c6
202: #define BT485_CURSOR_Y_HIGH 0x3c7
203:
204: // Commands.
205:
206: #define BT485_CURSOR_DISABLE (~0x03)
207: #define BT485_CURSOR_MODE2 0x02
208:
209: #define BT485_64X64_CURSOR 0x04
210:
211:
212: // Current position & source position registers.
213:
214: #define CUR_X ppdev->cur_x
215: #define CUR_Y ppdev->cur_y
216:
217: // Destination register.
218:
219: #define DEST_X ppdev->dest_x
220: #define DEST_Y ppdev->dest_y
221:
222: #define AXSTP ppdev->axstp
223: #define DIASTP ppdev->diastp
224:
225: #define RECT_WIDTH ppdev->rect_width
226: #define LINE_MAX ppdev->line_max
227:
228: #define ERR_TERM ppdev->err_term
229:
230: // Graphic Processor status and command registers.
231:
232: #define GP_STAT ppdev->gp_stat
233: #define CMD ppdev->cmd
234: #define SHORT_STROKE_REG ppdev->short_stroke_reg
235:
236: // Command Types
237:
238: #define NOP 0x0000
239: #define DRAW_LINE 0x2000
240: #define RECTANGLE_FILL 0x4000
241: #define BITBLT 0xC000
242:
243: #define BYTE_SWAP 0x1000
244: #define BUS_SIZE_16 0x0200
245: #define BUS_SIZE_8 0x0000
246: #define WAIT 0x0100
247:
248: // Drawing directions (radial)
249:
250: #define DRAWING_DIRECTION_0 0x0000
251: #define DRAWING_DIRECTION_45 0x0020
252: #define DRAWING_DIRECTION_90 0x0040
253: #define DRAWING_DIRECTION_135 0x0060
254: #define DRAWING_DIRECTION_180 0x0080
255: #define DRAWING_DIRECTION_225 0x00A0
256: #define DRAWING_DIRECTION_270 0x00C0
257: #define DRAWING_DIRECTION_315 0x00E0
258:
259: // Drawing directions (x/y)
260:
261: #define DRAWING_DIR_BTRLXM 0x0000
262: #define DRAWING_DIR_BTLRXM 0x0020
263: #define DRAWING_DIR_BTRLYM 0x0040
264: #define DRAWING_DIR_BTLRYM 0x0060
265: #define DRAWING_DIR_TBRLXM 0x0080
266: #define DRAWING_DIR_TBLRXM 0x00A0
267: #define DRAWING_DIR_TBRLYM 0x00C0
268: #define DRAWING_DIR_TBLRYM 0x00E0
269:
270: // Drawing Direction Bits
271:
272: #define PLUS_X 0x0020
273: #define PLUS_Y 0x0080
274: #define MAJOR_Y 0x0040
275:
276: // Draw
277:
278: #define DRAW 0x0010
279:
280: // Direction type
281:
282: #define DIR_TYPE_RADIAL 0x0008
283: #define DIR_TYPE_XY 0x0000
284:
285: // Last Pixel
286:
287: #define LAST_PIXEL_OFF 0x0004
288: #define LAST_PIXEL_ON 0x0000
289:
290: // Pixel Mode
291:
292: #define MULTIPLE_PIXELS 0x0002
293: #define SINGLE_PIXEL 0x0000
294:
295: // Read/Write
296:
297: #define READ 0x0000
298: #define WRITE 0x0001
299:
300:
301: // G.P. Status
302:
303: #define HARDWARE_BUSY 0x200
304: #define READ_DATA_AVAILABLE 0x100
305:
306: // Fifo Status
307:
308: #define FIFO_7_STATUS 0x080
309: #define FIFO_6_STATUS 0x040
310: #define FIFO_5_STATUS 0x020
311: #define FIFO_4_STATUS 0x010
312: #define FIFO_3_STATUS 0x008
313: #define FIFO_2_STATUS 0x004
314: #define FIFO_1_STATUS 0x002
315: #define FIFO_0_STATUS 0x001
316:
317: // Fifo status in terms of empty entries
318:
319: #define FIFO_1_EMPTY FIFO_7_STATUS
320: #define FIFO_2_EMPTY FIFO_6_STATUS
321: #define FIFO_3_EMPTY FIFO_5_STATUS
322: #define FIFO_4_EMPTY FIFO_4_STATUS
323: #define FIFO_5_EMPTY FIFO_3_STATUS
324: #define FIFO_6_EMPTY FIFO_2_STATUS
325: #define FIFO_7_EMPTY FIFO_1_STATUS
326: #define FIFO_8_EMPTY FIFO_0_STATUS
327:
328: // These are the defines for the multifunction control register.
329: // The 4 MSBs define the function of the register.
330:
331: #define MULTIFUNC_CNTL ppdev->multifunc_cntl
332:
333: #define RECT_HEIGHT 0x0000
334:
335: #define CLIP_TOP 0x1000
336: #define CLIP_LEFT 0x2000
337: #define CLIP_BOTTOM 0x3000
338: #define CLIP_RIGHT 0x4000
339:
340: #define DATA_EXTENSION 0xA000
341: #define ALL_ONES 0x0000
342: #define CPU_DATA 0x0080
343: #define DISPLAY_MEMORY 0x00C0
344:
345: // Foreground & Background Color Registers.
346:
347: #define BKGD_COLOR ppdev->bkgd_color
348: #define FRGD_COLOR ppdev->frgd_color
349:
350: // Foreground & Background Mix register defines.
351:
352: // Registers
353:
354: #define BKGD_MIX ppdev->bkgd_mix
355: #define FRGD_MIX ppdev->frgd_mix
356:
357: // Color source
358:
359: #define BACKGROUND_COLOR 0x00
360: #define FOREGROUND_COLOR 0x20
361: #define SRC_CPU_DATA 0x40
362: #define SRC_DISPLAY_MEMORY 0x60
363:
364: // Mix modes
365:
366: #define NOT_SCREEN 0x00
367: #define LOGICAL_0 0x01
368: #define LOGICAL_1 0x02
369: #define LEAVE_ALONE 0x03
370: #define NOT_NEW 0x04
371: #define SCREEN_XOR_NEW 0x05
372: #define NOT_SCREEN_XOR_NEW 0x06
373: #define OVERPAINT 0x07
374: #define NOT_SCREEN_OR_NOT_NEW 0x08
375: #define SCREEN_OR_NOT_NEW 0x09
376: #define NOT_SCREEN_OR_NEW 0x0A
377: #define SCREEN_OR_NEW 0x0B
378: #define SCREEN_AND_NEW 0x0C
379: #define NOT_SCREEN_AND_NEW 0x0D
380: #define SCREEN_AND_NOT_NEW 0x0E
381: #define NOT_SCREEN_AND_NOT_NEW 0x0F
382:
383: // Read and write masks
384:
385: #define WRT_MASK ppdev->wrt_mask
386: #define RD_MASK ppdev->rd_mask
387:
388: // Data port
389:
390: #define PIXEL_TRANSFER ppdev->pixel_transfer
391:
392: // General purpose support routines & macros.
393:
394: #define FIFOWAIT(level) while (INPW(GP_STAT) & level);
395:
396: #define GPWAIT() while (INPW(GP_STAT) & HARDWARE_BUSY);
397:
398: // 801/805/928 specific macros.
399:
400: #define ENABLE_DIRECT_ACCESS \
401: if (ppdev->bNewBankControl) \
402: { \
403: TEST_928 ("S3.DLL!pre enable direct access 928 failure\n"); \
404: while (inpw(GP_STAT) & 0x200); \
405: OUTPW1(CRTC_INDEX, (ppdev->SysCnfg | 0x0800)); \
406: OUTPW1(CRTC_INDEX, (ppdev->LawCtl | 0x1000)); \
407: TEST_928 ("S3.DLL!post enable direct access 928 failure\n");\
408: }
409:
410:
411: #define ENABLE_S3_ENGINE \
412: if (ppdev->bNewBankControl) \
413: { \
414: TEST_928 ("S3.DLL!pre enable S3 engine 928 failure\n"); \
415: OUTPW1(CRTC_INDEX, ppdev->LawCtl); \
416: OUTPW1(CRTC_INDEX, (ppdev->SysCnfg | 0x0100)); \
417: TEST_928 ("S3.DLL!post enable S3 engine 928 failure\n"); \
418: }
419:
420: VOID vSetS3ClipRect(PPDEV ppdev, PRECTL prclClip);
421: VOID vResetS3Clipping(PPDEV ppdev);
422:
423: VOID vDataPortOut (PPDEV ppdev, PWORD pw, UINT count);
424: VOID vDataPortOutB(PPDEV ppdev, PBYTE pb, UINT count);
425: VOID vDataPortIn (PPDEV ppdev, PWORD pw, UINT count);
426: VOID vDataPortInB (PPDEV ppdev, PBYTE pb, UINT count);
427:
428: // Shadow macros
429:
430: #define TEST_AND_SET_FRGD_MIX(val) \
431: if (val != ppdev->ForegroundMix) \
432: { \
433: ppdev->ForegroundMix = val; \
434: OUTPW(FRGD_MIX, val); \
435: }
436:
437: #define TEST_AND_SET_BKGD_MIX(val) \
438: if (val != ppdev->BackgroundMix) \
439: { \
440: ppdev->BackgroundMix = val; \
441: OUTPW(BKGD_MIX, val); \
442: }
443:
444: #define TEST_AND_SET_FRGD_COLOR(val) \
445: if (val != ppdev->ForegroundColor) \
446: { \
447: ppdev->ForegroundColor = val; \
448: OUTPW(FRGD_COLOR, val); \
449: }
450:
451: #define TEST_AND_SET_BKGD_COLOR(val) \
452: if (val != ppdev->BackgroundColor) \
453: { \
454: ppdev->BackgroundColor = val; \
455: OUTPW(BKGD_COLOR, val); \
456: }
457:
458: #define TEST_AND_SET_WRT_MASK(val) \
459: if (val != ppdev->WriteMask) \
460: { \
461: ppdev->WriteMask = val; \
462: OUTPW(WRT_MASK, val); \
463: }
464:
465: #define TEST_AND_SET_RD_MASK(val) \
466: if (val != ppdev->ReadMask) \
467: { \
468: ppdev->ReadMask = val; \
469: OUTPW(RD_MASK, val); \
470: }
471:
472: #define SET_FRGD_MIX(val) \
473: { \
474: ppdev->ForegroundMix = val; \
475: OUTPW(FRGD_MIX, val); \
476: }
477:
478: #define SET_BKGD_MIX(val) \
479: { \
480: ppdev->BackgroundMix = val; \
481: OUTPW(BKGD_MIX, val); \
482: }
483:
484: #define SET_FRGD_COLOR(val) \
485: { \
486: ppdev->ForegroundColor = val; \
487: OUTPW(FRGD_COLOR, val); \
488: }
489:
490: #define SET_BKGD_COLOR(val) \
491: { \
492: ppdev->BackgroundColor = val; \
493: OUTPW(BKGD_COLOR, val); \
494: }
495:
496: #define SET_WRT_MASK(val) \
497: { \
498: ppdev->WriteMask = val; \
499: OUTPW(WRT_MASK, val); \
500: }
501:
502: #define SET_RD_MASK(val) \
503: { \
504: ppdev->ReadMask = val; \
505: OUTPW(RD_MASK, val); \
506: }
507:
508:
509:
510: #define SCRN_TO_SCRN_CPY 0x01
511: #define SOLID_PATTERN 0x02
512: #define BRUSH_PATTERN 0x04
513: #define BLACK_AND_WHITE 0x08
514: #define HOST_TO_SCRN_CPY 0x10
515:
516: // Clipping Control Stuff
517:
518: typedef struct {
519: ULONG c;
520: RECTL arcl[8];
521: } ENUMRECTS8;
522:
523: typedef ENUMRECTS8 *PENUMRECTS8;
524:
525: typedef struct {
526: ULONG c;
527: TRAPEZOID atrap[8];
528: } ENUMTRAPS8;
529:
530: typedef ENUMTRAPS8 *PENUMTRAPS8;
531:
532: #define MAX_DDA_RECTS 40 // most rects we want enumerated by DDAOBJ at once
533:
534: typedef struct _DDAENUM
535: {
536: LONG yTop;
537: LONG yBottom;
538: LONG axPairs[MAX_DDA_RECTS];
539: } DDAENUM;
540:
541: BOOL bIntersectTest(PRECTL prcl1, PRECTL prcl2);
542: BOOL bTrivialAcceptTest(PRECTL prcl1, PRECTL prcl2);
543:
544: // ROP translation stuff.
545:
546: extern BYTE Rop2ToS3Rop[];
547:
548: // Full screen support stuff
549:
550: VOID vSaveOffScreenMemory(PPDEV);
551: VOID vRestoreOffScreenMemory(PPDEV);
552:
553: // SaveScreenBits and source bitmap cache stuff.
554:
555: BOOL bMoveSaveScreenBitsToHost(PPDEV ppdev, PSAVEDSCRNBITS *ppssbNewNode);
556:
557: // Hooks and Driver function table.
558:
559: #define HOOKS_BMF8BPP (HOOK_BITBLT | HOOK_TEXTOUT | HOOK_FILLPATH | \
560: HOOK_COPYBITS | HOOK_STROKEPATH | HOOK_PAINT)
561:
562: #define HOOKS_BMF16BPP 0
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