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1.1 root 1: page ,132
2: ;-----------------------------Module-Header-----------------------------;
3: ; Module Name: EGAVGA.INC
4: ;
5: ; This file contains the external definitions of the EGA/VGA specific
6: ; locations which driver output routines need to reference.
7: ;
8: ; Copyright (c) 1992 Microsoft Corporation
9: ;-----------------------------------------------------------------------;
10: ; Restrictions:
11: ;
12: ; The following rules apply to the use of the EGA/VGA registers
13: ; for the drivers (excluding pointer code and state detection
14: ; code):
15: ;
16: ;
17: ; 1) Routines are allowed to alter the following registers:
18: ;
19: ; Sequencer:
20: ;
21: ; SEQ_DATA SEQ_MAP_MASK
22: ;
23: ; Graphics Controller:
24: ;
25: ; GRAF_ADDR
26: ; GRAF_DATA GRAF_DATA_ROT
27: ; GRAF_SET_RESET GRAF_READ_MAP
28: ; GRAF_ENAB_SR GRAF_MODE
29: ; GRAF_COL_COMP GRAF_BIT_MASK
30: ;
31: ;
32: ; 2) The following registers will always contain the indicated
33: ; value. Routines are not allowed to alter them:
34: ;
35: ; Sequencer:
36: ;
37: ; SEQ_ADDR set to point SEQ_MAP_MASK
38: ;
39: ; Graphics Controller:
40: ;
41: ; GRAF_CDC set appropriately for color model
42: ;
43: ;
44: ; 3) Rotation counts for GRAF_DATA_ROT are not allowed.
45: ;
46: ;
47: ; 4) The following EGA/VGA registers will contain the indicated
48: ; value upon entry to a routine. Any routine which alters
49: ; them must restore them to the indicated state.
50: ;
51: ; Map Mask all planes enabled
52: ; Enable Set/Reset all planes disabled
53: ; Data Rotate Set, no rotation
54: ; Mode Processor write, data read
55: ; Bit Mask all bits enabled
56: ;
57: ;
58: ; 5) The Mode Register is always shadowed in EGA/VGA memory for
59: ; the state detection code. At interrupt time, the mode
60: ; will be restored from the structure "shadowed_graf_mode".
61: ; Any routine altering the Mode Register must keep this location
62: ; current. This is the only EGA/VGA register which requires
63: ; shadowing.
64: ;
65: ;
66: ; 6) Pointer drawing will save and restore the contents of
67: ; the processor latches.
68: ;
69: ;
70: ; 7) Pointer drawing will leave GRAF_ADDR set to GRAF_BIT_MASK.
71: ;
72: ;-----------------------------------------------------------------------;
73:
74: include i386\driver.inc
75:
76: ; Miscellaneous Registers used only at EGA/VGA initialization time
77:
78: MISC_OUTPUT EQU 0C2h ;Miscellaneous Output Register
79: CRTC_ADDR EQU 0D4h ;CRTC Address Register for color mode
80: CRTC_DATA EQU 0D5h ;CRTC Data Register for color mode
81: GRAF_1_POS EQU 0CCh ;Graphics 1 Address Register
82: GRAF_2_POS EQU 0CAh ;Graphics 2 Address Register
83: ATTR_READ EQU 0DAh ;Attribute Controler Read Address
84: ATTR_WRITE EQU 0C0h ;Attribute Controler Write Address
85: IN_STAT_0 EQU 0C2h ;Input Status Register 0
86: IN_STAT_1 EQU 0DAh ;Input Status Register 1
87:
88:
89:
90: ; EGA/VGA Register Definitions.
91: ;
92: ; The following definitions are the EGA/VGA registers and values
93: ; used by this driver. All other registers are set up at
94: ; when the EGA/VGA is placed into graphics mode and never altered
95: ; afterwards.
96: ;
97: ; All unspecified bits in the following registers must be 0.
98:
99:
100: EGA_BASE EQU 300h ;Base address of the EGA (3xx)
101: VGA_BASE EQU 300h ;Base address of the VGA (3xx)
102:
103:
104:
105: ; EGA/VGA Register Definitions.
106:
107: EGA_BASE EQU 300h ;Base address of the EGA (3xx)
108: VGA_BASE EQU 300h ;Base address of the VGA (3xx)
109:
110: ; SEQUencer Registers Used
111:
112: SEQ_ADDR EQU 0C4h ;SEQUencer Address Register
113: SEQ_DATA EQU 0C5h ;SEQUencer Data Register
114:
115: SEQ_MAP_MASK EQU 02h ;Write Plane Enable Mask
116: MM_C0 EQU 00000001b ; C0 plane enable
117: MM_C1 EQU 00000010b ; C1 plane enable
118: MM_C2 EQU 00000100b ; C2 plane enable
119: MM_C3 EQU 00001000b ; C3 plane enable
120: MM_ALL EQU 00001111b ; All planes
121:
122: SEQ_MODE EQU 04h ;Memory Mode
123: SM_ALPHA EQU 00000001b ; Char map select enable
124: SM_EXTENDED EQU 00000010b ; Extended memory present
125: SM_ODD_PLANE EQU 00000100b ; Odd/even bytes to same plane
126:
127:
128: ; Graphics Controller Registers Used
129:
130: GRAF_ADDR EQU 0CEh ;Graphics Controller Address Register
131: GRAF_DATA EQU 0CFh ;Graphics Controller Data Register
132:
133: GRAF_SET_RESET EQU 00h ; Set/Reset Plane Color
134: GRAF_ENAB_SR EQU 01h ; Set/Reset Enable
135: GRAF_COL_COMP EQU 02h ; Color Compare Register
136:
137: GRAF_DATA_ROT EQU 03h ; Data Rotate Register
138: DR_ROT_CNT EQU 00000111b ; Data Rotate Count
139: DR_SET EQU 00000000b ; Data Unmodified
140: DR_AND EQU 00001000b ; Data ANDed with latches
141: DR_OR EQU 00010000b ; Data ORed with latches
142: DR_XOR EQU 00011000b ; Data XORed with latches
143:
144: GRAF_READ_MAP EQU 04h ; Read Map Select Register
145: RM_C0 EQU 00000000b ; Read C0 plane
146: RM_C1 EQU 00000001b ; Read C1 plane
147: RM_C2 EQU 00000010b ; Read C2 plane
148: RM_C3 EQU 00000011b ; Read C3 plane
149:
150: GRAF_MODE EQU 05h ; Mode Register
151: M_PROC_WRITE EQU 00000000b ; Write processor data rotated
152: M_LATCH_WRITE EQU 00000001b ; Write latched data
153: M_COLOR_WRITE EQU 00000010b ; Write processor data as color
154: M_AND_WRITE EQU 00000011b ; Write (procdata AND bitmask)
155: M_DATA_READ EQU 00000000b ; Read selected plane
156: M_COLOR_READ EQU 00001000b ; Read color compare
157:
158: GRAF_MISC EQU 06h ; Miscellaneous Register
159: MS_NON_ALPHA EQU 00000001b ; Char generator disabled
160: MS_ODD_EVEN EQU 00000010b ; Map odd addresses to even
161: MS_A0000_128K EQU 00000000b ; Memory present at A0000, 128kb
162: MS_A0000_64K EQU 00000100b ; Memory present at A0000, 64kb
163: MS_B0000_32K EQU 00001000b ; Memory present at B0000, 32kb
164: MS_B8000_32K EQU 00001100b ; Memory present at B8000, 32kb
165: MS_ADDR_MASK EQU 00001100b
166:
167: GRAF_CDC EQU 07h ; Color Don't Care Register
168: GRAF_BIT_MASK EQU 08h ; Bit Mask Register
169:
170:
171: ; Various sizes for EGA/VGA data structures
172:
173: ;-----------------------------------------------------------------------;
174: ; On the EGA/VGA, the number of bits/pel is 4
175: ; The number of bytes per scan is 80
176: ;-----------------------------------------------------------------------;
177:
178: BITS_PEL EQU 4
179:
180: ;-----------------------------------------------------------------------;
181: ; Helper flags for the xyCreateMasks call
182: ;-----------------------------------------------------------------------;
183:
184: PTRI_INVERT EQU 1 ; !!! In WINGDIP.H when H2INC works
185: PTRI_ANIMATE EQU 2 ; !!! In WINGDIP.H when H2INC works
186:
187: ;-----------------------------------------------------------------------;
188: ; The pointer parameters are the size of the pointer as received from
189: ; DeviceSetCursor.
190: ;-----------------------------------------------------------------------;
191:
192: PTR_HEIGHT EQU 32
193: PTR_WIDTH EQU 4 ;Width in bytes of pointer
194: PTR_WIDTH_BITS EQU PTR_WIDTH*8 ;Width in bits of pointer
195:
196: ;-----------------------------------------------------------------------;
197: ; The work width/height is the size of a pointer as manipulated by
198: ; the pointer drawing code.
199: ;-----------------------------------------------------------------------;
200:
201: WORK_WIDTH EQU PTR_WIDTH+1 ;Width of mask, work area
202: WORK_HEIGHT EQU PTR_HEIGHT+0 ;Height of mask, work area
203: MASK_LENGTH EQU WORK_WIDTH*WORK_HEIGHT ;#bytes in mask, work area
204: CLR_MASK_LENGTH EQU WORK_WIDTH*WORK_HEIGHT*BITS_PEL ;#bytes in color mask
205: .errnz BITS_PEL-4
206:
207: ;-----------------------------------------------------------------------;
208: ; The save area parameters control the size of the buffer used for
209: ; saveing the bits underneath the pointer image. It should be a
210: ; power of two to allow for easy wrap calculations.
211: ;-----------------------------------------------------------------------;
212:
213: SAVE_BUFFER_WIDTH EQU 8 ;Width of the save area
214: SAVE_BUFFER_HEIGHT EQU 32 ;Height of the save area
215: .errnz PTR_WIDTH GT SAVE_BUFFER_WIDTH
216: .errnz PTR_HEIGHT GT SAVE_BUFFER_HEIGHT
217:
218:
219:
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