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1.1 root 1: /******************************Module*Header*******************************\
2: * Module Name: xga.h
3: *
4: * All the XGA specific driver h file stuff
5: *
6: * Copyright (c) 1992 Microsoft Corporation
7: *
8: \**************************************************************************/
9:
10:
11: //
12: // XGA I/O register definitions
13: //
14:
15: #define OP_MODE_REG 0x0
16: #define APP_CTL_REG 0x1
17: #define INT_ENABLE_REG 0x4
18: #define INT_STATUS_REG 0x5
19: #define VMEM_CONTROL_REG 0x6
20: #define APP_INDEX_REG 0x8
21: #define MEMACC_MODE_REG 0x9
22: #define INDEX_REG 0xA
23: #define DATA_IN_REG 0xB
24: #define DATA_OUT_REG 0xC
25:
26: //
27: // XGA Pointer (cursor) specific registers
28: //
29:
30: #define SPRITE_HORZ_START_LOW 0x30
31: #define SPRITE_HORZ_START_HIGH 0x31
32: #define SPRITE_HORZ_PRESET 0x32
33:
34: #define SPRITE_VERT_START_LOW 0x33
35: #define SPRITE_VERT_START_HIGH 0x34
36: #define SPRITE_VERT_PRESET 0x35
37:
38: #define SPRITE_CONTROL 0x36
39: #define SC 0x01
40:
41: #define SPRITE_COLOR_REG0_RED 0x38
42: #define SPRITE_COLOR_REG0_GREEN 0x39
43: #define SPRITE_COLOR_REG0_BLUE 0x3a
44:
45: #define SPRITE_COLOR_REG1_RED 0x3b
46: #define SPRITE_COLOR_REG1_GREEN 0x3c
47: #define SPRITE_COLOR_REG1_BLUE 0x3d
48:
49: #define SPRITE_INDEX_LOW 0x60
50: #define SPRITE_INDEX_HIGH 0x61
51: #define SPRITE_DATA 0x6a
52:
53: // XGA Chip Stuff
54:
55: // Start of Pel Operation Register defines
56:
57: #define BS_BACK_COLOR 0x00000000 // Background source
58: #define BS_SRC_PEL_MAP 0x80000000
59:
60: #define FS_FORE_COLOR 0x00000000 // Foreground source
61: #define FS_SRC_PEL_MAP 0x20000000
62:
63: #define STEP_DRAW_AND_STEP_READ 0x02000000 // Step Control
64: #define STEP_LINE_DRAW_READ 0x03000000
65: #define STEP_DRAW_AND_STEP_WRITE 0x04000000
66: #define STEP_LINE_DRAW_WRITE 0x05000000
67: #define STEP_PX_BLT 0x08000000
68: #define STEP_INVERTING_PX_BLT 0x09000000
69: #define STEP_AREA_FILL_PX_BLT 0x0A000000
70:
71: #define SRC_PEL_MAP_A 0x00100000 // Source Bitmap
72: #define SRC_PEL_MAP_B 0x00200000
73: #define SRC_PEL_MAP_C 0x00300000
74:
75: #define DST_PEL_MAP_A 0x00010000 // Dest Bitmap
76: #define DST_PEL_MAP_B 0x00020000
77: #define DST_PEL_MAP_C 0x00030000
78:
79: #define PATT_PEL_MAP_A 0x00001000 // Pattern Bitmap
80: #define PATT_PEL_MAP_B 0x00002000
81: #define PATT_PEL_MAP_C 0x00003000
82: #define PATT_FOREGROUND 0x00008000
83: #define PATT_GEN_FROM_SRC 0x00009000
84:
85: #define MSK_DISABLE 0x00000000 // Mask (clipping)
86: #define MSK_BOUNDARY_ENABLE 0x00000040
87: #define MSK_MAP_ENABLE 0x00000080
88:
89: #define DM_ALL_PELS 0x00000000 // Display modes
90: #define DM_FIRST_PEL_NULL 0x00000010
91: #define DM_LAST_PEL_NULL 0x00000020
92: #define DM_AREA_BOUNDARY 0x00000030
93:
94: #define OCT_DX 0x00000004 // Octants
95: #define OCT_DY 0x00000002
96: #define OCT_DZ 0x00000001
97:
98: // End of Pel Operation Register defines
99:
100: #define MASK_MAP 0x00 // Pel Map Index (PMI) values
101: #define PEL_MAP_A 0x01
102: #define PEL_MAP_B 0x02
103: #define PEL_MAP_C 0x03
104:
105: #define PO_INTEL 0x00 // Pel Order (PO) values
106: #define PO_MOTOROLA 0x08
107:
108: #define PS_1_BIT 0x00 // Pel Size (PS) values
109: #define PS_2_BIT 0x01
110: #define PS_4_BIT 0x02
111: #define PS_8_BIT 0x03
112:
113: #define PEL_MAP_FORMAT (PO_INTEL | PS_8_BIT)
114: #define PATT_MAP_FORMAT (PO_MOTOROLA | PS_1_BIT)
115:
116: #define XGA_0 0x00 // XGA Mix functions
117: #define XGA_S_AND_D 0x01
118: #define XGA_S_AND_NOT_D 0x02
119: #define XGA_S 0x03
120: #define XGA_NOT_S_AND_D 0x04
121: #define XGA_D 0x05
122: #define XGA_S_XOR_D 0x06
123: #define XGA_S_OR_D 0x07
124: #define XGA_NOT_S_AND_NOT_D 0x08
125: #define XGA_S_XOR_NOT_D 0x09
126: #define XGA_NOT_D 0x0A
127: #define XGA_S_OR_NOT_D 0x0B
128: #define XGA_NOT_S 0x0C
129: #define XGA_NOT_S_OR_D 0x0D
130: #define XGA_NOT_S_OR_NOT_D 0x0E
131: #define XGA_1 0x0F
132: #define XGA_MAX 0x10
133: #define XGA_MIN 0x11
134: #define XGA_ADD_WITH_SATURATE 0x12
135: #define XGA_SUBTRACT_D_MINUS_S_WITH_SATURATE 0x13
136: #define XGA_SUBTRACT_S_MINUS_D_WITH_SATURATE 0x14
137: #define XGA_AVERAGE 0x15
138:
139: #define CCCC_TRUE 0x0 // Color Compare Condition codes
140: #define CCCC_DD_GT_CCV 0x1
141: #define CCCC_DD_EQ_CCV 0x2
142: #define CCCC_DD_LT_CCV 0x3
143: #define CCCC_FALSE 0x4
144: #define CCCC_DD_GT_EQ_CCV 0x5
145: #define CCCC_DD_NOT_EQ_CCV 0x6
146: #define CCCC_DD_LT_EQ_CCV 0x7
147:
148:
149: extern VOID vWaitForCoProcessor(PPDEV ppdev, ULONG ulDelay) ;
150:
151: extern BOOL bSetXgaClipping(PPDEV ppdev, CLIPOBJ *pco, PULONG pulXgaMask) ;
152:
153: // Acceleration Control.
154:
155: #define CACHED_FONTS 0x1
156:
157: #define SCRN_TO_SCRN_CPY 0x01
158: #define SOLID_PATTERN 0x02
159:
160: #define XGA_ZERO_INIT 0x1
161: #define XGA_LOCK_MEM 0x2
162:
163: extern HANDLE hCpAlloc(PPDEV ppdev, ULONG nSize, ULONG ulFlags) ;
164: extern HANDLE hCpFree(PPDEV ppdev, HANDLE hXgaMem) ;
165: extern PVOID pCpMemLock(PPDEV ppdev, HANDLE hXgaMem, ULONG ulFlags) ;
166: extern BOOL bCpMemUnLock(PPDEV ppdev, HANDLE hXgaMem) ;
167: extern BOOL bCpMmInitHeap(PPDEV ppdev) ;
168: extern BOOL bCpMmDestroyHeap(PPDEV ppdev) ;
169:
170:
171: // BitBlt stuff
172:
173: // Define the A vector polynomial bits
174: //
175: // Each bit corresponds to one of the terms in the polynomial
176: //
177: // Rop(D,S,P) = a + a D + a S + a P + a DS + a DP + a SP + a DSP
178: // 0 d s p ds dp sp dsp
179:
180: #define AVEC_NOT 0x01
181: #define AVEC_D 0x02
182: #define AVEC_S 0x04
183: #define AVEC_P 0x08
184: #define AVEC_DS 0x10
185: #define AVEC_DP 0x20
186: #define AVEC_SP 0x40
187: #define AVEC_DSP 0x80
188:
189: #define AVEC_NEED_SOURCE (AVEC_S | AVEC_DS | AVEC_SP | AVEC_DSP)
190: #define AVEC_NEED_PATTERN (AVEC_P | AVEC_DP | AVEC_SP | AVEC_DSP)
191:
192:
193: // Hooks and Driver function table.
194:
195: #define HOOKS_BMF8BPP (HOOK_BITBLT | HOOK_TEXTOUT | \
196: HOOK_COPYBITS | HOOK_STROKEPATH | HOOK_PAINT)
197: #define HOOKS_BMF16BPP 0
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